JP2762855B2 - Frame synchronization protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization protection circuit, and more particularly, to a frame synchronization protection circuit applied to a receiver of a synchronous data transmission system.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional frame synchronization protection circuit. Here, data Si is 1 ms
A complete pattern detector 1 which detects a 16-bit frame synchronization pattern included in the period and sends out a detection pulse Pd when all bits match a predetermined pattern, and a synchronization pulse Ps synchronized with the received frame synchronization pattern A coincidence detector 4 for outputting a coincidence pulse K1 when the timing is coincident by comparing the detected frame Pd with the synchronizing pulse Ps;
A coincidence counter 7 that counts 1; a correlation pattern detector 2 that sends out a detection pulse Pe when the frame synchronization pattern included in the data Si matches, for example, 12 bits or more out of 16 bits, assuming frame synchronization; Inverter 3 for inverting detection pulse Pe to generate detection pulse Pf
To detect the non-coincidence pulse K2 when the detection pulse Pf is compared with the synchronization pulse Ps, and to output the non-coincidence pulse K2; Flip-flop 9 and AND gate 11 provided in
And an OR gate 10 provided for resetting the match counter 7 and the mismatch counter 8 and the flip-flop 9.

Next, the operation will be described.

The coincidence counter 7 sends a coincidence determination signal C1 to the OR gate 10 when the coincidence pulse K1 is counted up to three times, for example. The OR gate 10 resets the match counter 7, the mismatch counter 8 and the flip-flop 9 by a reset signal R2. Further, the mismatch counter 8 sends the mismatch determination signal C2 and sets the flip-flop 9 when the mismatch pulse K2 is counted up to, for example, eight times.

Here, the coincidence counter 7 and the non-coincidence counter 8 compete with each other. If the coincidence counter 7 has counted three times before the non-coincidence counter 8 has counted eight times, the non-coincidence counter 8 is reset. Being synchronized is protected. On the other hand, if the non-coincidence counter 8 counts eight times first, the synchronization protection is lost and the flip-flop 9 is set. Next, the AND gate 11 sends out a reset signal R1 in response to the detection pulse Pd, resets the frame counter 6, and pulls in synchronization.

With the above operation, synchronization is protected so that synchronization is not lost due to mere data error in the transmission path.

[0007]

In the conventional frame synchronization protection circuit, when a correlation pattern is detected at the same timing position as the frame synchronization pattern before the switching immediately after the input data is switched, the input to the mismatch detector is made. Since the detected pulse Pf and the synchronizing pulse Ps have the same timing, no mismatch pulse is transmitted, and no coincidence pulse is transmitted because the frame synchronization pattern after switching does not coincide with the timing of the synchronizing pulse. Therefore, since the mismatch counter and the match counter do not count pulses, the circuit does not function.

[0008]

SUMMARY OF THE INVENTION A frame synchronization protection circuit according to the present invention detects a frame synchronization pattern of p (p is an integer of 2 or more) bits contained in input data, and detects all bits coincident with a predetermined pattern. Means for sending a first pattern detection pulse to the second pattern detection pulse when at least q bits (q is an integer of q <p) in the p-bit frame synchronization pattern match a predetermined pattern. A frame counter that flywheels in synchronization with the frame synchronization pattern, generates a synchronization pulse by performing synchronization pull-in according to a first reset signal, and generates a synchronization pulse with the first pattern detection pulse. Means for transmitting a coincidence pulse when the timings coincide with each other by comparing the pulse with the second pattern detection pulse; Means for delivering a mismatch pulse when the timing by comparing the pulse does not match,
A coincidence counter that sends out coincidence counting pulses when the number of coincidence pulses is counted and reaches a predetermined number m (m is an integer of 2 or more), and a predetermined number n (n is n
> M integer), and a mismatch counter for sending a mismatch count pulse when the count value is equal to or greater than m, and for resetting the match counter and the mismatch counter when receiving the match count pulse or the first reset signal of the frame counter. Means for sending a second reset signal, means for counting the synchronization pulse to at least a predetermined number n, and sending a signal indicating a predetermined period, and receiving the signal indicating the predetermined period, and Means for detecting the presence or absence of the reset signal of No. 2 and transmitting an abnormality detection signal when there is no reset signal, and transmitting the first reset signal in response to the first pattern detection pulse when receiving the abnormality detection signal Means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The same parts as those of the conventional frame synchronization protection circuit shown in FIG. 3 are denoted by the same reference numerals.

The difference from the conventional example is that the constant counter 12 counts the number of synchronization pulses Ps output from the frame counter 6 to a predetermined number, and the reset which determines the presence or absence of the reset signal R2 during the counting period of the constant counter 12. That is, a signal determiner 13 and an OR gate 14 are newly provided.

That is, as shown in FIG. 1, a complete pattern detector 1 which sends out a detection pulse Pd when a frame synchronization pattern included in input data Si at a predetermined period (1 ms) completely matches a predetermined pattern. A frame counter 6 that generates a synchronization pulse Ps by flywheeling at the same cycle as the frame synchronization pattern of the input data, and a coincidence that generates a coincidence pulse K1 when the detection pulse Pd and the synchronization pulse Ps are compared and the timings coincide. Detector 4
A coincidence counter 7 for counting the coincidence pulse K1, a correlation pattern detector 2 for generating a detection pulse Pe when the frame synchronization pattern correlates, and a detection pulse P
The inversion pulse Pf and the synchronization pulse Ps are compared with each other, and a mismatch detector 5 that generates a mismatch pulse K2 when the timings do not match, a mismatch counter 8 that counts the mismatch pulse K2, and a count value of the mismatch pulse K2 A flip-flop 9 which is set when the count value reaches a predetermined value n and reset when the count value of the coincidence pulse K1 reaches a predetermined value m
And the detection pulse P by the signal output from the flip-flop 9
An AND gate 11 that permits the passage of d and resets the frame counter 6 by the reset signal R1, an OR gate 10 that resets the match counter 7, the mismatch counter 8 and the flip-flop 9, respectively, and counts the output signal of the frame counter 6. The constant counter 12 and the presence or absence of the output of the OR gate 10 are determined during a predetermined period counted by the constant counter 12, and when it is determined that there is no output, the abnormality detection signal C4 is transmitted, and the flip-flop 9 is set via the OR gate 14. A reset signal determiner 13.

Next, the operation will be described.

The constant counter 12 counts the synchronization pulse Ps and outputs a signal C3 indicating a determination period for determining the presence or absence of the reset signal R2. In this case, if the determination period is short, out-of-synchronization occurs, and if the determination period is long, the response to the synchronization abnormality becomes slow. Here, the count value m of the match counter 7 is 3, the count value of the mismatch counter 8 is 8, and the determination period is m.
And 11 ms, which is the sum of n and n.

The reset signal determiner 13 determines the presence or absence of the reset signal R2 every determination period indicated by the signal C3. If there is no reset signal R2 during the determination period (11 ms), it is regarded as a synchronization abnormality, and the flip-flop 9 is set via the OR gate 14 by the abnormality detection signal C4. Next, the detection pulse P from the complete pattern synchronization detector 1
d through the AND gate 11 and the frame counter 6
Is reset and synchronization is performed.

FIG. 2 is a timing chart showing the operation immediately after the input data Si is switched from data A to data B, and shows a case where a correlation pattern is detected even at the same timing position as the frame synchronization pattern before the switching.

When the input data is A, the synchronization is protected, the coincidence pulse K1 is output at the timing position of the synchronization pulse Ps having a period of 1 ms, and the coincidence counter 7 is set to 3
The pulse C1 is sent out every time the counting is performed. Pulse C
The coincidence counter 7, the non-coincidence counter 8 and the flip-flop 9 are reset by the reset pulse R2 sent from the OR gate 10 in response to 1.

Immediately after the switching, a correlation pattern is detected corresponding to the synchronization pulse Ps, so that the coincidence pulse K1 and the non-coincidence pulse K2 are not output. Therefore, the match counter 7 and the mismatch counter 8 are not counted up,
The synchronization pulse Ps is continuously generated in the synchronization state of the data A.

On the other hand, since the reset pulse judging unit 13 cannot detect the reset pulse R2 within the period of the pulse C3 sent every 11 ms from the constant counter 12, the reset pulse judging unit 13 sends out the abnormality detection signal C4 and forcibly turns the flip-flop 9 on. set. In other words, this is the same state as when forcible loss of synchronization has occurred.

Thereafter, the frame counter 6 is reset by the reset signal R1 sent from the AND gate 11 in response to the detection pulse Pd, whereby the data B can be synchronized with the frame synchronization pattern.

[0021]

As described above, according to the present invention, immediately after the input data is switched, the correlation pattern is detected at the same timing position as the frame synchronization pattern before the switching, and no coincidence and non-coincidence pulses are generated. Even in the case of, it is possible to prevent the circuit function from stopping by detecting this and forcibly executing the synchronization pull-in in the same state as the loss of synchronization.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the present embodiment.

FIG. 3 is a block diagram illustrating an example of a conventional frame synchronization protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Perfect pattern detector 2 Correlation pattern detector 4 Match detector 5 Mismatch detector 6 Frame counter 7 Match counter 8 Mismatch counter 9 Flip-flop 10,14 OR gate 11 AND gate 12 Constant counter 13 Reset signal judgment device C3 The judgment period Signal C4 abnormality detection signal Ps synchronization pulse R1, R2 reset signal

Claims (1)

(57) [Claims] 1. A means for detecting a frame synchronization pattern of p (p is an integer of 2 or more) bits included in input data and transmitting a first pattern detection pulse when all bits match a predetermined pattern; Means for transmitting a second pattern detection pulse when at least q bits (q is an integer of q <p) in the p-bit frame synchronization pattern coincide with a predetermined pattern; A frame counter that flywheels and performs synchronization pull-in in response to a first reset signal to generate a synchronization pulse; and when the first pattern detection pulse and the synchronization pulse are compared and the timings match. Means for transmitting a coincidence pulse to the second pattern detection pulse, and comparing the second pattern detection pulse with the synchronization pulse to determine that the timings do not coincide with each other. Means for transmitting a non-coincidence pulse at a time; a coincidence counter for transmitting a coincidence counting pulse when the coincidence pulse is counted to reach a predetermined number m (m is an integer of 2 or more); A non-coincidence counter for transmitting a non-coincidence counting pulse when a predetermined number n (n is an integer of n> m) is reached;
Means for transmitting a second reset signal for resetting the coincidence counter and the non-coincidence counter when the reset signal is received, and transmitting a signal indicating a predetermined period by counting the synchronization pulse to at least a predetermined number n. Means for receiving the signal indicating the predetermined period and receiving the signal indicating the predetermined period within the predetermined period.
Means for detecting the presence / absence of a reset signal, and sending an abnormality detection signal when there is no reset signal; means for sending the first reset signal in response to the first pattern detection pulse when receiving the abnormality detection signal And a frame synchronization protection circuit.