JPH03270337A - Clock synchronizing data communication method - Google Patents

Abstract

PURPOSE:To easily detect occurrence of an error in the communication between a host unit and plural slave units by inserting a frequency division clock of a clock to a command signal line. CONSTITUTION:A 1/2 frequency division clock of a clock inputted from a command signal and a signal 9 of low-order 2-bit outputted from a counter, and when they are dissident, it is discriminated to be in error and a signal 16 is outputted. The signal 16 and a signal 17 notifying an error caused at command decode are used to detect an error and to control a signal 18 enabling an output buffer. When no error takes place, the output buffer is enabled by a match signal and an output data in response to a command is outputted to a terminal OUT, but when an error takes place, the output buffer is kept disable and the OUT signal reaches a high impedance. Thus, the occurrence of an error is easily detected in the communication between a host unit and plural slave units.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock synchronous data communication method, particularly to a clock synchronous data communication method in a system constituted by one master unit and a plurality of slave units. .

[Conventional technology]

In this type of technology, noise in the clock signal tends to cause transmission errors, so conventionally this has been avoided using the following method.

1. Use a material with good noise resistance for the signal line.

2. Add a signal line and use it for error detection.

3. Make the clock faster than the data transmission rate so that erroneous clock counts can be ignored.

[Problem to be solved by the invention]

Each of the three systems has the following disadvantages.

1. Since a shielded cable or the like is used as a signal line with good noise resistance, there is a drawback that the cost φ increases, and there is also a drawback that inspection is impossible when an error occurs.

There is a disadvantage that the number of 26 signal lines increases and the cost Φ increases.

3. The transmission lock that can transmit signal lines has a limit depending on the line size and cable length, and in order to raise the clock higher than the data transmission rate, it is necessary to lower the data transmission rate.

[Means to solve the problem]

The clock synchronized data communication method of the present invention has at least a clock signal line, a command signal line, and a data transfer signal line as signal lines, and a plurality of host units are synchronized with the clock output from one host unit. In a clock synchronous data communication method for performing data communication with a slave φ unit,
When no command signal is output to the command signal line, the host unit outputs a frequency-divided clock to the command signal line, each slave unit counts the clock using a flip-flop, and calculates the count value. An error is detected by comparing the frequency-divided clock and the frequency-divided clock.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention.

1 host 0 unit and 11 slave units 2 to 4
It consists of 5 units, and the signal line between them is 5.
6 clock signals, 6 command signals.

There are 7 OUT signals.

The clock signal is a communication reference clock and is output from the host. The command signal is output from the boss unit to the slave unit. OUT
The signal is the transmitted data from the slave unit.

The operation of the system is as follows.

The host unit transmits a command of a predetermined number of bits in synchronization with the clock. All slave units that received the command count up their clocks,
If the address previously set for each slave unit and the counter value match, that slave unit outputs according to the command.

When no command is sent to the command signal, a clock divided by 2 is output to the command signal line, and each slave unit compares it with the lower 2 bits of the counter, and if there is a difference, it is treated as an error 2, and the data is No output.

FIG. 2 is a block diagram of the interface portion of the slave cornit for realizing the above operation.

8 is a command decoder, 9 is a clock counter, 1
0 is a comparator that detects a match between the counter and AT/S, and 11 is a data output buffer. 12 to 18 explain the opening time during the explanation of the operation.

The operation of the slave unit will be explained below.

Decoder 8 converts the command into serial/parallel data in synchronization with the clock, and depending on the command, outputs a counter reset signal to 12 to synchronize with the host unit. A counter 9 counts the clock and compares it with a preset address using a comparator 1, 0. If they match, it outputs a match signal 14 to enable the output buffer 11.

Check for errors as follows. The 2-frequency divided clock input from the command signal and the signal 9 outputting the lower 2 bits of the counter are compared, and if they do not match, it is determined that there is an error and a signal 16 is output. Error detection is performed using these 16 signals and 17 signals that notify an error that has occurred during command decoding, and a signal 18 that enables the output buffer is controlled. As a result, when no error occurs, the output buffer is enabled by the MATCH signal and output data is output to the OUT signal in response to the command, but when an error occurs, the output buffer remains disabled and the OUT signal is Goes into high impedance state.

Since the host unit enters a high impedance state when the slave unit outputs data to the OUT signal, the host unit can know that an error has been detected in the slave unit.

〔Effect of the invention〕

As explained above, the present invention inserts a frequency-divided clock into the command signal line, thereby achieving clock synchronous data communication between a host unit and multiple slave units without increasing the number of signal lines. Furthermore, there is an effect that the occurrence of an error can be easily detected without reducing the transmission rate.

1...Host unit, 2...Slave unit) (1), 3...Slave unit (2), 4...
・Slave unit (3), 5...clock signal,
6... Command signal, 7... Data output signal, 8.
...Decoder, 9...Counter, 10...Comparator, 11...Output buffer, 12...Counter
Reset signal, 13... Count/output, 14...
Match signal, 15...Counter lower 2 bits output, 1
6...Clock error output, 17...Command/
Error output, 18... Output buffer output control.

Claims (1)

[Claims] 1. It has at least a clock signal line, a command signal line, and a data transfer signal line as signal lines, and is connected to a plurality of slave units in synchronization with a clock output from one host unit. In a clock synchronous data communication method for data communication, when a command signal is not output to the command signal line, the host unit outputs a divided clock to the command signal line, and each slave unit outputs a divided clock to the command signal line. 1. A clock synchronous data communication method, characterized in that an error is detected by counting by a flip-flop and comparing the count value and the frequency-divided clock. 2. The clock according to claim 1, wherein the frequency-divided clock signal inserted into the command signal line is compared with the second lower bit of the counter of the slave unit, and if they do not match, an error signal is generated. Synchronous data communication method.