JPH0314250B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a frame synchronization circuit having measures to prevent false synchronization in digital communications.

[Prior art]

FIG. 1 is a format diagram showing the structure of one frame in, for example, PCM digital communication. In the figure, 100 is one frame composed of N bits, 101 is a data signal in frame 100, 102 is a synchronization signal, and 103 is a data signal in frame 100. is the code error control signal. The synchronization signal 102 is composed of _ns bits having a specific bit pattern, and the code error control signal 103 is a redundant bit added to detect code errors in the frame 100 and automatically correct them. For example, n _c bits are added so that the remainder when the N-bit bit pattern of frame 100 is divided by a characteristic polynomial of order n _c -1 (division modulo 2) is 0. Therefore, when the N-bit bit pattern of received frame 100 is divided by the above polynomial,
If the remainder does not become 0, it means that a code error exists.

FIG. 2 is a block diagram showing an example of a conventional frame synchronization circuit. In the figure, 1 is a shift register;
2 is a synchronization pattern detection circuit, 3 is a synchronization protection circuit,
5 is a frame counter. Also, PCM IN
PCM signal input terminal, CLK is clock signal input terminal, FP is frame synchronization pulse output terminal, DATA
is a branch output terminal for the input PCM signal.

a is an _ns- bit signal input from the shift register 1 to the synchronization pattern detection circuit 2, and b is an output signal of the synchronization pattern detection circuit 2. When the signal a matches the bit pattern of the synchronization signal 102, the logic becomes "1". c is a signal that becomes logic "0" when they do not match, and c becomes logic "1" only when the count value of frame counter 5 is 0 (that is, becomes logic "1" at the timing to perform synchronization verification). ,
d is a signal indicating an out-of-synchronization state, e is a signal for resetting the frame counter 5, and f is a signal indicating the count value of the frame counter 5.

By the way, on the transmitting side of PCM communication, the N-bit frame shown in Figure 1 is repeatedly sent out, so once the frame pulse can be sent correctly to the terminal FP, the next frame pulse will be sent to the terminal FP.
The clock signal from CLK is sent to frame counter 5.
It is only necessary to send it to the terminal FP when N pieces have been counted.
Therefore, if the frame counter 5 is configured to output one overflow pulse for each input of N clock signal pulses, once the overflow pulse matches the frame pulse, the transmission side As long as frame repetition is performed normally, the overflow pulse from the frame counter 5 will always match the frame pulse. Such a state is called a synchronous state, and in the synchronous state, when the count value f of the frame counter 5 is 0, the signal a matches the bit pattern of the synchronizing signal 102, and the signal b becomes logic "1".

Next, assume that the circuit of FIG. 2 is out of synchronization. When the signal c is logic "1", the signal b is logic "0", and the output signal d of the synchronization protection circuit 3 indicates an out-of-synchronization state, and the control circuit 4 detects this and outputs the signal e, and the frame counter 5 Reset. The next bit is input from the terminal PCM IN, and the signal a becomes a bit pattern shifted by one bit. If this bit pattern also does not match the bit pattern of the synchronization signal, signal b is logic "0", frame counter 5 is reset again by signal e, and signal c is logic "1" (count value f is 0). As a result, the signal a becomes a bit pattern further shifted by one bit, and is compared in the synchronization pattern detection circuit 2. In this way, the frame counter 5 is reset each time the output signal of the synchronization pattern detection circuit 2 is logic "0", and the state in which the signal a is shifted by one bit and compared with the bit pattern of the synchronization signal is called hunting. ) state. When the bits are sequentially shifted one bit at a time in the hunting state, a time comes when the signal a becomes the n _s bit of the synchronization signal 102.
At this time, the signal b becomes logic ``1'' and the frame counter 5 is not reset, so its count value increases sequentially, and after counting N bits of the clock signal, an overflow pulse is output and the count value f increases. The signal will not become logic "1" until it becomes 0 again, so the signal e will not be output. This state is called a backward protection state.

In the backward protection state, signal b becomes logic "1" because the synchronization signal 102 was correctly detected, or because the bit pattern of the synchronization signal 102 coincidentally matches the synchronization signal 102, although it is not the synchronization signal 102. During the period for checking whether this is due to the arrival of a signal, it is checked whether the signal b becomes logic "1" again N bits after the time when signal b became logic "1". Signal _b is input continuously at N bit intervals.
If the logic becomes "1" a number of times (N _B can be set arbitrarily), it is assumed that the synchronization state is correct and the state is transferred to the forward protection state. If the logic of signal b is "0" while the logic of signal c is "1" before reaching N _B times, the hunting state is entered.

In the forward protection state, it operates on the premise that it is in a correct synchronization state. Therefore, every time the frame counter 5 counts N bits of clock signal pulses, a frame pulse is output, and at that point, the signal b
Even if the logic is "0", it is determined that this is not an out-of-synchronization but some kind of error. however,
If _NF ( _NF can be set arbitrarily) errors in which the logic of signal b becomes ``0'' when the logic of signal c is ``1'' occur consecutively in the forward protection state, synchronization occurs. It is assumed that it is out of order and goes into a hunting state.

Figure 3 shows the synchronization protection circuit 3 and control circuit 4 in Figure 2.
A diagram showing three-state operation controlled by and,
h, g, i, j, k, l indicate the respective signals, h, j, l correspond to the signal d output from the synchronization protection circuit 3, and the signals h, j indicate that the signal c is logic "1". If signal b becomes logic "0" once, signal g is output, signal g is output if signal c becomes logic "1" and signal b becomes logic "1" once, and signal l is output when the state where signal c is logic "1" and signal b is logic "0" occurs N _F times in succession, and the signal i is output when the state where signal c is logic "1" and signal b is logic "1" is N _B The signal k is output if it occurs continuously twice, and the signal k is output in all cases except when the signal l is output.

By the way, in PCM signals, etc., it is difficult to completely remove the part of the bit pattern that is the same as the synchronization signal 102 from the data signal, and such a bit pattern may repeat in the frame period. In sync with the pseudo sync pattern,
The vehicle may enter the forward protection state from the rear protection state.

In order to prevent such pseudo synchronization, a code error control signal 103 has been used. FIG. 4 is a block diagram showing another example of the conventional device.
The same reference numerals as in the figure indicate the same or corresponding parts, and 6 is a division circuit. This division circuit 6 performs division modulo 2 on the input N bits using the characteristic polynomial used when generating the code error control signal 103, and checks whether the remainder becomes 0 or not. It can generally be called a sign verification circuit. 7 is an AND gate, m is an N-bit signal input from the shift register 1 to the division circuit 6, n is a timing signal for performing sign verification, and o is the division circuit 6
If there is no code error, the output becomes logic "1", and if there is a code error, it becomes logic "0". In other words, in the case of pseudo synchronization, the sign of the N bits of the signal m is not the N bits of one frame shown in Figure 1, but is the N bits that are the concatenation of the rear bits of the previous frame and the front bits of the subsequent frame. Therefore, there is generally a high probability that the signal o, which is the output of the divider circuit, will be logic "0". In the case of Figure 2, signal b
However, in the case of Fig. 4, it is assumed that the synchronization signal is detected by the logical product of signal b and signal o, reducing the chance of false synchronization. can do. However, when dividing the bit pattern of signal m, there are many chances that the remainder becomes 0 by chance. Therefore, due to pseudo synchronization, signal b becomes logic "1" and signal o becomes logic "1" by chance. Therefore, the forward protection state may be entered by mistake, and to prevent this, N _B must be set considerably large. If N _B is set to a large value, there will be a point in time during which the signal o becomes logic "0", thereby preventing erroneous entry into the forward protection state.

Further, even in a state where accurate synchronization is achieved, the signal may become logic "0". This is because code errors occur due to noise in the transmission path, etc. In anticipation of such a situation, a code error control signal 103 is added to detect code errors and correct the errors. However,
In order to prevent such a code error from occurring in the forward protection state and erroneously entering the hunting state, N _F must be set large.
For this reason, the circuit shown in FIG. 4 has the disadvantage that it takes a long time to detect false synchronization.

[Summary of the invention]

This invention was made to eliminate the drawbacks of the conventional ones as described above.In this invention, in addition to a synchronization protection circuit using a synchronization pattern detection circuit, a synchronization protection circuit using a code error detection circuit is provided to prevent hunting from occurring. The operation of entering the forward protection state after passing through the backward protection state is controlled by the output of the synchronization pattern detection circuit, and the output of the code error detection circuit is also used to control escape from the forward protection state by mistake. be.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG.
9 is a control circuit used in the present invention, and 10 is a frame counter. Further, p is an operation timing signal of the synchronization protection circuit 8, q is a signal indicating an out-of-synchronization state, r is a load signal for the frame counter 10, and s is a signal indicating the contents of the frame counter 5, which is the same signal as the signal f. .

FIG. 6 is a diagram showing the operation in three states controlled by the synchronization protection circuits 3 and 8 and the control circuit 9 in FIG. 5, and the same symbols as in FIG. 3 mean the same or equivalent signals. , u corresponds to the signal q in FIG. 5, t is a signal output in cases other than when the signal u is output,
Signal v is an AND signal of signals k and t and is a load signal corresponding to signal r, and signal x is a signal that maintains the forward protection state.

FIG. 6 shows that the control circuit 9 stores which of the three states the controlled object is in. However, since there is no essential difference in the control operation of the control circuit 9 between the hunting state and the rear protection state, the control circuit 9 has a 1-bit memory that stores whether or not the object to be controlled is in the forward protection state. It can be controlled if the This memory is tentatively referred to as a forward protection state memory, and if this memory is set, it is in the forward protection state, and if it is reset, it indicates that it is not in the forward protection state.

Regarding the forward protection state memory, what is meant by FIG. 6 is that the forward protection state memory is reset at the time of initialization, by the signal 1, by the signal u, and by the signal i.

The operation from the hunting state to the rear protection state to the front protection state and the operation of changing to the hunting state by the h, j, and l signals are the same in the circuit of FIG. 5 as in the circuit of FIG. 2. . When the forward protection state is entered and no code error is detected by the title protection circuit 8, the content s of the frame counter 5 is loaded into the frame counter 10 by the signal r, and the frame counter 10 outputs a frame pulse. The control circuit 9 outputs the timing pulse p when the content f of the frame counter 5 is 0, and the synchronization protection circuit 8 stores the logic of the signal o at that time and outputs the timing pulse p out of M times (MeM, M and
(Me can be arbitrarily set) If a logic 0 is present, it is determined that it is pseudo synchronization and a signal q is output. The control circuit 9 outputs a signal e based on the signal q.
(corresponding to signal u in Fig. 6), resets the frame counter 5, and enters the hunting state.
Thereafter, the same operation as in FIG. 2 is performed regardless of the output of the synchronization protection circuit 8, and when the forward protection state is entered, the signal k shown in FIG. 6 is output. At this time, if the signal t is output, the contents of the frame counter 5 are loaded into the frame counter 10. That is,
Since the frame counter 5 that performs hunting and the frame counter 10 that outputs frame pulses are independent, even if hunting is entered by mistake, the output pulses of the frame counter 10 will not be disturbed and the forward protection state will be maintained. Since the contents of both counters match at the time when the frame counter 5 is loaded into the frame counter 10, the effect of erroneously entering hunting does not appear on the terminal FP. In addition, when signal b (at the time when signal c is logic "1") becomes logic "1" continuously due to pseudo synchronization, signal o out of M
M _E values or more become logic "0", and it is possible to quickly escape from the pseudo synchronization.

Note that the synchronization signal 102 may be placed at any position in the frame 100, or may be distributed throughout the frame 100.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to quickly escape from pseudo synchronization, and even if hunting is accidentally entered, the synchronization state can be maintained without being affected by it.

[Brief explanation of the drawing]

Fig. 1 is a format diagram showing the structure of one frame, Fig. 2 is a block diagram showing an example of a conventional circuit, and Fig. 3 is a three-dimensional circuit that is controlled by the circuit shown in Fig. 2.
4 is a block diagram showing another example of the conventional circuit, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a diagram showing the circuit of FIG. 5. It is a figure which shows operation|movement of three controlled states. 1...Shift register, 2...Synchronization pattern detection circuit, 3, 8...Synchronization protection circuit, respectively, 5...
...First frame counter, 6...Division circuit, 9
...Control circuit, 10...Second frame counter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A digital signal including, for each signal frame, a synchronization signal having a specific bit pattern and a code error control signal for controlling code errors;
In a frame synchronization circuit for extracting a frame synchronization pulse from a received signal when a plurality of frames of the digital signal are transmitted continuously, means for generating a clock signal having a clock period equal to the bit period of the received signal; When the number of bits in one frame of the digital signal is N, N-ary first and second frame counters each input the clock signal and count the number of pulses of the input clock signal; means for arranging signals in series in a shift register, for N consecutive bits to be arranged in the shift register at every clock instant when the count value of the first frame counter is 0;
Logic "0" when a code error is detected by performing code verification determined in accordance with the above code error control signal.
a sign verification circuit that outputs a logic "1" signal when the signal is not equal to "1"; The bit pattern of the part corresponding to the synchronization signal among the N bits is compared with the above specific bit pattern, and if the comparison matches, a logic "1" signal is set, and if not, a logic "0" signal is set.
A synchronization pattern detection circuit that outputs a signal of Each time a logic "0" signal is output from the detection circuit, the first frame counter is reset to make its count value 0, and the logic "1" output from the synchronization pattern detection circuit is N _B
If the output of the sign verification circuit is logic "1" when the number of consecutive times is consecutive, the memory is set, and the contents of the first frame counter at this time are loaded into the second frame counter, and this memory is set. When the above-mentioned synchronization pattern detection circuit outputs a logic "0" consecutively N _F times, or the above-mentioned sign verification circuit outputs a logic "0" M times or _more during the M outputs. a control circuit that resets the first frame counter and resets the memory only when N _B , N _F ,
M, _ME are integers determined by design); and means for outputting an overflow pulse of the second frame counter as the frame synchronization pulse.