JPS63116537A - Synchronization protecting circuit - Google Patents

Abstract

PURPOSE:To facilitate establishment of synchronization and to cause out-of- synchronization to be hard to occur by making a first step coarse at the back protection, raising successively the accuracy, making the first step strict at the front protection and making the accuracy coarse successively. CONSTITUTION:When the intermediate output of the counter of a back protecting circuit 11, for example, an intermediate output 16 is a second step counter output, an intermediate output 17 is a third step counter output, an intermediate output 18 is a fourth step counter output, and an intermediate output 19 of the counter of a front protecting circuit is the first step counter output, and an intermediate output 20 is the second step counter output. Consequently, the detecting pattern of a synchronizing pattern is coarse to the first step at the back protection, a correct synchronizing pattern is successively detected, and when an unfair synchronizing pattern is detected once at the front protection, the detecting pattern is made coarse a little, further, when the circuit comes off from the detecting pattern, it works to make the detecting pattern coarse one more time. Thus, the probability that the delay in the establishment of synchronization occurs due to the code error, etc., in a transmission system and the out-of-synchronization generated can be widely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to means for detecting synchronization success or synchronization failure in a digital transmission device when a receiving side needs to synchronize with a transmitting side.

[Conventional technology]

FIG. 3 is a lecture diagram showing a conventional synchronization protection circuit. In the figure, 1 is an 8-bit synchronous 7ξ turn signal. 2
is a clock signal that causes the synchronization pattern signal 1 to be read into the shift register 3 of the 8-bit serial input Φ parallel output. 4 and 5 are inverters for inverting the most significant bit (QH) and the least significant bit (QA) of the output signal of the shift register 3. 6 is N for inverting the logical sum of the output signals of the shift register 3 and each inverter 4 and 5.
It is an OR circuit. 7 is a synchronization gate signal which has the same period as the repeated synchronization of synchronization pattern signal 1, has a positive pulse width equal to or less than the period of clock signal 2, and has the same timing as the read clock of the least significant bit of the synchronization pattern. , and is input to the AND circuit 8 and the inverter 9, respectively.

8 is an AND circuit that takes the logical product of the output signal of the NOR circuit 6 and the synchronization gate signal 7; its output is input to the backward protection circuit 11 consisting of an M-stage counter; The signal is input to a NOR circuit 10 which inverts the logical sum of the output signals. 12 is an output signal of the rear protection circuit 11, which is a synchronization success signal. Reference numeral 13 denotes a forward protection circuit consisting of an N-stage counter that receives the output of the NOR circuit 10, and its output signal is the synchronization failure signal 14.

FIG. 4 shows the function of the synchronization protection circuit shown in FIG. 3.

It is a timing chart for explaining the effect.

Next, the operation of the above-mentioned conventional synchronization protection circuit will be explained. As shown in FIGS. 3 and 4, the synchronization pattern signal 1
is read into the shift register 3 by the clock signal 2. At this time, if the synchronization pattern signal 1 is a synchronization pattern of 10000001 as shown in FIG. "H"
become. At the same time, the synchronization gate signal 7 is set to be rHJ with the same timing, so the AND circuit 8 outputs rlE(j) at the same timing. For example, if this backward protection circuit 11 is a 6-stage counter, when the output of the AND circuit 8 outputs "H" 6 times, the backward protection circuit 11 indicates that the synchronization is successful. Outputs signal 12. Also, synchronization pattern signal 1
is different from 10000001, NOR
The output of the circuit 6 is rH during the rHJ period of the synchronization gate signal 7.
J is not output, and the output of the AND circuit 8 remains rLJ. On the other hand, since the output of the inverter 9 is an inverted signal of the synchronization gate signal 7, it is normally rHJ and is "L" only during the period from the read clock of the least significant bit (8th bit) of the synchronization pattern to the next clock. become. Therefore, N
In this case, the output of the OR circuit 1° is rHJ. For example, if the number of stages of the counter of the forward protection circuit 13 is three, the synchronization failure signal 14 is output when the output of the NOR circuit 10 is output three times. be done.

Although omitted in FIG. 3, the synchronization success signal 12
The forward protection circuit 13 is cleared by the synchronization failure signal 14, and the backward protection circuit 11 is cleared by the synchronization failure signal 14, so that a synchronization failure is detected from a synchronization success state, and a synchronization success is detected from a synchronization failure state. .

[Problem that the invention seeks to solve]

Generally, digital transmission equipment has a training mode and a data mode, and when synchronization is not established between the transmitting and receiving equipment, the training mode (which naturally includes synchronization pattern signal 1) is transmitted to indicate that synchronization has been established. When received from the sender, it switches to data mode and sends data.

Therefore, since the conventional synchronization protection circuit described above is configured as described above, the correct synchronization pattern is repeated six times from the state of out-of-synchronization to the establishment of synchronization, and during that time, three or more incorrect synchronization patterns are detected. must not. That is,
This makes it difficult to establish synchronization. In addition, even if synchronization is established, synchronization will be lost if three incorrect synchronization patterns are input despite normal synchronization, such as a code error in the transmission system affecting the synchronization pattern. However, there was a problem that synchronization was easily lost.

However, it is also a problem that synchronization may be mistakenly determined to have been established during an out-of-synchronization state, and the setting of 6 stages of backward protection and 3 stages of forward protection in the above conventional example is a This is the optimum number of stages when the out-of-synchronization establishment and false synchronization establishment are set to specific values under specific conditions such as the period and the shortest out-of-synchronization time interval.

The present invention has been made to solve these problems, and an object of the present invention is to provide a synchronization protection circuit that facilitates the establishment of synchronization and is less likely to lose synchronization.

[Means for solving problems]

The synchronization protection circuit according to the present invention does not fix the detection of the synchronization pattern, but detects the synchronization pattern in the backward protection by roughening the detection at the first stage and gradually increasing the accuracy. It is strict, but the accuracy is made progressively rougher.

[Effect]

In the synchronization protection circuit of the present invention, by varying the detection accuracy of synchronization patterns, synchronization protection can be performed by removing invalid synchronization patterns due to code errors in the transmission system.

〔Example〕

FIG. 1 is a block diagram showing a synchronization protection circuit according to an embodiment of the present invention. In the figure, 1 is an 8-bit synchronization pattern signal. 2 is a clock signal for reading the synchronization pattern signal 1 into the 8-bit serial input/parallel output shift register 3. Inverters 4 and 5 invert the most significant bit QH and the least significant bit QA of the output signal of the shift register 3. Reference numeral 15 inputs output signals of the shift register 3 and each inverter 4, 5, and output control terminals A, B.

This is a switch circuit having C. 6 is a switch circuit 15
This is a NOR circuit that takes the output of . 7 is a synchronization gate signal which has the same period as the repetition period of the synchronization pattern signal, has a positive pulse width equal to or less than the period of clock signal 2, and has the same timing as the reading clock of the least significant bit of the synchronization pattern. , and is input to the AND circuit 8 and the inverter 9, respectively. 8 is an AND circuit which inputs the output signal of the NOR circuit 6 and the synchronization gate signal 7; its output is input to the backward protection circuit 11 consisting of an M-stage counter;
The signal is input to a NOR circuit 10 which inverts the logical sum of the output signals. 12 is an output signal of the rear protection circuit 11, which is a synchronization success signal. Reference numeral 13 denotes a forward protection circuit consisting of an N-stage counter that receives the output of the NOR circuit 10, and its output signal is the synchronization failure signal 14. 16°17.18 are intermediate outputs of the counter of the rear protection circuit 11, and are connected to each output control terminal A of the switch circuit 15.
, B, and C, respectively.

19.20 are intermediate outputs of the counter of the forward protection circuit 13, and intermediate outputs 16.20 of the rear protection circuit 11, respectively.
17 through a wired OR, and is further input to each output control terminal A, H of the switch circuit 15. Further, the synchronization success signal 12 is also combined with the intermediate output 18 of the counter of the backward protection circuit 11 by wired OR, and is further inputted to the output control terminal C of the switch circuit 15.

FIG. 2 is a diagram for explaining changes in detection patterns of synchronization patterns according to the conventional method and the method according to the present invention.

Next, the operation of the synchronization protection circuit which is one embodiment of the present invention will be described. Synchronous pattern signal 1 is read into shift register 3 by clock signal 2. Here, the switch circuit 15 has its respective output control terminals A
, B, and C, the least significant bit (1st bit) and most significant bit (8th bit) pass the input signal as is to the output, and the other bits (2nd to 7th bit) ) always outputs rL regardless of the input signal.
j + rub. Then, when there is a signal at the output control terminal A, the switch circuit 15 controls each first . 2nd bit and each 7th bit. The 8th bit passes the input signal as it is to the output, but the 3rd to 6th bits always make the output rLJ regardless of the input signal.

In addition, when there is a signal at the output control terminal B, the switch circuit 15 controls each fourth . Only the fifth bit always shifts the output to rLJ regardless of the input signal. Furthermore, when there is a signal at the output control terminal C, the switch circuit 15 is set to pass all input signals to the output as is, similar to the conventional example described above.

By setting the switch circuit 15 as described above, for example, each output control terminal A.

If there is no signal at B or C, the synchronization pattern detection pattern will be 1××××××1 (× indicates that it can be either 1 or 0), and if there is a signal at output control terminal A, , the detection pattern is 10XXXXOI. If there is a signal at the output control terminal B, the detection pattern is 100XXOOI. If there is a signal at the output control terminal C, the detection pattern is 100XXOOI, which is the same as the conventional example above.
00001, and four types of detection patterns are obtained. For example, if there is no signal at each output control terminal A, B, or C, if the most significant bit and the least significant bit of synchronous pattern signal 1 are 1, no matter which value the intermediate bit has, the NOR circuit will The output signal of 6 becomes "H" when the 8th bit of the synchronization pattern is read, and the AND circuit 8
rHJ is output at the same timing, which moves the counter of the rear protection circuit 11 by one step.

The intermediate output of the counter of the backward protection circuit 11 is, for example, the intermediate output 16 is a two-stage counter output, the intermediate output 17 is a three-stage counter output, and the intermediate output 18 is a four-stage counter output,
Assuming that the intermediate output 19 of the counter of the forward protection circuit 13 is a 1-stage counter output, and the intermediate output 2° is a 2-stage counter output,
As shown in Figure 2, in backward protection, the synchronization pattern detection pattern is rough at the first stage, and then accurate synchronization patterns are detected sequentially, and in forward protection, once an invalid synchronization pattern is detected, a small number of detection patterns are detected. It makes the pattern rough, and when it deviates from the detected pattern, it works to make the detected pattern rougher again. On the other hand, an example of a synchronization pattern detected by the conventional method is as shown in FIG.

In the above embodiment, it has been described that the detection accuracy of the synchronization pattern is changed, but the synchronization pattern detection timing may be more lenient, or the detection level may be more or less strict.

〔Effect of the invention〕

As explained above, in the synchronization protection circuit, the detection of the synchronization pattern is not fixed in the synchronization protection circuit, but the detection of this synchronization pattern is made rough in the first stage in the backward protection, and the accuracy is gradually increased. As for protection, the first stage is strict, but the accuracy is gradually made rougher, so it is an excellent method that can significantly reduce the probability of delays in synchronization establishment or loss of synchronization due to code errors in the transmission system. It is effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a synchronization protection circuit according to an embodiment of the present invention, FIG. 2 is a diagram for explaining changes in detection patterns of synchronization patterns according to the conventional method and the method of the present invention, and FIG. 4 is a block diagram showing a conventional synchronization protection circuit, and FIG. 4 is a timing chart for explaining the function 1 of the synchronization protection circuit shown in FIG. In the figure, 1... synchronous pattern signal, 2... clock signal, 3... shift register, 4, 5.9...
Inverter, 6, 10...NOR circuit, 7...Synchronization gate signal, 8...AND circuit, 11...Backward protection circuit, 12...Synchronization success signal, 13...Forward protection circuit, 14...Synchronization failure signal, 15...Switch circuit, 16,17°18.19,20...Intermediate output. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a synchronization protection circuit of a digital transmission device having a synchronization pattern, in a circuit that performs synchronization coincidence detection and synchronization mismatch detection multiple times, backward protection or forward protection is performed without fixing the detection of the synchronization pattern. A synchronization protection circuit characterized by comprising a means for sequentially varying the detection accuracy of the synchronization protection circuit.