JPH04310029A - Phase locked loop circuit and signal transmitter-receiver - Google Patents

Abstract

PURPOSE:To reduce the synchronization lock time at reception, to minimize sensitive phase correction at transmission and to improve the reliability by switching a synchronization protection stage number automatically without fixing the synchronization protection stage number to correct the title circuit. CONSTITUTION:A phase lead detection signal Sphi1 or a phase lag detection signal Sphi2 are inputted to a synchronization protection/control means 12. A synchronization protection control signal Ci representing number of synchronization protection stages is selected based on a phase of a signal RXD and a phase of a synchronization extraction clock Ci at the reception of the signal. An internal control signal CR based thereon is outputted to a frequency divider means 13. Moreover, when the signal RXD from a reception communication line L1 is processed by a reception means 14 at the transmission of a signal, the signal phi2 from a phase locked loop means 15 is subject to extraction processing by a control means 17. Thus, a transmission signal OXD based on the signal phi2 is outputted to a transmission communication line L2 from the transmission means 16 via the control means 17.

Description

[Detailed description of the invention]

[Table of Contents] Industrial field of application Conventional technology (FIG. 8) Problem to be solved by the invention (FIG. 9) Means for solving the problem (FIGS. 1 and 2) Working example (1) No. Description of the first embodiment (FIGS. 3 to 6) (2) Description of the second embodiment (FIG. 7) Effects of the invention

0002

[Field of Industrial Application] The present invention relates to a phase-locked loop circuit and a signal transmitting/receiving device, and more specifically to a bit synchronization extraction circuit for transmitting and receiving data by performing bit synchronization processing between received data and transmitted data. This invention relates to a device for applying the same.

In recent years, phase-locked loop circuits (hereinafter simply referred to as DPLL circuits) for digital signals have been added to integrated digital communication service networks (hereinafter simply referred to as ISDN networks) that centrally provide various types of communication services such as voice, image, and data. A signal transmitting/receiving device with a built-in is used.

According to this, in the DPLL circuit, one fixed internal control signal is output from the synchronization protection/control circuit to the frequency divider based on the phase lead detection signal or the phase lag detection signal. Therefore, if the number of synchronization protection stages is increased more than necessary and set to a fixed value, the synchronization pull-in period becomes longer.

On the other hand, if the number of synchronization protection stages is reduced below the necessary value and set to a fixed value, the synchronization extraction clock will be overly corrected. As a result, the reliability of the digital signal transmitting/receiving device incorporating the DPLL circuit may decrease.

Therefore, without setting the number of synchronization protection stages to a fixed value, it is automatically switched to shorten the synchronization pull-in time during reception, and to suppress sensitive phase correction during transmission as much as possible. There is a desire for circuits and devices that can improve the reliability of the device.

[0007]

2. Description of the Related Art FIGS. 8 and 9 are explanatory diagrams of a conventional example. FIGS. 8A and 8B show explanatory diagrams of a phase-locked loop circuit for digital signals according to a conventional example.

FIG. 8(a) shows an explanatory diagram of a communication device to which a phase-locked loop circuit for digital signals is applied.

In FIG. 8(a), a digital signal transmitting/receiving device 10 used in an ISDN network that centrally provides various types of communication services such as voice, image, data, etc. communication line L1 and its transmission communication line L2. Further, the signal transmitting/receiving device 10
When the device becomes a slave (sub transmitter/receiver) device, the signal (
On the slave device side, the received signal RXD is synchronized with the synchronization extraction clock Φ2 extracted from the received signal RXD).
The communication regulations (common protocol) specify that the reception process of D and the transmission process of the transmission signal OXD signal are performed.

[0010]The digital signal DPLL circuit 6 is as follows:
It is provided in the signal transmitting/receiving device 10 in order to comply with communication regulations, and inputs the received signal RXD transmitted to the receiving communication line L1 via the code converter 5, and converts the signal RX
The synchronous extraction clock Φ2 is detected from D and outputted as a fixed value.

FIG. 8(b) shows a configuration diagram of a phase-locked loop circuit for digital signals. In FIG. 8(b),
The DPLL circuit 6 that fixedly outputs the synchronization extraction clock Φ2 includes a phase comparison circuit 1, a synchronization protection/control circuit 2, and a frequency divider 3.
Consists of.

The function of the circuit 6 is that the received signal RXD and the synchronization extraction signal Φ2 are compared, and the resulting phase lead detection signal SΦ1 or phase lag detection signal SΦ2 is sent from the phase comparison circuit 1 to the synchronization protection/control circuit 2. is output to. In addition, in the synchronization protection/control circuit 2, the phase lead detection signal SΦ
One fixed internal control signal SR is output from the circuit 2 to the frequency divider 3 based on the phase delay detection signal SΦ2 or the phase delay detection signal SΦ2. As a result, the synchronous extraction clock Φ2 is fixedly output from the frequency dividing means 3 based on the internal control signal SR, and the signal to be transmitted from the master device and the transmission clock signal of the transmission signal OXD output from the slave device are Synchronized.

[0013]

[Problem to be solved by the invention] By the way, the conventional DP
According to the LL circuit 6, one fixed internal control signal SR is output from the synchronization protection/control circuit 2 to the frequency divider 3 based on the phase lead detection signal SΦ1 or the phase lag detection signal SΦ2. This is because the number of synchronization protection stages for correcting the phase-locked loop is set to a fixed value in accordance with the physical conditions (standards) of the communication line in order to eliminate the influence of noise on the communication line.

Therefore, the first problem is that the synchronization pull-in period T becomes long as shown in FIG. 9(b). That is, in the configuration diagram of the synchronization protection/control circuit as shown in FIG. Then, a count up signal UP or a count clear signal CLR is output to the synchronization protection counter 2B based on the phase of the reception signal RXD and the phase of the synchronization extraction clock Φ2.

For example, assuming that the number of synchronization protection stages = 4 is set as a fixed value, in a signal waveform diagram as shown in FIG. 9(b), the phase and synchronization extraction of the received signal RXD during reception are When the initial phase shift Δφ1 with respect to the phase of the clock Φ2 continues four times, the internal control signal SR is output from the counter 2B to the timing generator 2C. here,
The number of synchronization protection stages refers to the counter setting value when correcting the phase-locked loop circuit. As a result, the internal control signal SR output from the generator 2C and the sampling clock Φ
The phase of the synchronization extraction clock Φ2 is corrected based on the frequency divider count value 0 to 7 outputted from the frequency divider 4 based on the frequency divider 4. Similarly, the second phase shift Δφ between the phase of the received signal RXD and the phase of the corrected synchronous extraction clock Φ2
2 continues four times, the internal control signal C is output from the counter 2B to the timing generator 2C, and the phase of the synchronization extraction clock Φ2 is corrected. Sequentially, the phase shift Δφ3,
By correcting Δφ4 to "0", the synchronous extraction clock Φ2 is fixedly outputted from the frequency dividing means 3, and a signal (=received signal RXD) is transmitted from the master device.
The transmission clock signal of the transmission signal OXD and the transmission clock signal of the transmission signal OXD output from the slave device are synchronized.

[0016] As a result, if the number of synchronization protection stages is increased more than necessary and it is set to a fixed value, the period until the phase deviations Δφ1 to Δφ4 that occur during reception are corrected to "0",
In other words, the synchronization pull-in period T becomes longer.

On the other hand, if the number of synchronization protection stages is reduced below the necessary level and set to a fixed value, a second problem occurs in that the synchronization extraction clock Φ2 is overly corrected as shown in FIG. 9(c). There is. For example, if it is assumed that the number of synchronization protection stages = 1 is set as a fixed value, in the signal waveform diagram shown in FIG. When noise 6 is mixed in the transmission clock signal φ0) related to the signal RXD, the synchronization extraction clock Φ2 is corrected every time the noise is received, and the transmission signal OX is output from the slave device to the master device.
Jitter occurs in D. Here, jitter refers to a state in which the synchronization extraction clock Φ2 is overly corrected, making the transmission clock signal unstable and the transmission signal OXD fluctuating.

[0018] This poses a problem in that the reliability of the digital signal transmitting/receiving device incorporating the DPLL circuit is reduced.

The present invention has been created in view of the problems of the prior art, and it automatically switches the number of synchronization protection stages for correcting the phase locked loop without setting it to a fixed value, so that the number of synchronization protection stages at the time of reception is The purpose of the present invention is to provide a phase-locked loop circuit and a signal transmitting/receiving device that can shorten the synchronization pull-in time, minimize sensitive phase correction during transmission, and improve the reliability of the applied device. .

[0020]

[Means for Solving the Problems] FIG. 1 is a diagram showing the principle of a phase-locked loop circuit according to the present invention, and FIG. 2 is a diagram showing the principle of a signal transmitting/receiving device according to the present invention.

As shown in FIG. 1, the phase-locked loop circuit of the present invention compares the received signal RXD and the synchronization extraction signal Φ2 to obtain a phase lead detection signal SΦ1 or a phase lag detection signal SΦ.
2, a synchronization protection control means 12 that outputs an internal control signal SR based on the phase lead detection signal SΦ1 or phase lag detection signal SΦ2, and synchronization extraction based on the internal control signal SR. The synchronization protection control means 12 is provided with a signal selection means 14 for selectively outputting the synchronization protection control signal Ci based on the transmission/reception status signal SEL. It is characterized by

Note that in the phase-locked loop circuit,
The present invention is characterized in that at least the phase detecting means 11 and the frequency dividing means 13 perform signal processing based on the reference signal Φ1.

Further, as shown in FIG. 2, the signal transmitting/receiving apparatus of the present invention includes receiving means 1 for receiving the received signal RXD.
4, a phase-locked loop means 15 for extracting the synchronization extraction signal Φ2 from the received signal RXD, a transmitting means 16 for outputting the transmission signal OXD based on the synchronization extraction signal Φ2, and the reception means 14, Phase locked loop means 1
5 and a control means 17 for controlling input and output of the transmitting means 16, and the phase-locked loop means 15 is comprised of the phase-locked loop circuit according to claim 1.

In the signal transmitting/receiving apparatus, the phase-locked loop means 15 receives the received signal RXD based on the first transmitting/receiving status signal SEL1 outputted from the receiving means 14 and indicating that synchronization is being established or trial reception is in progress. It is characterized in that the synchronous extraction signal Φ2 is extracted from the synchronous extraction signal Φ2.

Further, in the signal transmitting/receiving apparatus, the phase-locked loop means 15 extracts a synchronization extraction signal Φ2 from the received signal RXD based on a second transmitting/receiving status signal SEL2 outputted from the transmitting means 16 and indicating that transmission is in progress. It is characterized by performing extraction processing.

Furthermore, in the signal transmitting/receiving apparatus, the phase-locked loop means 15 controls the reception signal RXD based on the third transmission/reception status signal SEL3 outputted from the control means 17 and indicating that synchronization is being established or trial reception is in progress. The above object is achieved by extracting the synchronous extraction signal Φ2 from the synchronous extraction signal Φ2.

[0027]

[Operation] According to the phase-locked loop circuit of the present invention, as shown in FIG. Synchronous protection control signal C based on signal SEL
A signal selection means 14 is provided for selectively outputting i.

For example, the received signal RXD at the time of signal reception is compared with the synchronization extraction signal Φ2 fed back from the frequency dividing means 13 based on the reference signal Φ1, and the phase lead detection signal SΦ1 or phase lag detection signal SΦ2 between the two is compared. is the phase detection means 1
1 to the synchronization protection control means 12. As a result, the phase lead detection signal SΦ1 or the phase delay detection signal SΦ2
An internal control signal SR based on one synchronization protection control signal Ci is selectively outputted from the synchronization protection control means 12 to the frequency dividing means 13 from among the plurality of synchronization protection control signals Ci based on the synchronization protection control signal Ci.

That is, in the synchronization protection/control means 12, the phase lead detection signal SΦ1 or the phase delay detection signal S
When Φ2 is input to the synchronization protection/control means 12, when the signal is received, a synchronization protection control signal Ci is generated to reduce the number of synchronization protection stages based on the phase of the received signal RXD and the phase of the synchronization extraction clock Φ2. An internal control signal SR based on the selection is output to the frequency dividing means 13. At this time, the signal selection means 14 provided in the synchronization protection control means 12 selects, for example, a synchronization protection control signal Ci that sets the number of synchronization protection stages to 1 based on the transmission/reception status signal SEL. .

Furthermore, when transmitting a signal, a synchronization protection control signal Ci that increases the number of synchronization protection stages is selected based on the phase of the received signal RXD and the phase of the synchronization extraction clock Φ2, and the internal control signal SR based on the synchronization protection control signal Ci is selected to increase the number of synchronization protection stages. is frequency dividing means 1
3 is output. At this time, the signal selection means 14 selects
For example, a synchronization protection control signal Ci with a content that sets the number of synchronization protection stages to 4 is selected based on the transmission/reception status signal SEL.

Therefore, the number of synchronization protection stages for correcting the phase-locked loop is not set to a fixed value as in the conventional example, but the number of synchronization protection stages is automatically switched based on the reference signal Φ1 and the transmission/reception status signal SEL. becomes possible.

[0032] This makes it possible to shorten the synchronization pull-in time during reception and suppress excessive phase correction during transmission as much as possible, thereby improving the reliability of the application device.

Furthermore, according to the signal transmitting/receiving device of the present invention,
As shown in FIG. 2, a receiving means 14, a phase-locked loop means 15, a transmitting means 16, and a control means 17 are provided, and the phase-locked loop means 15 is constituted by a phase-locked loop circuit according to the present invention.

For example, when the reception signal RXD is received and processed by the reception means 14 from the reception communication line L1, a first signal indicating that synchronization is being established or trial reception is being outputted from the reception means 14 is output from the reception means 14.
A synchronization extraction signal Φ2 is extracted from the phase-locked loop means 15 to the control means 17 based on the transmission/reception status signal SEL1. As a result, the transmission signal OXD based on the synchronization extraction signal Φ2 is outputted from the transmission means 16 to the transmission communication line L2 via the control means 17.

For this reason, the first transmission/reception status signal SEL
1, for example, if the number of synchronization protection stages = 1 is set as a variable value, the received signal R at the time of reception as in the conventional example
When an initial phase shift occurs between the phase of XD and the phase of the synchronization extraction clock Φ2, the control release signal SR is sent from the synchronization protection/control means 12 by detecting it only once.
is output to the frequency dividing means 13. As a result, the first phase shift of the synchronization extraction clock Φ2 is immediately corrected, and similarly, the second phase shift between the phase of the received signal RXD and the corrected synchronization extraction clock Φ2 is corrected. The internal control signal C is output to the frequency dividing means 13 by only one detection. Further, the second phase shift of the synchronization extraction clock Φ2 is corrected immediately, and the third and fourth phase shifts are sequentially corrected to "0". As a result, the synchronous extraction clock Φ2 is fixedly output from the frequency dividing means 3, and the transmission clock of the signal to be transmitted from the master device (=transmission clock signal related to the reception signal RXD) and the transmission signal OXD output from the slave device. The signals are synchronized.

From this, when receiving, the period until the phase shift occurring at the time of reception is corrected to "0" by setting the number of synchronization protection stages to the minimum required, that is, the synchronization pull-in period T, is set as the conventional example. It is possible to make it shorter than .

Conversely, the first transmission/reception status signal SE
By setting the optimum value of the number of synchronization protection stages based on L1, it becomes possible to avoid excessive correction of the synchronization extraction clock Φ2 as in the conventional example. For example, if the number of synchronization protection stages = 4 is set at the time of signal transmission, which is greater than that at the time of reception, the signal (=
Even if noise is mixed in the transmission clock signal φ0) related to the reception signal RXD, the noise reception state is 4.
If the signal is not input continuously twice, the synchronization protection control means 12 will not proceed to the phase-locked loop correction process.

For this reason, at the time of transmission, the sensitive correction process of the synchronization extraction clock Φ2 as in the conventional example is avoided as much as possible. This makes it possible to suppress as much as possible the jitter that occurs in the transmission signal OXD output from the slave device to the master device, as in the conventional example.

[0039] This makes it possible to improve the reliability of the digital signal transmitting/receiving device incorporating the DPLL circuit.

Note that the second transmission/reception status signal SEL2 indicating that transmission is in progress output from the transmission means 16 and the control means 17
A similar effect can be obtained by extracting the synchronization extraction signal Φ2 from the received signal RXD based on the third transmission/reception status signal SEL3 indicating that synchronization is being established or trial reception is being outputted from the receiving signal SEL3.

[0041]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. 3 to 7 are diagrams illustrating a phase-locked loop circuit and a signal transmitting/receiving device according to each embodiment of the present invention. (1) Explanation of the first embodiment FIG. 3 is a block diagram of a digital signal phase-locked loop circuit according to the first embodiment of the present invention, and FIGS. 4 to 5 each illustrate the operation thereof. There is.

In FIG. 3, a digital signal phase-locked loop circuit (hereinafter simply referred to as a DPLL circuit) which changes the number of synchronization protection stages as appropriate based on the transmission/reception status signal SEL and outputs a fixed synchronization extraction clock Φ2 is a phase comparison circuit. circuit 21
, a synchronization protection/control circuit 22 and an 8 frequency divider 23.

That is, the phase comparison circuit 21 is an embodiment of the phase detection means 11, and is composed of an edge detection circuit 21A and a phase comparator 21B. The edge detection circuit 21A detects the change point (of the received signal RXD) based on the sampling clock, which is an example of the reference signal (hereinafter simply referred to as the original wave) Φ1.
The edge detection signal SE is output to the phase comparator 21B. The phase comparator 21B is
The phase lead or phase lag of the synchronization extraction clock Φ2 fed back from the 8-frequency divider 23 is detected based on the edge detection signal SE, and the phase lead detection signal SΦ1 or phase lag detection signal SΦ2 is sent to the synchronization protection/control circuit 22. It is output to the state machine 22A.

The synchronization protection/control circuit 22 is an embodiment of the synchronization protection control means 12, and includes a state machine 22A, a synchronization protection counter 22B, a protection stage number switching circuit 22C, and a timing generator 22D. state machine 22
A is the phase lead detection signal SΦ1 or the phase delay detection signal S
A count up signal UP or a count clear signal CLR is output to the synchronization protection counter 22B based on Φ2. Further, the state machine 22A outputs a phase state signal F/L to the timing generator D.

The synchronization protection counter 22B receives both signals UP,
The protection stage number switching circuit 22 selects a plurality of count values C1 to Cn, which are an example of the synchronization protection control signal Ci, based on the CLR.
This is what is output to C.

The protection stage number switching circuit 22C is an embodiment of the signal selection means 14, and changes the number of synchronization protection stages as appropriate based on the transmission/reception status signal SEL. In addition,
The switching circuit 22C is not provided in the conventional example, but is provided in the phase-locked loop circuit of the present invention. For example, send/
One of the first to nth count values C1 to Cn is outputted to the timing generator D based on the reception status signal SEL. Note that when receiving a signal, a count value Ci that reduces the number of synchronization protection stages is output, and when transmitting a signal, a count value Cj that increases it is output.

The timing generator 22D generates an 8 based on the phase state signal F/L outputted from the state machine 22A, the frequency divider count values 0 to 7 outputted from the 8 frequency divider 23, and the optimum count value Ci. A reset signal, which is an example of the internal control signal SR, is output to the frequency divider 23.

The 8 frequency divider 23 is an embodiment of the frequency dividing means 13, and based on the sampling clock Φ1 and the reset signal SR, the synchronous extraction clock, which is an example of the synchronous extraction signal Φ2, is transmitted to, for example, a higher-level control circuit. etc. For example, if the synchronous extraction clock Φ2 of the phase-locked loop circuit is delayed compared to the received signal RXD,
The frequency divider 23 by 8 is automatically controlled so as to advance it, and conversely, when the synchronization extraction clock Φ2 of the phase-locked loop circuit is ahead compared to the received signal RXD, the frequency is divided by 8 to delay it. The device 23 is automatically controlled. Note that the phase-locked loop circuit according to the embodiment of the present invention uses the reference signal Φ1
is frequency-divided by 8 and has a resolution of 1/8.

In this way, according to the phase-locked loop circuit for digital signals according to the first embodiment of the present invention, as shown in FIG.
As shown in FIG.
2 and 8 frequency dividers 23 are provided, and the synchronization protection/control circuit 22 includes a state machine 22A and a synchronization protection counter 22B.
, protection stage number switching circuit 22C and timing generator 2
It consists of 2D.

For example, a DPLL as shown in FIG. 4(a)
In the operation time chart of the phase comparator circuit 21 of the circuit, first, the rising edge ■ of the received signal RXD during signal reception is detected by the edge detecting circuit 21A in synchronization with the rising edge ■ of the reference signal Φ1, and the edge detection signal SE is detected in phase. It is output to the comparison circuit 21B. Here, the received signal R
It is assumed that the rising edge (■) of XD causes a phase shift Δφ compared to the synchronous extraction clock Φ2 fed back from the 8 frequency divider 23.

Furthermore, in the phase comparator 21B, as shown in FIG.
In the operation time chart of the DPLL circuit as shown in FIG. 2, the lead or lag state of the synchronization extraction clock Φ2 is compared based on the reference signal Φ1 and the edge detection signal SE, and the phase lead detection signal SΦ1 or phase lag detection signal between the two is compared. S
Φ2 is output from the phase comparator 21B to the state machine 22A of the synchronization protection control circuit 22.

[0052] As a result, the synchronization protection control circuit 22 and the frequency divider 23 as shown in FIG.
In the extracted configuration diagram, the phase advance detection signal SΦ1
Alternatively, a reset signal SR based on one count value Cout1 from among a plurality of synchronization protection count values Cout1, Cout2 .

That is, in the synchronization protection control circuit 22, the phase lead detection signal SΦ1 or the phase lag detection signal SΦ2
is input to the synchronization protection counter 22B, when receiving the signal, the phase of the received signal RXD and the synchronization extraction clock Φ
The count value Cou has a content that reduces the number of synchronization protection stages for correcting the phase-locked loop circuit based on the phase of No. 2.
t1 is selected. For example, the timing generator 22D sets the count value Cout1 such that the protection stage number switching circuit 22C provided in the synchronization protection control circuit 22 sets the number of synchronization protection stages to 1 based on the transmission/reception status signal SEL.
is selected and output.

At this time, in the state transition diagram of the synchronization protection control circuit 22 as shown in FIG. is being detected, the count-up signal UP is output to the synchronization protection counter 21B so that it is delayed, and on the other hand, when the synchronization extraction clock Φ2 of the phase-locked loop circuit is delayed compared to the received signal RXD. Then, a count clear signal CLR is output to the synchronization protection counter 21B to advance it. As a result, a reset signal SR based on the state control signal F/L output from the state machine 22A and the count value Cout1 selectively output to the timing generator 22D is generated.
is output to the 8 frequency divider 23.

In addition, in the 8 frequency divider 23, in the operation time chart of the frequency divider as shown in FIG. The internal count value of the 8 frequency divider = "0" is counted twice and counted again from "0" to "7". That is, when correcting the delay of the synchronization extraction clock Φ2, one original oscillation period is added to one bit rate of the received signal RXD by the frequency divider 23 by eight based on the sampling clock Φ1 and the reset signal SR.

Note that when correcting the advance of the synchronization extraction clock Φ2, the advance of the synchronization extraction clock Φ2 is adjusted based on the reset signal SR serving as the advance correction pulse output from the timing generator 22D.
The internal count value = "7" of the frequency divider is omitted, and the count value = "6" is followed by counting from "0" to "7". That is, when correcting the advance of the synchronization extraction clock Φ2, one original period is subtracted from one bit rate of the received signal RXD by the frequency divider 23 by eight based on the sampling clock Φ1 and the reset signal SR.

In this case, one bit rate corresponds to one cycle of the synchronization extraction clock Φ2 in FIG. 6(b), and refers to one unit in which the received signal RXD is transmitted during the one cycle. As a result, the rising edge of the received signal RXD and the 8 frequency divider 2
The phase shift Δφ that had occurred between the signal RXD and the synchronized extraction clock Φ2 fed back from the signal RXD and the synchronization extraction clock Φ2 fed back from the signal RXD and the synchronization extraction clock Φ2 is eliminated, and both the signals RXD and Φ2 are brought into a synchronous state.

Furthermore, when transmitting a signal, a count value Cout4 is selected that increases the number of synchronization protection stages for correcting the phase-locked loop circuit based on the phase of the received signal RXD and the phase of the synchronization extraction clock Φ2. For example, the reset signal SR based on the count value Cout4 with the contents such that the protection stage number switching circuit 22C provided in the synchronization protection control circuit 22 sets the number of synchronization protection stages to 4 based on the transmission/reception status signal SEL is set to a frequency divider of 8. 23.

Note that the function of the state machine 22A at this time is the same as the state transition of the synchronization protection control circuit described above, so a description thereof will be omitted (see FIG. 5(b)).

This makes it possible to automatically switch the number of synchronization protection stages based on the transmission/reception status signal SEL, without setting the number of synchronization protection stages for correcting the phase-locked loop to a fixed value as in the conventional example. Become.

[0061] As a result, the synchronization pull-in time during reception can be shortened, and sensitive phase correction during transmission can be suppressed as much as possible, making it possible to improve the reliability of the application device. (2) Description of Second Embodiment FIG. 7 shows a configuration diagram of a digital signal transmitting/receiving apparatus according to a second embodiment of the present invention.

For example, in a digital signal transmitting/receiving device used in an ISDN network that centrally provides various types of communication services such as voice, image, and data, in the case of a full-duplex communication system, a receiving input unit is shown in FIG. 24, DPLL circuit 2
5, transmission output unit 26, data terminal control unit 2
7, a keyboard 28, a display 29, etc.

That is, the reception input unit 24 is an embodiment of the reception means 14, and receives the reception signal RXD.
It performs demodulation processing and outputs the received data DIN to the data terminal control unit 27. Further, the reception input unit 24 is connected to the reception communication line L1, and performs reception processing of the reception signal RXD based on a communication protocol (common protocol). In addition, reception input unit 2
4 indicates that the DPLL circuit 25 is establishing synchronization or undergoing trial reception (during a sync character signal).
It outputs a transmission/reception status signal SEL1.

The DPLL circuit 25 is a phase-locked loop means 1.
5, and the first to third transmission/reception status signals S
Received signal R based on any one of EL1 to SEL3
It extracts the synchronous extraction clock Φ2 from the XD and outputs it to the data terminal control unit 27. Note that the DPLL circuit 25 is composed of a digital signal phase-locked loop circuit according to the first embodiment of the present invention. For example, when the signal transmitting/receiving device becomes a slave (sub transmitting/receiving device) device, the synchronization extracted from the signal transmitted and processed from the master (main signal transmitting/receiving device) device (received signal RXD on the slave device side) The extracted clock Φ2 is output to the data terminal control unit 27.

The transmission output unit 26 is an embodiment of the transmission means 16, and performs modulation processing on the transmission data DOUT based on the synchronization extraction clock Φ2, and outputs it as the transmission signal O.
It outputs as XD. Note that the transmission output unit 26 is connected to the transmission communication line L2, and performs transmission processing of the transmission signal OXD based on a common protocol. Further, in another embodiment, the transmission output unit 26 outputs a second transmission/reception status signal SEL2 indicating that transmission is in progress to the DPLL circuit 2.
This is what is output to 5.

The data terminal control unit 27 is the control means 1
7, the receiving input unit 24, DPLL
It controls the input/output of the circuit 25, transmission/output unit 26, keyboard 28, and display 29. For example, the output of the transmission data DOUT input by the user is controlled to the transmission output unit 26, or the reception input unit 2
It controls the input of the received data DIN output from 4. In other embodiments, the data terminal control unit 27 outputs a third transmission/reception status signal SEL3 indicating that synchronization is being established or trial reception is in progress to the DPLL circuit 25.

The keyboard 28 is used by the user to input data to be transmitted and control data related to data transmission. The display 29 performs display processing based on display data of the transmitted data DOUT and the received data DIN.

In this way, according to the signal transmitting/receiving device according to the second embodiment of the present invention, as shown in FIG. 27, keyboard 28
and a display 29, and the DPLL circuit 25
consists of a digital signal phase-locked loop circuit according to the present invention.

For example, when the reception signal RXD is received and processed by the reception input unit 24 from the reception communication line L1, the first transmission/transmission signal RXD indicating that synchronization is being established or a sync character is being received is output from the reception input unit 24. Reception status signal S
A synchronous extraction clock Φ2 is extracted from the DPLL circuit 25 to the data terminal control unit 27 based on EL1. As a result, the transmission signal OXD based on the synchronization extraction clock Φ2 is outputted from the transmission output unit 26 to the transmission communication line L2 via the data terminal control unit 27.

For this reason, the first transmission/reception status signal SEL
1, for example, if the number of synchronization protection stages = 1 is set as a variable value, the received signal R at the time of reception as in the conventional example
When an initial phase shift occurs between the phase of XD and the phase of the synchronization extraction clock Φ2, the synchronization protection/control circuit 22 generates a signal based on the synchronization protection counter value Cout1 by detecting it only once. Reset signal SR is divided by 8 frequency divider 23
is output to. As a result, the first phase shift of the synchronization extraction clock Φ2 is immediately corrected, and similarly, the phase shift of the received signal RXD and the second phase of the corrected synchronization extraction clock Φ2 is only one time. Upon detection, the reset signal SR is output to the frequency divider 23 by eight. Further, the second phase shift of the synchronization extraction clock Φ2 is immediately corrected, and the third and fourth phase shifts are sequentially corrected to "0". As a result, the synchronous extraction clock Φ2 is fixedly outputted from the frequency divider 23 by 8, and the signal to be transmitted from the master device (=transmission clock signal φ0 related to the reception signal RXD) and the transmission signal O output from the slave device.
The XD transmission clock signal is brought into synchronization early.

From this, when receiving, the period until the phase shift occurring at the time of reception is corrected to "0" by setting the number of synchronization protection stages to the minimum required, that is, the synchronization pull-in period T, is set as the conventional example. It is possible to make it shorter than .

Conversely, the first transmission/reception status signal SE
By setting the optimum value of the number of synchronization protection stages based on L1, it becomes possible to avoid excessive correction of the synchronization extraction clock Φ2 as in the conventional example. For example, if the number of synchronization protection stages = 4 is set at the time of signal transmission, which is greater than that at the time of reception, the signal (=
Even if noise is mixed in the transmission clock signal φ0) related to the reception signal RXD, the noise reception state is 4.
If the signal is not input continuously twice, the synchronization protection control circuit 22 will not proceed to the phase-locked loop correction process.

Therefore, at the time of transmission, the sensitive correction process of the synchronization extraction clock Φ2 as in the conventional example is avoided as much as possible. This makes it possible to suppress as much as possible the jitter that occurs in the transmission signal OXD output from the slave device to the master device, as in the conventional example.

[0074] This makes it possible to improve the reliability of the digital signal transmitting/receiving device incorporating the DPLL circuit.

In the second embodiment of the present invention, a case has been described in which the synchronization extraction clock Φ2 is extracted based on the first transmission/reception status signal SEL1. The synchronization extraction clock is extracted from the reception signal RXD based on the second transmission/reception status signal SEL2 indicating that the synchronization is being established or the third transmission/reception status signal SEL3 that is output from the data terminal control unit 27 and indicating that synchronization is being established or trial reception is in progress. A similar effect can be obtained by performing extraction processing of Φ2.

[0076]

As explained above, the phase-locked loop circuit of the present invention is provided with a phase detection means, a synchronization protection control means, and a frequency division means, and the synchronization protection control means is provided with a transmission/reception status signal SEL. A signal selection means is provided for selectively outputting a synchronization protection control signal based on the synchronization protection control signal.

Therefore, an internal control signal based on one synchronization protection control signal selected from a plurality of synchronization protection control signals based on a phase lead detection signal or a phase lag detection signal between the received signal and the synchronization extraction signal. It becomes possible to automatically control the frequency dividing means based on. This makes it possible to automatically switch the number of synchronization protection stages based on the reference signal and the transmission/reception status signal, without having to set the number of synchronization protection stages for correcting the phase-locked loop to a fixed value as in conventional examples. Become.

Further, the signal transmitting/receiving apparatus of the present invention is provided with receiving means, phase-locked loop means, transmitting means, and control means, and the phase-locked loop means is constituted by the phase-locked loop circuit according to the present invention.

Therefore, at the time of reception, by setting the number of synchronization protection stages to the necessary minimum, it is possible to shorten the synchronization pull-in period compared to the conventional example. Conversely, by setting the optimal value for the number of synchronization protection stages based on the first, second, or third transmission/reception status signal, excessive correction of the synchronization extraction clock as in the conventional example is avoided as much as possible. It becomes possible to do so. This makes it possible to suppress jitter as much as possible as in the conventional example.

[0080] This improves the reliability of the phase-locked loop circuit, which greatly contributes to the provision of a highly reliable and high quality data communication transmitting/receiving device that is applied to an integrated digital communication service network.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of a phase-locked loop circuit according to the present invention.

FIG. 2 is a principle diagram of a signal transmitting/receiving device according to the present invention.

FIG. 3 is a configuration diagram of a phase-locked loop circuit for digital signals according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram (Part 1) of the operation of the DPLL circuit according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram (part 2) of the operation of the DPLL circuit according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram (part 3) of the operation of the DPLL circuit according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a digital signal transmitting/receiving device according to a second embodiment of the present invention.

FIG. 8 is an explanatory diagram of a phase-locked loop circuit for digital signals according to a conventional example.

FIG. 9 is a circuit configuration diagram and a signal waveform diagram illustrating problems related to a conventional example.

[Explanation of symbols]

11... Phase detection means, 12... Synchronization protection control means, 13... Frequency division means, 14... Receiving means, 15... Phase locked loop means, 16... Transmitting means, 17... Control means, 12A... Signal selection means, RXD... Reception Signal, SΦ1...Phase lead detection signal, SΦ2...Phase lag detection signal, SR...Internal control signal, Φ2...Synchronization extraction signal, SEL, SEL1 to SEL3...Transmission/reception status signal, first
~Third transmission/reception status signal, Ci...Synchronization protection control signal, OXD...Transmission signal, L1...Reception communication line, L2...Transmission communication line.

Claims (6)

[Claims] [Claim 1] A received signal (RXD) and a synchronization extraction signal (
Φ2) and outputs a phase lead detection signal (SΦ1) or a phase lag detection signal (SΦ2).
1), a synchronization protection control means (12) that outputs an internal control signal (SR) based on the phase lead detection signal (SΦ1) or the phase lag detection signal (SΦ2), and and frequency dividing means (13) for outputting a synchronization extraction signal (Φ2) based on the transmission/reception status signal (SEL) to the synchronization protection control means (12). Signal selection means (
14) A phase-locked loop circuit comprising: 2. The phase-locked loop circuit according to claim 1, wherein at least the phase detection means (11) and the frequency division means (13) perform signal processing based on a reference signal (Φ1). Phase-locked loop circuit. 3. Receiving means (14) for receiving a received signal (RXD); phase-locked loop means (15) for extracting a synchronization extraction signal (Φ2) from the received signal (RXD); a transmitting means (16) that performs output processing of a transmitting signal (OXD) based on the synchronization extraction signal (Φ2);
control means (17) for controlling input and output of the receiving means (14), phase-locked loop means (15) and transmitting means (16);
), wherein the phase-locked loop means (15) comprises the phase-locked loop circuit according to claim 1. 4. The signal transmitting/receiving device according to claim 3, wherein the phase-locked loop means (15) is connected to the receiving means (
14) extracts the synchronization extraction signal (Φ2) from the received signal (RXD) based on the first transmission/reception status signal (SEL1) indicating that synchronization is being established or trial reception is in progress. A signal transmitting and receiving device. 5. The signal transmitting/receiving device according to claim 3, wherein the phase-locked loop means (15) is connected to the transmitting means (15).
16) A signal transmitting/receiving device characterized in that a synchronization extraction signal (Φ2) is extracted from a received signal (RXD) based on a second transmitting/receiving status signal (SEL2) indicating that transmission is in progress outputted from the transmitting/receiving device. 6. The signal transmitting/receiving device according to claim 3, wherein the phase-locked loop means (15) controls the control means (
17) extracts the synchronization extraction signal (Φ2) from the received signal (RXD) based on the third transmission/reception status signal (SEL3) indicating that synchronization is being established or trial reception is in progress. A signal transmitting and receiving device.