JP2002064477A - Device and method for phase locking - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for phase locking with which a phase of a 1S periodic frame pulse can be matched with a phase of an external reference clock easily and the phase can be matched at a speed at which frequency of an oscillator is synchronized. SOLUTION: A second frequency divider 20 is used to match a phase of a clock obtained by dividing a clock from an oscillator 60 for comparing phases by a phase comparator 30 constituting a frequency locking circuit, and a phase of a 1S periodic frame pulse generated by a clock conversion unit 70 periodically. A phase of a reference clock received from an external device (not shown), and a phase of the 1S periodic frame pulse frequency generated by the clock conversion unit 70 at a later stage in the frequency locking circuit, are synchronized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronizing technique using a frequency synchronizing circuit. In particular, the present invention can easily adjust the phase of a 1S-period frame pulse to the phase of an external reference clock. The present invention relates to a phase synchronizing apparatus and a phase synchronizing method that can adjust the phase at a speed for synchronizing the frequency of an oscillator even when the phase of a 1S cycle frame pulse is shifted with respect to an external reference 8 KHz clock.

[0002]

2. Description of the Related Art As a conventional phase synchronization technique using a frequency synchronization circuit, for example, there is one described in Japanese Patent Application Laid-Open No. 10-224336 (first prior art). That is, the first prior art aims to establish a high-speed phase synchronization between an input reference clock and a reproduction clock, and to generate a reproduction clock having a frequency corresponding to the input control voltage. A phase-locked loop that includes a voltage-controlled oscillator for output and forms a recovered clock synchronized with the input reference clock; a phase difference detection unit that detects a phase difference between the reference clock and the recovered clock; A control voltage is input, and a phase difference from the phase difference detection means at that time is taken in. Based on the trial control voltage and the detected phase difference, characteristic information of the input control voltage and the output oscillation frequency in the voltage controlled oscillator is obtained. And an oscillation frequency for determining the oscillation frequency of the voltage-controlled oscillator for eliminating the current phase difference from the phase difference detection means. A constant section, the determined oscillation frequency, based on the characteristic information approximator means is obtained, a phase locked loop circuit and a control voltage determining means for determining a control voltage to be input to the voltage controlled oscillator.

The first prior art includes a voltage-controlled oscillator that outputs a reproduced clock having a frequency corresponding to an input control voltage, and a phase-controlled oscillator that forms a reproduced clock synchronized with the input reference clock. In a synchronous circuit, a phase difference detecting means for detecting a phase difference between a reference clock and a reproduced clock, and a trial control voltage are input to a voltage-controlled oscillator, and the phase difference from the phase difference detecting means at that time is taken in, and a trial control voltage is obtained. And based on the detected phase difference,
Characteristic approximation means for obtaining characteristic information between an input control voltage and an output oscillation frequency in a voltage-controlled oscillator, and an oscillation frequency for determining an oscillation frequency of the voltage-controlled oscillator for eliminating a current phase difference from a phase difference detection means Determining means, control voltage determining means for determining a control voltage to be input to the voltage-controlled oscillator based on the determined oscillation frequency and characteristic information obtained by the characteristic approximating means, and a phase difference from the phase difference detecting means. Filter means for performing filtering on to determine a control voltage to be input to the voltage-controlled oscillator,
In the initial state of the phase synchronization process between the reference clock and the recovered clock, the control voltage determined by the control voltage determining means is input to the voltage controlled oscillator, and after the initial state, the control voltage determined by the filter means is controlled by the voltage controlled oscillator. There is also disclosed a phase locked loop having a control voltage selection means for inputting the control voltage to the control circuit.

According to the first prior art, it is possible to establish synchronization at high speed, to shorten the time until the phase synchronization is established, and to reduce the residual jitter in the reproduced clock. Is disclosed.

As another conventional technique, for example, there is one described in Japanese Patent Application Laid-Open No. 9-205362 (see
Prior art). That is, the second prior art aims at minimizing the fluctuation of the phase synchronization response to the fluctuation of the circuit characteristic in the reproduction signal processing circuit of the magnetic recording / reproducing apparatus. , Which has an adjusting means for adjusting a phase synchronization response to an input signal to a predetermined phase synchronization response.

In the second prior art, there is provided a phase synchronization device for generating an output signal synchronized with an input signal, wherein a phase synchronization response to a known input signal coincides with a phase synchronization response uniquely determined in advance. The disclosed phase synchronizer is also disclosed.

Further, the second prior art is a phase synchronizer for generating an output signal synchronized with an input signal, the phase synchronizer responding to a known input signal at first, second, and third times. Out of which, the phase synchronization response at the third time is determined based on the second phase synchronization response, and the second phase synchronization response is determined based on the first phase synchronization response. There is also disclosed a phase synchronization apparatus characterized in that the phase synchronization response at time 3 coincides with the phase synchronization response uniquely determined in advance.

According to the second prior art, it is possible to reduce the variation in the phase synchronization time due to the characteristic fluctuation of the phase synchronizer, and to minimize the decrease in the recording capacity of the information recording / reproducing apparatus. Can be suppressed, phase synchronization can be completed in a standard phase synchronization period of 15 bytes, and the characteristics of the phase synchronization device can be adjusted to a phase synchronization time of 12.3 bytes. Is disclosed.

Further, as another conventional technique, for example, there is one described in Japanese Patent Application Laid-Open No. 8-107532 (third patent application).
Prior art). That is, the third prior art aims to provide a communication circuit that can accurately detect the level of a transmitted signal without impairing compatibility with a conventional communication circuit. Communication means for performing full-duplex communication or one-way communication; detection means for detecting operation information supplied from at least one external device via the communication means; and internal input according to a detection result of the detection means And control means for performing switching control of an external input. The control means, when the operation information is detected by the detection means, switches to an input from an external device corresponding to the detected operation information and operates. This is an input switching control device that controls to perform an operation based on information.

The third prior art is a communication circuit for performing full-duplex two-way communication or one-way communication by detecting a transmission level on a transmission side, wherein a voltage V1 of a transmission signal on a reception side is provided.
It has a transmission impedance R1 on the reception side, a voltage V2 of a transmission signal on the transmission side, a transmission impedance R2 on the transmission side, and a voltage V3 of a transmission signal transmitted to the reception side via a control line connecting the transmission side and the reception side. And K = R1 / (R1 + R
2) V1 = V3−K × V1 The first calculation unit that performs the calculation, and the calculation result V4 of the first calculation unit, V
5 = 2 × V4;
There is also disclosed a communication circuit that detects the transmission level on the transmission side by using the voltage V5 obtained by the first and second operation means as the voltage V2 of the transmission signal on the transmission side.

According to the third prior art, it is possible to automatically switch between an internal input and an external input according to operation information from a device connected to the device provided with the input switching control device. Therefore, there is disclosed an effect that the device can be connected to a conventional device and the connection between the devices can be easily performed.

[0012]

However, in the first to third prior arts, the frequency of the oscillator clock can be synchronized with a reference clock from an external device constituting a frequency synchronization circuit. In addition, there has been a problem that the frequency of the divided clock and the frame pulse generated from the clock of the oscillator cannot be matched with the reference clock from the external device at any time. Therefore, in order to perform phase matching of the divided clock and the frame pulse with the reference clock of the external device, there is a problem that a phase matching circuit must be formed separately from the frequency synchronization circuit.

The present invention has been made in view of such a problem, and an object thereof is to easily adjust the phase of a 1S-period frame pulse to the phase of an external reference clock, and to reduce noise and the like. It is an object of the present invention to provide a phase synchronizing apparatus and a phase synchronizing method that can adjust the phase at a speed for synchronizing the frequency of the oscillator even when the phase of the 1S cycle frame pulse is shifted from the external reference 8 kHz clock due to the influence. .

[0014]

The gist of the present invention is that an external reference 8K received from an external device.
A first frequency divider for generating and outputting a frequency-divided 4 KHz clock for frequency-dividing the Hz clock and synchronizing the frequency of the clock of the oscillator, and a 1S-period frame pulse from the oscillator as a 1-second frame pulse 8K for dividing the frequency and performing frequency synchronization of the clock of the oscillator
A second frequency divider for generating and outputting a frequency clock, and a phase of a clock obtained by dividing a clock from the oscillator for phase comparison by a phase comparator constituting a frequency synchronization circuit. There is provided a phase synchronization device having means for performing phase matching with the phase of the generated 1S cycle frame pulse by the second frequency divider. The gist of the invention described in claim 2 of the present invention is as follows.
2. The apparatus according to claim 1, further comprising means for synchronizing a frequency and a phase of the reference clock received from the external device with a frequency and a phase of the 1S cycle frame pulse generated by the clock conversion unit subsequent to the frequency synchronization circuit. In the described phase synchronizer. The gist of the invention according to claim 3 of the present invention resides in that the 1S-period frame pulse received from the clock conversion unit is input to a load signal of a counter of the second frequency divider and a clock for operating the counter. 3. The phase synchronization apparatus according to claim 2, wherein a 16.384 MHz clock which is a 16.384 MHz clock of the oscillator is used. The gist of the invention described in claim 4 of the present invention is that there is provided means for outputting an output phase of the frequency-divided 8 KHz clock a predetermined time after a rising edge of the 1S-period frame pulse. 3. The phase synchronizer according to item 3. The gist of the invention described in claim 5 of the present invention is that the phase comparator includes a counter that counts from a rising edge of the divided 4 kHz clock to a rising edge of the divided 8 kHz clock. A phase synchronizer according to any one of claims 2 to 4, characterized in that: The gist of the invention described in claim 6 of the present invention is to have a control unit having means for performing frequency synchronization based on the phase difference count value and transmitting control data to the D / A conversion unit. The phase synchronizer according to any one of claims 2 to 5, wherein: The gist of the invention described in claim 7 of the present invention resides in that the D / A converter has means for converting the control data from the controller into an oscillator control voltage and controlling the oscillator. The phase synchronizer according to claim 6, wherein: The gist of the invention described in claim 8 of the present invention is that the clock conversion unit has a function of generating a frame pulse of one second cycle from the 16.384 MHz clock, and a function of synchronizing with the 1S cycle frame pulse. The phase synchronizer according to any one of claims 2 to 7, further comprising means for reloading the counter and loading the counter into the second frequency divider. Further, the gist of the invention according to claim 9 of the present invention is that, when duplexing is performed using an active system and a protection system, means for transmitting and receiving the 1S cycle frame pulse between an active system and a protection system, 9. The apparatus according to claim 1, wherein a selector is provided in a stage preceding an input portion of the load signal of the clock converter, and the load signal is controlled by a select signal from the selector. In the described phase synchronizer. The gist of the invention described in claim 10 of the present invention resides in that a first divided 4 KHz clock for dividing the frequency of an external reference 8 KHz clock received from an external device and performing frequency synchronization of an oscillator clock is provided. Generating and outputting by using an oscillator, and a frequency divider of 8 KH for frequency-dividing a 1S-period frame pulse from the oscillator to perform frequency synchronization of a clock of the oscillator.
generating and outputting a z clock by using a second frequency divider; and periodically dividing a phase of a clock obtained by dividing a clock from the oscillator for phase comparison by a phase comparator constituting a frequency synchronization circuit. The 1S generated by the clock converter
The phase synchronization method includes a step of performing phase matching with a phase of a periodic frame pulse by the second frequency divider. The gist of the invention described in claim 11 of the present invention resides in that a reference clock received from the external device and a frequency and a phase of the 1S-period frame pulse generated by the clock conversion unit subsequent to the frequency synchronizing circuit. 11. The step of synchronizing
In the phase synchronization method described in (1).

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a 1S cycle in which a clock converter periodically generates a clock phase obtained by dividing a clock from an oscillator for phase comparison by a phase comparator constituting a frequency synchronization circuit. By performing the phase and phase adjustment of the frame pulse by the second frequency divider, the reference clock received from the external device (not shown) and the 1S-period frame pulse generated by the clock conversion unit at the subsequent stage of the frequency synchronization circuit can be used. It is characterized in that frequency and phase can be synchronized. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a functional block diagram for explaining a phase synchronizer 100 according to a first embodiment of the present invention, and FIG. 2 is a block diagram of the first embodiment. 6 is a timing chart for explaining an operation. 1, reference numeral 10 denotes a first frequency divider, 20 denotes a second frequency divider, 30 denotes a phase comparator, 40 denotes a control unit, 50 denotes a D / A converter, and 60 denotes a D / A converter.
Denotes an oscillator, 70 denotes a clock converter, and 100 denotes a phase synchronizer.

Referring to FIG. 1, a phase synchronizer 100 according to the present embodiment includes a first frequency divider 10 and a second frequency divider 20.
, Phase comparator 30, control unit 40, D / A conversion unit 5
0, an oscillator 60, and a clock converter 70.

As shown in FIG. 1, in this embodiment, a first frequency divider for generating and outputting a frequency-divided 4 kHz clock for performing frequency synchronization of the clock of the oscillator 60 by dividing the frequency of the external reference 8 kHz clock. And a second 8K clock for generating and outputting a frequency-divided 8 KHz clock for performing frequency synchronization of the clock of the oscillator 60 by dividing the 1S-period frame pulse, which is a 1-second frame pulse, from the oscillator 60.
A frequency divider 20 is provided.

Here, in the second frequency divider 20 that divides the frequency of the clock from the oscillator 60, the frame pulse having a one-second cycle (1S cycle frame pulse) received from the clock converter 70 is input to the load signal of the counter. 16.384 of the oscillator 60 is used as a clock for operating the counter.
MHz clock (16.384 MHz clock) is used.

The output phase of the frequency-divided 8 KHz clock shown in FIG. 2 is configured to be output after 62.5 μsec (predetermined time) from the rising edge of the 1S-period frame pulse.

The phase comparator 30 includes a counter that counts from the rising edge of the frequency-divided 4 kHz clock to the rising edge of the frequency-divided 8 kHz clock.

The control section 40 has a function of performing frequency synchronization based on the phase difference count value and transmitting control data to the D / A conversion section 50.

The D / A converter 50 has a function of converting control data from the controller 40 into an oscillator control voltage and controlling the oscillator 60.

The clock converter 70 has a frequency of 16.384 MH.
It has a function of generating a frame pulse of 1 second cycle from the z clock, a function of reloading its own counter in synchronization with a frame pulse of 1S cycle, and a function of loading a counter into the second frequency divider 20.

Next, the phase synchronizer 100 of the present embodiment
Will be described.

Referring to FIG. 1, in the phase synchronizer 100 of the present embodiment, in order to perform frequency synchronization with a reference clock from an external device (not shown), a first frequency divider shown in FIG. In step 10, the external reference 8 KHz clock is frequency-divided by を to generate and output a frequency-divided 4 KHz clock.

Further, one of the oscillators 60 for frequency synchronization
6.384 MHz clock is 1/20 divided by the second frequency divider 20
The frequency is divided by 48 and output as a clock of frequency division 8 KHz (frequency division 8 KHz clock).

External reference 8 KHz in phase comparator 30
The phase difference between the divided 4 KHz clock generated by dividing the clock and the 8 KHz clock obtained by dividing the clock from the oscillator 60 is expressed by the clock from the oscillator 60 (16.384M).
(Hz clock) to generate and output a phase difference count value, and transmit the phase difference count value to the control unit 40.

In response, the control unit 40 controls the phase comparator 3
The control data for synchronizing the frequency of the clock of the oscillator 60 based on the phase difference count value from 0 is transmitted to the D / A converter 5.
Send to 0.

In response, the D / A converter 50 converts the control data from the controller 40 into an oscillator control voltage and applies the oscillator control voltage to the oscillator 60 to control the oscillator 60. .

The clock conversion unit 70 converts the frequency-synchronized 16.384 MHz clock of the oscillator 60 to 8.192 MHz.
It generates and outputs an MHz clock, a frame pulse of 2 ms cycle, a frame pulse of 1S cycle, and the like.

The 1S cycle frame pulse generated by the counter of the clock converter 70 is loaded to the counter of the second frequency divider 20. Also, the frequency division of the second frequency divider 20 is 8 kHz.
The clock is used to adjust the phase of the 1S cycle frame pulse.

As described above, the first embodiment is as follows.
The phase of the clock obtained by dividing the clock from the oscillator 60 for phase comparison by the phase comparator 30 constituting the frequency synchronization circuit and the 1S periodically generated by the clock conversion unit 70
By performing phase matching with the phase of the periodic frame pulse in the second frequency divider 20, the reference clock received from an external device (not shown) and the 1S generated by the clock conversion unit 70 at the subsequent stage of the frequency synchronization circuit. There is an effect that the frequency and the phase of the periodic frame pulse can be synchronized.

Next, an embodiment of the phase synchronization method will be described with reference to FIGS.

As shown in FIGS. 1 and 2, in the phase synchronization method according to the present embodiment, first, the frequency divider 4 KHz clock is used, and the counter of the first frequency divider 10 is set at the rising edge of the external reference 8 KHz clock. Make it work.

Further, based on the 16.384 MHz clock of the oscillator 60, the phase of the 1S-period frame pulse generated by the clock converter 70 is arbitrarily determined.

Thereafter, as shown in the timing chart of FIG. 2, when the second frequency divider 20 generates the frequency-divided 8 KHz clock, the second frequency divider 20 generates the clock after 62.5 μsec (predetermined time) from the rising edge of the 1S cycle frame pulse. 8KH around
Second so that the rising edge of the z clock is generated
The counter value of the frequency divider 20 is set. Thereby, 1S
The rising edge of the frequency-divided 8 kHz clock with respect to the periodic frame pulse is output after 62.5 μsec (predetermined time) from the rising edge of the 1S periodic frame pulse.

In synchronization with this, the phase comparator 30 counts from the rising edge of the frequency-divided 4 kHz clock to the rising edge of the frequency-divided 8 kHz clock with the 16.384 MHz clock, and the control section 40 counts the phase difference so that the frequency is synchronized. Calculate control data based on the value. Therefore, when the frequency is synchronized, the rising edge of the frequency-divided 8 kHz clock is output after 62.5 μsec (predetermined time) with respect to the rising edge of the frequency-divided 4 kHz clock.

That is, the frequency-divided 8 KHz clock obtained by dividing the clock of the oscillator 60 has the same phase as the 1S-period frame pulse generated by the clock converter 70, and at the same time, the frequency obtained by dividing the frequency of the external reference 8 KHz clock. Since the phase of the peripheral 4 KHz clock is determined with the external reference 8 KHz clock, the frequency synchronization is performed as described above, so that the phase synchronization between the 1S cycle frame pulse generated by the clock conversion unit 70 and the external reference 8 KHz clock is achieved. You can take it.

As described above, according to the first embodiment, the following effects can be obtained. First, the first effect is that the 1S cycle frame pulse generated by the clock of the oscillator 60 synchronized with the external reference 8 KHz clock is phase-matched by the frequency divider in the frequency synchronization circuit, so that the phase of the external reference clock can be easily adjusted. That is, the phase of the 1S cycle frame pulse can be matched.

The second effect is that even when the phase of the 1S-period frame pulse is shifted with respect to the external reference 8 KHz clock due to the influence of noise or the like, the phase can be adjusted at the speed for synchronizing the frequency of the oscillator 60. is there.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described in detail with reference to the drawings. In addition,
The same parts as those already described in the first embodiment are denoted by the same reference numerals, and duplicate description will be omitted.

FIG. 3 is a functional block diagram illustrating a phase synchronizer 100 according to a second embodiment of the present invention. In FIG. 3, reference numeral 80 denotes a selector.

Referring to FIG. 3, the present embodiment is different from FIG.
As shown in (1), when duplication is performed using an active system and a protection system based on this configuration, means for transmitting and receiving 1S cycle frame pulses between the working system and the protection system, and a load signal of the clock conversion unit 70 A feature is that a selector 80 is provided at a stage preceding the input portion, and a load signal is controlled by a select signal. As a result, one of the working system and the non-working system
There is an effect that the phase of the S period frame pulse can be synchronized with the external reference 8 KHz clock.

It is apparent that the present invention is not limited to the above embodiments, and that the above embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiments, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0046]

Since the present invention is configured as described above, the following effects can be obtained. First, the first effect is that the 1S periodic frame pulse generated by the clock of the oscillator synchronized with the external reference 8 KHz clock is phase-aligned by the frequency divider circuit frequency divider, whereby the phase of the external reference clock can be easily adjusted by 1S. That is, the phase of the periodic frame pulse can be matched.

The second effect is that even when the phase of the 1S-period frame pulse deviates from the external reference 8 KHz clock due to the influence of noise or the like, the phase can be adjusted at the speed for synchronizing the frequency of the oscillator. .

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a phase synchronizer according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a functional block diagram for explaining a phase synchronization device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... 1st frequency divider 20 ... 2nd frequency divider 30 ... Phase comparator 40 ... Control part 50 ... D / A conversion part 60 ... Oscillator 70 ... Clock conversion part 80 ... Selector 100 ... Phase synchronization device

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasunori Aoki 5-7-1 Shiba, Minato-ku, Tokyo F-term within NEC Corporation 5J106 AA04 CC01 CC25 CC52 DD35 KK03 KK27 5K028 AA04 AA06 5K047 AA01 AA05 GG09 GG24 GG44 MM44 MM49 MM53 MM55 MM63

Claims (11)

[Claims] 1. An external reference 8 KHz received from an external device.
A first frequency divider for generating and outputting a frequency-divided 4 kHz clock for frequency-dividing the clock to synchronize the frequency of the oscillator clock, and 1S, which is a one-second cycle frame pulse from the oscillator
For phase comparison between a second frequency divider for generating and outputting a frequency-divided 8 kHz clock for frequency-dividing a periodic frame pulse and performing frequency synchronization of the oscillator clock, and a phase comparator constituting a frequency synchronization circuit Means for performing phase matching between the phase of the clock obtained by dividing the clock from the oscillator and the phase of the 1S periodic frame pulse periodically generated by the clock converter in the second frequency divider. A phase synchronizer characterized by: And means for synchronizing a frequency and a phase of a reference clock received from the external device with a frequency and a phase of the 1S-period frame pulse generated by the clock conversion unit subsequent to the frequency synchronization circuit. The phase synchronizer according to claim 1. 3. The device according to claim 1, wherein
An S period frame pulse is input to a load signal of the counter of the second frequency divider, and a 16.384 MHz clock, which is a 16.384 MHz clock of the oscillator, is used as a clock for operating the counter. The phase synchronizer according to claim 2, wherein: 4. The phase synchronizer according to claim 3, further comprising means for outputting an output phase of the frequency-divided 8 KHz clock a predetermined time after a rising edge of the 1S-period frame pulse. 5. The phase comparator according to claim 2, further comprising a counter that counts from a rising edge of the frequency-divided 4 kHz clock to a rising edge of the frequency-divided 8 kHz clock. The phase synchronizer according to claim 1. 6. A control unit having means for performing frequency synchronization based on the phase difference count value and transmitting control data to a D / A conversion unit.
The phase synchronizer according to any one of claims 1 to 5. 7. The D / A converter according to claim 6, further comprising means for converting control data from the controller into an oscillator control voltage and controlling the oscillator. Phase synchronizer. 8. The clock conversion unit according to claim 16, wherein:
A function of generating a frame pulse having a cycle of 1 second from a 4 MHz clock, and having means for reloading its own counter in synchronization with the frame pulse of the 1S cycle and loading the counter into the second frequency divider. The phase synchronizer according to any one of claims 2 to 7, characterized in that: 9. When duplication is performed by using an active system and a protection system, means for transmitting and receiving the 1S periodic frame pulse between the working system and the protection system, and a stage preceding an input part of a load signal of the clock conversion unit. 9. The phase synchronization device according to claim 1, wherein a selector is provided in the controller, and a load signal is controlled by a select signal from the selector. 10. 10. An external reference 8KH received from an external device.
a step of generating and outputting a frequency-divided 4 KHz clock for dividing the frequency of the z clock to synchronize the frequency of the clock of the oscillator using the first frequency divider; and a frame pulse having a one-second cycle from the oscillator. 1S
A second frequency divider for generating and outputting a frequency-divided 8 kHz clock for frequency-synchronizing the clock of the oscillator by dividing the periodic frame pulse, and a phase comparator constituting a frequency synchronization circuit. A step of performing, in the second frequency divider, a phase of a clock obtained by dividing a clock from the oscillator for phase comparison and a phase of the 1S-period frame pulse periodically generated by a clock converter. A phase synchronization method comprising: 11. A method for synchronizing a frequency and a phase of a reference clock received from the external device and a frequency and a phase of the 1S-period frame pulse generated by the clock conversion unit subsequent to the frequency synchronization circuit. Claim 1
0, the phase synchronization method.