JPH11154940A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change over a clock supply path without causing a phase deviation on occurrence of a fault in a clock supply path incoming from a host device. SOLUTION: The synchronization is tracked by using a frame clock E8KCLK supplied from a host device as a reference clock in the case of synchronization switching. After the synchronization tracking, a bit clock E8MCLK supplied similarly from the host device is used for another reference clock to cope with external disturbance in a steady-state. A switching timing detection circuit 1, that switchovers the two reference clocks in a proper timing, produces a selection signal SEL to control changeover circuits A, B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for controlling the synchronization of transmission signals inside an electronic exchange or the like.

[0002]

2. Description of the Related Art In an electronic exchange or the like, clock signals and phases on a transmitting side and a receiving side must be completely synchronized in order to correctly transmit and receive signals between functional blocks. In order to achieve this object, the electronic exchange has a reference clock generator therein. The reference clock generated by the reference clock generator (hereinafter referred to as a higher-level device) is distributed to each functional block.

A signal transmitted inside the electronic exchange is constituted by, for example, dividing a bit signal having a frequency of 8 MHz by a frame signal having a frequency of 8 kHz. In order to control a signal having such a configuration, each functional block applies a PLL (Phase Locked) to a reference clock distributed from this higher-level device.
Loop) synchronizes the circuit to generate an internal clock of a specific frequency required by itself.

[0004]

However, the conventional clock generation circuit as described above has the following problems to be solved. It is assumed that a clock generation circuit (hereinafter referred to as a PLL circuit) of a certain functional block generates an internal clock in synchronization with a clock of 8 MHz corresponding to a bit clock supplied from a host device. It is assumed that an abnormality has occurred in the bit clock supply path. At this time, the clock generation circuit needs to resynchronize the PLL circuit with the bit clock supplied through another system. It takes a certain time to establish the synchronization of the PLL circuit. However, since this bit clock has a high frequency of 8 MHz, the clock cycle is shorter than the time required to establish synchronization of the PLL circuit. Therefore, the reference clock for phase comparison and the internal clock generated by the PLL circuit are likely to drop or overlap due to excessive response at the time of switching, noise, or the like.

In order to solve this problem, it is conceivable that the PLL circuit is synchronized with a frame clock whose clock cycle is longer than the time required for establishing synchronization. In this case, since the clock cycle is long, the above-described problem does not occur at the time of clock switching. But,
After the synchronization, when the clock frequency fluctuates due to some disturbance, the clock cycle is long, so that the following of the PLL circuit is delayed, and a phase shift occurs temporarily between bits in the frame, so that data cannot be transmitted and received normally.

[0006]

The present invention adopts the following constitution in order to solve the above points. <Structure 1> A phase locked loop circuit (hereinafter, referred to as a PLL circuit) that accepts a frame-structured transmission signal, a frame clock serving as a reference for frame synchronization of the transmission signal, and a bit clock serving as a reference for bit synchronization inside the frame And a switching circuit for supplying one of them to the PLL circuit, and the switching circuit first inputs the frame clock to the PLL circuit,
Upon detecting that the PLL circuit has generated an internal clock synchronized with the frame clock, switching timing detection for controlling switching of an input signal to the PLL circuit so that the switching circuit inputs the bit clock to the PLL circuit. A clock generation circuit comprising a circuit.

<Structure 2> In the clock generation circuit according to structure 2, the switching circuit operates so that the bit clock is input to the PLL circuit, and the PLL circuit generates an internal clock synchronized with the bit clock. When
The internal clock generated by the PLL circuit is monitored, and when the phase difference between the internal clock and the bit clock exceeds a predetermined value, the switching circuit inputs the frame clock to the PLL circuit so that the frame clock is input to the PLL circuit. A clock generation circuit, comprising: a switching timing detection circuit for controlling switching of the input signal.

<Structure 3> A PLL circuit that receives a reference clock and generates an internal clock having a frequency synchronized with the reference clock, and receives a plurality of reference clocks each having a different repetition frequency, and any one of the reference clocks And a switching circuit that supplies the reference circuit with the lowest repetition frequency to the PLL circuit, and the PLL circuit generates an internal clock synchronized with the reference clock. When the switching circuit detects that the switching signal has been supplied, the switching circuit controls switching of an input signal to the PLL circuit so that the switching circuit supplies a reference clock having a higher repetition frequency than the reference clock to the PLL circuit. Is supplied to the PLL circuit, and the PLL circuit synchronizes with the reference clock. The internal clock generated by the PLL circuit is monitored when the internal clock is generated to generate the internal clock, and when the phase difference between the internal clock and the reference clock exceeds a predetermined value, the switching circuit is activated. A clock generation circuit comprising: a switching timing detection circuit that controls switching of a signal supplied to a PLL circuit so that a reference clock having a low repetition frequency is supplied to the PLL circuit.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A clock generation circuit according to the present invention first causes a PLL circuit to synchronously follow a frame clock supplied from a higher-level device as a reference clock at the time of synchronization switching. After the synchronization follow-up, a bit clock, which is also supplied from a higher-level device, is switched to a reference clock to deal with a disturbance in a steady state. Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

<Structure of Specific Example> FIG. 1 is a block diagram of a specific example. As shown in the drawing, a PLL circuit according to a specific example includes a switching timing detection circuit 1, a switching circuit A, a switching circuit B, a phase comparison circuit 2, a low-pass filter (hereinafter referred to as LPF) 3, a voltage-controlled oscillator (hereinafter VC).
O) 4 and a counter 5.

The switching timing detecting circuit 1 includes a counter 5 for generating a frequency 8M generated based on the output of the VCO 4.
This section generates a selection signal (hereinafter, referred to as a SEL signal) for controlling clock switching timing from the internal clock I8MCLK of 8 Hz and the internal clock I8KCLK of 8 KHz. Further, the switching timing detection circuit 1 is a part for transferring the SEL signal to the switching circuit A and the switching circuit B. The switching circuit A uses the SEL signal transferred from the switching timing detection circuit 1 to generate a reference clock E8MCL having a frequency of 8 MHz.
This is a part that selects one of K and the reference clock E8KCLK of 8 KHz and supplies it to the phase comparison circuit 2.

The switching circuit B selects one of an internal clock I8MCLK having a frequency of 8 MHz and an internal clock I8KCLK having a frequency of 8 KHz based on the SEL signal transferred from the switching timing detection circuit 1 and supplies it to the phase comparison circuit 2. This is the part to do. The phase comparison circuit 2 receives the reference clock E8MCLK, the internal clock I8MCLK, or the reference clock E8KCLK supplied from the switching circuits A and B, respectively.
And a phase which compares the phase of the internal clock I8KCLK and supplies the difference to the LPF 3 as an UP pulse or a DOWN pulse.

The LPF 3 is a part for smoothing an UP pulse or a DOWN pulse supplied from the phase comparison circuit 2, converting the UP pulse or the DOWN pulse into a control voltage, and supplying the control voltage to the VCO 4. VCO4
Is a voltage controlled oscillator that oscillates and outputs an output VCOCLK near a specific frequency (here, for example, fixed to 16 MHz for convenience of explanation) by the control voltage output from the LPF 3. It is also a part for supplying the output to the counter 8. The counter 5 divides the output VCOCLK or
Multiplied by the internal clock I8MCLK and the internal clock I8
This is a part for generating KCLK.

<Operation of Specific Example> FIG. 2 is an explanatory diagram (part 1) of the operation. FIG. 9 is a diagram for explaining a process from a state where a reference clock is ahead of an internal clock to a time when synchronization is established. (A) shows an internal clock and a selection reference signal (SELD).
FIG. 3 is a waveform diagram of a signal). The upper part is an 8 MHz internal clock I8MCLK, and the middle part is an 8 KHz internal clock I8MCLK.
The lower part of KCLK represents a selection reference signal (SELD signal). 8MHz internal clock I8MCL
K and the 8 KHz internal clock I8KCLK are VC
This is a signal obtained by dividing the output of O4 (FIG. 1) by the counter 5.

The 8 KHz internal clock I8KCLK is
This is a pulse signal that goes low at the rising A1 of the internal clock I8MCLK of 8 MHz and goes high at the next rising A2. The SELD signal is a pulse signal used by the switching timing detection circuit 1 (FIG. 1) to detect that the phase difference between the reference clock and the internal clock falls within a certain range. 8KHz internal clock I8
± 30 ns around the rising edge E2 of KCLK
This is a pulse signal that goes high during ec. The rising edge C2 of the 8 KHz reference clock E8KCLK is
As shown in (c), this SELD signal is at H level, ± 30
When located between nSec, the switching circuit A
An 8 MHz reference clock E8MCLK is selected. Similarly, the switching circuit B has an internal clock I8M of 8 MHz.
Select CLK.

Conversely, when the rising edge C2 of the 8 KHz reference clock is at the H level as shown in FIG.
When it is not located between the levels, ± 30 nSec, the switching circuit A outputs the 8 KHz reference clock E8KCLK.
Select Similarly, the switching circuit B selects the internal clock I8KCLK of 8 kHz. Here, the H level of the SELD signal is fixed to ± 30 nSEC for convenience of description, but this value is a value determined by the characteristic specifications required for the electronic exchange.

FIG. 3B is a waveform diagram when the reference clock is advanced. The upper part shows the reference clock of 8 MHz, and the middle part shows the reference clock of 8 KHz.
As in (a), the 8 KHz reference clock is a pulse signal that goes low at the rising A1 of the 8 MHz reference clock and goes high at the next rising A2. The lower part shows the waveform of the UP pulse detected by the phase comparison circuit 2.

FIG. 3C is a waveform diagram when the reference clock and the internal clock are close to each other. 8KHz as in (a)
Is a pulse signal that goes low at the rising edge A1 of the 8 MHz reference clock E8MCLK and goes high at the next rising edge A2. The lower part shows the waveform of the UP pulse detected by the phase comparison circuit 2.

FIG. 3D is a waveform diagram showing the synchronization between the reference clock and the internal clock. The first stage represents the SEL signal, the second stage represents the internal comparison clock, and the third stage represents the reference comparison clock. It shows how the reference clock and the internal clock in the phase comparison circuit 2 (FIG. 1) reach the establishment of synchronization. The bottom row shows the waveform of the UP pulse detected by the phase comparison circuit 2. As described above, (a) to (d)
Represents the level magnitude on the vertical axis and the time on the horizontal axis.
1 and 2 (a) to 2 (d) show the operation of synchronous switching.
The operation steps will be described separately using FIG.

It is now assumed that some disturbance occurs in the reference clock supply system when the PLL circuit (FIG. 1) according to the specific example is generating the internal clock (a). By switching the clock changeover switch A (FIG. 1), the reference clock E8MCLK that has passed through another system
And E8KCLK are input to the PLL circuit (FIG. 1). At this time, it is assumed that the phase of the reference clock E8KCLK has advanced by t1Sec with respect to the phase of the internal clock I8KCLK as shown in FIG. At this time, since the rising edge C2 of the reference clock E8KCLK is not positioned between the SELD signal of H level and ± 30 nSec, the switching circuits A and B (FIG. 1) respectively operate the reference clock E8KCLK and the internal clock I8KCLK. Is selected.

S-1. The phase comparison circuit 2 (FIG. 1)
(A) The lower stage internal clock I8KCLK is compared with (b) the middle stage reference clock E8KCLK. The time difference t1
During the period (b), the lower-stage UP pulse is output to the LPF 3 (FIG. 1). LPF3 (FIG. 1) smoothes the UP pulse,
The voltage is converted into a control voltage and supplied to the VCO 4 (FIG. 1). S-
2. The VCO 4 (FIG. 1) to which the control voltage is applied increases the oscillation frequency according to the control voltage. VCO4 (Fig. 1)
Is fed back to the phase comparison circuit 2 (FIG. 1) through the counter 5 (FIG. 1) and the switching circuit B (FIG. 1). As a result, the timing correlation between (a) and (b) changes in the direction of arrow R1 ((b) moves as a whole in the direction of arrow R1), and finally becomes the correlation between (a) and (c). .
The time difference t1 between the internal clock I8KCLK in the lower stage (a) and the reference clock E8KCLK in the middle stage (c) gradually narrows. Eventually, t2Sec shown in (c) is reached.
(C) The UP pulse in the lower stage also becomes smaller, and the smoothed control voltage also becomes smaller. As a result, the speed at which the whole (b) moves in the direction of arrow R1 also decreases.

S-3. At time difference t2, reference clock E
The rising edge C2 of 8KCLK is, as shown in FIG.
It is assumed that the signal has entered between the H level of the SELD signal and ± 30 nSec. At this time, the switching timing detection circuit 1 (FIG. 1) switches the SEL signal to the H level (d). As a result, the switching circuits A and B (FIG. 1)
CLK and I8MCLK to select the phase comparison circuit 2
(FIG. 1). (D) shows a waveform that the phase comparison circuit 2 compares the phases. Until timing TC, the internal clock I8KCLK is compared with the reference clock E8KCLK.
8MCLK and the reference clock E8MCLK are compared.
(D) shows the situation.

S-4. After the timing TC, the phase comparison circuit 2 sets the internal clock I8MCLK and the reference clock E8
Compare MCLK. At the timing TC, the reference clock E8MCLK is ahead of the internal clock I8MCLK by t3Sec. During the time difference t3, an UP pulse is output to LPF3 (FIG. 1). LPF3 (Fig. 1)
Smoothes the UP pulse, converts it into a control voltage, and
O4 (FIG. 1).

S-5. The VCO 4 (FIG. 1) to which the UP pulse is smoothed and to which the control voltage is applied increases the oscillation frequency in accordance with the control voltage. The output of VCO4 (FIG. 1)
The signal is fed back to the phase comparison circuit 2 (FIG. 1) through the counter 5 (FIG. 1) and the switching circuit B (FIG. 1). Result (d)
The timing correlation between the internal clock I8MCLK in the upper stage and the reference clock E8MCLK in the lower stage changes in the direction of arrow R2 (the entire waveform of the third stage in (d) moves in the direction of arrow R2), and the time difference t3Sec is: The width gradually narrows and finally coincides at the timing TN.

Next, a case where the phase of the reference clock E8KCLK is delayed by t1Sec from the phase of the internal clock I8KCLK when the input switch (FIG. 1) is switched will be described. FIG. 3 is an operation explanatory view (2).
FIG. 7 is a diagram for explaining a process from a state where a reference clock is delayed from an internal clock to a time when synchronization is established.

FIG. 3A is a waveform diagram of an internal clock and a selection reference signal (SELD signal). The upper part is an internal clock I8MCLK of 8 MHz, the middle part is an internal clock I8KCLK of 8 kHz, and the lower part is a selection reference signal (SELD).
Signal). 8 MHz internal clock I8MCLK and 8 KHz internal clock I8KCL
K is a signal obtained by dividing the output of the VCO 4 (FIG. 1) by the counter 5.

The 8 KHz internal clock I8KCLK is
This is a pulse signal that goes low at the rising A1 of the internal clock I8MCLK of 8 MHz and goes high at the next rising A2. The SELD signal is a pulse signal used by the switching timing detection circuit 1 (FIG. 1) to detect that the phase difference between the reference clock and the internal clock falls within a certain range. 8KHz internal clock I8
± 30 ns around the rising edge E2 of KCLK
This is a pulse signal that goes high during ec. The rising edge C2 of the 8 KHz reference clock E8KCLK is
As shown in (c), this SELD signal is at H level, ± 30
When located between nSec, the switching circuit A
An 8 MHz reference clock E8MCLK is selected. Similarly, the switching circuit B has an internal clock I8M of 8 MHz.
Select CLK.

Conversely, when the rising edge C2 of the 8 KHz reference clock is at the H level as shown in FIG.
When it is not located between the levels, ± 30 nSec, the switching circuit A outputs the 8 KHz reference clock E8KCLK.
Select Similarly, the switching circuit B selects the internal clock I8KCLK of 8 kHz. Here, the H level of the SELD signal is fixed to ± 30 nSEC for convenience of description, but this value is a value determined by the characteristic specifications required for the electronic exchange.

FIG. 3B is a waveform diagram when the reference clock is delayed. The upper part shows the reference clock of 8 MHz, and the middle part shows the reference clock of 8 KHz.
As in (a), the 8 KHz reference clock is a pulse signal that goes low at the rising A1 of the 8 MHz reference clock and goes high at the next rising A2. The lower part shows the waveform of the DOWN pulse detected by the phase comparison circuit 2.

FIG. 3C is a waveform diagram when the reference clock and the internal clock are close to each other. 8KHz as in (a)
Is a pulse signal that goes low at the rising edge A1 of the 8 MHz reference clock E8MCLK and goes high at the next rising edge A2. The lower part shows the waveform of the DOWN pulse detected by the phase comparison circuit 2.

FIG. 3D is a waveform diagram showing the synchronization between the reference clock and the internal clock. The first row shows the SEL signal, the second row shows the internal comparison clock, and the third row shows the reference comparison clock. It shows how the reference clock and the internal clock in the phase comparison circuit 2 (FIG. 1) reach the establishment of synchronization. The bottom row shows the UP detected by the phase comparison circuit 2.
This shows a pulse waveform. As described above, (a) to (d)
The vertical axis represents the magnitude of the level, and the horizontal axis represents the time. The operation of the synchronous switching will be described below with reference to FIG. 1 and FIGS.

It is now assumed that some disturbance occurs in the reference clock supply system when the PLL circuit (FIG. 1) according to the specific example is generating the internal clock (a). By switching the clock changeover switch A (FIG. 1), the reference clock E8MCLK that has passed through another system
And E8KCLK are input to the PLL circuit (FIG. 1). At this point, it is assumed that the phase of the reference clock E8KCLK lags behind the phase of the internal clock I8KCLK by t1Sec as shown in FIG. At this time, since the rising edge C2 of the reference clock E8KCLK is not positioned between the SELD signal of H level and ± 30 nSec, the switching circuits A and B (FIG. 1) respectively operate the reference clock E8KCLK and the internal clock I8KCLK. Is selected.

S-1. The phase comparison circuit 2 (FIG. 1)
(A) The lower stage internal clock I8KCLK is compared with (b) the middle stage reference clock E8KCLK. The time difference t1
During the period (b), the DOWN pulse at the lower stage is output to the LPF 3 (FIG. 1). The LPF 3 (FIG. 1) smoothes the DOWN pulse, converts it into a control voltage, and supplies it to the VCO 4 (FIG. 1).

S-2. VCO4 with control voltage applied
(FIG. 1) lowers the oscillation frequency according to the control voltage. The output of VCO 4 (FIG. 1) is a counter 5 (FIG. 1),
The signal is fed back to the phase comparison circuit 2 (FIG. 1) through the switching circuit B (FIG. 1). As a result, the timing correlation between (a) and (b) changes in the direction of arrow L1 ((b) moves in the direction of arrow L1), and finally becomes the correlation between (a) and (c). . (A) Lower internal clock I8KCLK
And (c) the time difference t1 between the middle stage reference clock E8KCLK.
Narrows steadily. Finally, t2Se shown in (c)
c. (C) The DOWN pulse in the lower stage also becomes smaller,
The smoothed control voltage also decreases. As a result, the speed at which the whole (b) moves in the direction of arrow L1 also decreases.

S-3. At time difference t2, reference clock E
The rising edge C2 of 8KCLK is, as shown in FIG.
It is assumed that the signal has entered between the H level of the SELD signal and ± 30 nSec. At this time, the switching timing detection circuit 1 (FIG. 1) switches the SEL signal to the H level (d). As a result, the switching circuits A and B (FIG. 1)
CLK and I8MCLK to select the phase comparison circuit 2
(FIG. 1). (D) shows a waveform that the phase comparison circuit 2 compares the phases. Until timing TC, the internal clock I8KCLK is compared with the reference clock E8KCLK.
8MCLK and the reference clock E8MCLK are compared.
(D) shows the situation.

S-4. After the timing TC, the phase comparison circuit 2 sets the internal clock I8MCLK and the reference clock E8
Compare MCLK. At the timing TC, the reference clock E8MCLK is still behind the internal clock I8MCLK by t3Sec. DOW for the time difference t3
An N pulse is output to LPF3 (FIG. 1). The LPF 3 (FIG. 1) smoothes the DOWN pulse, converts it into a control voltage, and supplies it to the VCO 4 (FIG. 1).

S-5. VCO4 with control voltage applied
(FIG. 1) lowers the oscillation frequency according to the control voltage. The output of VCO 4 (FIG. 1) is a counter 5 (FIG. 1),
The signal is fed back to the phase comparison circuit 2 (FIG. 1) through the switching circuit B (FIG. 1). As a result, the timing correlation between the internal clock I8MCLK in the upper stage and the reference clock E8MCLK in the lower stage changes in the direction of the arrow L2 ((d)).
The entire third-stage waveform moves in the direction of the arrow L2), and the time difference t3Sec gradually narrows and finally coincides with the timing TN.

The above description has been limited to the operation up to synchronizing with the reference clock that has passed through another system by switching the clock changeover switch S (FIG. 1) when any disturbance occurs in the reference clock supply system. However, this operation is not limited to the operation only when switching synchronously to the reference clock that has passed through another system. The present invention can also be applied to a case where a clock loss or the like occurs temporarily due to some situation change in the same system. Assume that a clock drop has occurred. At this time, the reference clock E8
The rising edge C2 of KCLK deviates from the time when the SELD signal is at the H level and ± 30 nSec.

Therefore, the switching circuits A and B (FIG. 1)
Again, the reference clock E8KCLK and the internal clock I8KCLK are selected respectively. Hereinafter, S-1 to S-
5 or s-1 to s-5, the synchronization is established without switching the synchronization to another system.

The operation leading to the establishment of the synchronization is performed when the phase of the internal clock I8KCLK lags behind the phase of the reference clock E8KCLK as shown in FIG. 2B, and conversely, in FIG. The case where it is proceeding as shown is described separately. By applying these two operations not separately but alternately in one operation leading to synchronization establishment, more accurate synchronization establishment can be obtained.

Further, for convenience of explanation, the explanation has been made only for the electronic exchange, but the invention is not limited to this. For example, the present invention is suitable for an apparatus (for example, an electronic exchange) that requires double synchronization, such as a frame and bits constituting the frame.

Furthermore, for the sake of explanation, the description has been made only for double synchronization, but it is not necessary to limit to double synchronization. By configuring a plurality of reference clocks having different frequencies and a plurality of selection reference signals, it is possible to obtain a PLL circuit for multiplex synchronization, not limited to double. For example, when one frame is composed of a plurality of blocks, each of which is composed of several bits of data, first synchronize with a frame clock, then synchronize with a block clock, and further synchronize with a bit clock. Control such as synchronization can also be performed. If a specific example is double synchronous control, this example is triple synchronous control. The present invention can be applied to such a triple or more control.

[0043]

A plurality of reference clocks having different frequencies,
If a plurality of selection reference signals for controlling the clock switching timing are formed, the following effects can be obtained. 1. When an abnormality occurs in the clock supply path from the host device, the clock supply path can be switched without causing a phase shift of the frame phase. 2. In the case where the clock supplied from the higher-level device temporarily loses clock or the like, it is possible to re-establish synchronization without changing the clock supply path and without shifting the frame phase.

[Brief description of the drawings]

FIG. 1 is a block diagram of a specific example.

FIG. 2 is an operation explanatory diagram (1).

FIG. 3 is an operation explanatory view (2).

[Explanation of symbols]

 1 switching timing detection circuit 2 phase comparison circuit 3 low pass filter 4 voltage controlled oscillator 5 counter A, B switching circuit S clock switching switch

Claims (3)

[Claims] 1. A phase locked loop circuit (hereinafter, referred to as a PLL circuit) for receiving a transmission signal having a frame structure, a frame clock serving as a reference for frame synchronization of the transmission signal, and a bit serving as a reference for bit synchronization in a frame. Clock, and either one of them is
A switching circuit for supplying to the L circuit; first, when the switching circuit inputs the frame clock to the PLL circuit and detects that the PLL circuit has generated an internal clock synchronized with the frame clock, the switching circuit The bit clock to the PL
A clock generation circuit comprising: a switching timing detection circuit that controls switching of an input signal to a PLL circuit so as to input to an L circuit. 2. The clock generation circuit according to claim 2, wherein the switching circuit inputs a bit clock to the PLL circuit, and the PLL circuit operates to generate an internal clock synchronized with the bit clock. , The internal clock generated by the PLL circuit is monitored, and when the phase difference between the internal clock and the bit clock exceeds a predetermined value, the switching circuit switches the frame clock to the PLL.
A clock generation circuit, comprising: a switching timing detection circuit that controls switching of an input signal to a PLL circuit so as to input to a circuit. 3. A PL that receives a reference clock and generates an internal clock having a frequency synchronized with the reference clock.
An L circuit, a switching circuit that receives a plurality of reference clocks each having a different repetition frequency, selects one of the reference clocks, and supplies the selected reference clock to the PLL circuit. When the reference circuit supplies a reference clock to the PLL circuit and detects that the PLL circuit has generated an internal clock synchronized with the reference clock, the switching circuit outputs the reference clock having a higher repetition frequency than the reference clock to the PLL circuit.
The switching circuit controls the switching of the input signal to the PLL circuit so as to supply the L circuit, and the switching circuit supplies an arbitrary reference clock to the PLL circuit so that the PLL circuit generates an internal clock synchronized with the reference clock. When the internal clock generated by the PLL circuit is monitored and the phase difference between the internal clock and the reference clock exceeds a predetermined value,
A clock generation circuit, comprising: a switching timing detection circuit that controls switching of a signal supplied to a PLL circuit so that the switching circuit supplies a reference clock having a lower repetition frequency to the PLL circuit.