JPH114362A - Clock recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the circuit to provide a sampling clock with an optimum phase automatically by changing an oscillated frequency from a clock generating circuit based on a comparison result in a phase comparator means between a phase of an edge of an original video signal and a phase of a sampling clock so as to correct the phase of the original video signal. SOLUTION: The circuit is provided with an edge detection means 21 that detects an edge of an original video signal, a phase comparator means 22 that compares a phase of a detected signal with a phase of a sampling clock, and a clock generating circuit 3 and the oscillated frequency of the clock generating circuit is changed based on the comparison result at the phase comparator means 22. Through the constitution above, the phase comparator means 22 detects a phase difference between the signal detected by the edge detection means 21 and an output clock from the clock generating circuit 3 to produce a voltage in response to the phase difference and the voltage is fed to a control voltage terminal of a voltage controlled oscillator circuit 12 to match the phase of the clock with the edge of the original video signal thereby conducting sampling at an optimum position automatically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video device for A / D converting a video signal.

[0002]

2. Description of the Related Art Conventionally, a clock recovery circuit is disclosed in
What is described in No. 12616 is known.

FIG. 3 shows the configuration of a conventional clock recovery circuit. In FIG. 3, reference numeral 1 denotes an A / D conversion circuit, and 3 denotes a clock generation circuit. These components include a phase comparison circuit 10, an LPF 11, a voltage controlled oscillation circuit 12, and a frequency division circuit 13. 4 is an MPU, 5 is a non-volatile memory, and 6 is a pulse width measurement circuit.

The pulse width measurement circuit 6 measures the pulse width of the video original signal, the MPU 4 calculates the frequency dividing information N, and controls the frequency dividing circuit 13 so that the sampling clock having the optimum frequency for the video original signal can be obtained. Occur.

[0005]

In this clock recovery circuit, a clock is generated only by comparing the phase with the horizontal synchronizing signal. Therefore, the phase of the clock and the original video signal is not optimal, and the A / D is shifted due to a phase shift. There is a possibility that the conversion circuit 1 performs sampling at a position different from the original sampling position, and therefore, it is required to provide a means for adjusting the phase from outside.

[0006]

In order to solve this problem, the present invention comprises means for detecting an edge of an original video signal, means for comparing the phase of the detected signal with a sampling clock, and the clock generating circuit. The oscillation frequency of the clock circuit is changed according to the result of comparison by the phase comparison means. As a result, the phase of the clock is adjusted to the edge of the video original signal, and sampling can be automatically performed at the optimum position.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is characterized in that the oscillation frequency is changed by the phase difference between the edge of the video original signal and the sampling clock, and the phase of the clock is changed. This makes it possible to match the edge of the original video signal, and has an effect that sampling can be automatically performed at an optimum position.

According to a second aspect of the present invention, there is provided a means for detecting an edge of a video original signal, a means for comparing the phase of the detected signal with a sampling clock, and a clock generating circuit for generating a sampling clock from a synchronization signal. The oscillation frequency of the clock circuit is changed according to the result of the comparison by the phase comparison means. The phase of the clock is adjusted to the edge of the original video signal, and sampling at the optimum position can be performed automatically. Has an action.

The invention according to claim 3 is characterized in that the edge detecting means is provided independently for each of a plurality of video original signal components, and performs a phase comparison from a detection signal obtained by calculating a logical sum of these components. By detecting the edge of each component of the original video signal, it is possible to perform an edge detection more effective than the second aspect of the present invention.

Embodiment 1 Hereinafter, a clock recovery circuit according to Embodiment 1 of the present invention will be described with reference to FIG.

FIG. 1 shows a main block configuration diagram of the clock recovery circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a means for detecting an edge of a video original signal;
Reference numeral 2 denotes a phase comparison unit between the edge detection signal and the sampling clock.

According to this configuration, the phase difference between the signal detected by the edge detecting means 21 and the output clock of the clock generating circuit 3 is detected by the phase comparing means 22 to generate a voltage corresponding to the phase difference. Is added to the control voltage in the voltage controlled oscillation circuit 12, the phase of the clock is adjusted to the edge of the original video signal, and sampling at the optimum position can be automatically performed.

(Embodiment 2) Next, a clock recovery circuit according to Embodiment 2 of the present invention will be described with reference to FIG.

FIG. 2 shows a main block diagram of a clock recovery circuit according to a second embodiment of the present invention. Edge detecting means 21 is provided independently for each of R, G, and B components of an original video signal. In this configuration, a logical sum of the output of the detection means is input to the phase comparison circuit 22.

According to this configuration, the logical sum of each signal detected by the edge detection means 21 provided independently for each of the R, G, and B components and the position of the output clock of the clock generation circuit 3 The phase difference is detected by the phase comparing means 22 and a voltage corresponding to the phase difference is generated.
2, the phase of the clock is adjusted to one of the edges of each of the R, G, and B components of the video original signal, and sampling can be automatically performed at an optimum position.

[0016]

As described above, according to the present invention, the oscillating frequency of the clock generation circuit is changed based on the result of comparison between the edge of the video original signal and the sampling clock by the phase comparison means, thereby correcting the phase of the video original signal. And the advantageous effect that the sampling clock with the optimal phase is automatically output is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a clock recovery circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a conventional clock recovery circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Phase comparison circuit 11 LPF 12 Voltage control oscillation circuit 13 Frequency divider circuit 21 Edge detection means 22 Phase comparison means

Claims (3)

[Claims] 1. A clock recovery circuit configured to change an oscillation frequency of a clock generation circuit according to a phase difference between an edge of a video original signal and a sampling clock. 2. A means for detecting an edge of an original video signal,
A clock recovery circuit comprising: a phase comparison means for detecting the detection signal and the sampling clock; and a clock generation circuit for generating a sampling clock from the synchronizing signal, wherein the oscillation frequency of the clock circuit is changed based on a result of the comparison by the phase comparison means. circuit. 3. The clock according to claim 2, wherein said edge detecting means is provided independently for each of a plurality of video original signal components, and performs a phase comparison based on a detection signal obtained by taking a logical sum of these components. Regeneration circuit.