JPH1127247A - System switching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a clock and a frame pulse without being affected by phase shift when an active system and a stand-by system are switched by outputting a high frequency clock and a third frame pulse. SOLUTION: An output clock CLK2 of a frequency divider 32 of a PLO part 30 and a frame pulse FP2 generated in a FP generation part 50 are outputted in a clock switching circuit 2. Similarly, an output clock CLK2' of a frequency divider 32' of a PLO part 30' and a frame pulse FP2' generated in an FP generation part 50' are outputted in a clock switching circuit 2'. These outputs of the clock switching circuits 2, 2' are inputted in lower order devices 3, 3' respectively and switching of input from each of the clock switching circuits 2, 2' to each of the lower order devices 3, 3' is controlled based on control from phase monitoring parts 60, 60'. The phase monitoring devices 60, 60' are linked together and controlled so that the input is not switched by the lower order devices 3, 3' until pull-in of the PLO parts 30, 30' are completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used, for example, in a pulse communication system and includes two systems, an active system and a standby system.
The present invention relates to a system switching method for switching these systems.

[0002]

2. Description of the Related Art As this type of system switching system, there is a clock switching system for selectively switching between two output clocks as disclosed in, for example, JP-A-4-316234. FIG. 3 shows the configuration of the clock switching system.

The clock switching system includes clock generation circuits 101 and 102 having the same oscillation frequency, a phase difference detection circuit 106 for detecting a phase difference between respective clocks from the clock generation circuits 101 and 102, and a phase difference detection circuit 106. Delay circuit 1 for delaying the output of clock generation circuit 1 in the range of 0 to 2π radians in accordance with the phase difference voltage from circuit 106
07, a clock switching circuit 103 for selectively selecting and outputting the clock from the delay circuit 107 and the clock from the clock generation circuit 2, and a frequency division for dividing the clock switched and selected by the clock switching circuit 103 by 1 / N. And a vessel 104.

The clock generation circuits 101 and 102 constitute a redundant system, one of which is a working system and the other is a standby system. Clocks as shown in FIGS. 4A and 4B are output from these circuits. Clock generation circuits 101 and 10
2 is detected by a phase difference detection circuit 106. The phase difference detection circuit 106 detects a phase difference between the clock output from the clock generation circuit 101 and the delay circuit 107 based on the voltage of the phase difference. And a clock as shown in FIG. 4C is output. Due to the delay by the delay circuit 107, the phase difference between the clocks output from the respective clock generation circuits 101 is minimized.

Each clock whose phase difference has been reduced as described above is selectively switched and output by the clock switching circuit 103 (clock switching between the working system and the standby system is performed), and
A clock as shown in FIG. 4D is output. The switched clock is further frequency-divided by 1 / N by the 1 / N frequency divider 104 to become a clock as shown in FIG. By dividing the frequency by 1 / N, the phase difference between the clocks before and after the switching is further reduced to 1 / N.

[0006] According to the clock switching system configured as described above, phase fluctuations caused by switching of the clock generation circuit are minimized, and data loss or duplication occurs when a digital signal is processed on the basis of a clock. Can be reduced.

[0007] In addition to the clock switching method described above,
Japanese Patent Application Publication No. 6768 discloses a method including a circuit for monitoring whether the phases of a working clock and a standby clock are synchronized. In this clock switching method, there are provided two delay circuits for delaying the output of two clocks (ACT and SBY) for a certain period of time, and furthermore, a rising position detecting circuit for detecting the rising positions of the two clocks, The phase synchronization monitoring unit includes a comparison circuit that outputs a pulse only when the rising position detected by the circuit matches, and an output pulse detection circuit that detects an output pulse of the comparison circuit. . In the clock switching method, when synchronization is not achieved due to a defect in the phase synchronization circuit, the phase synchronization monitoring unit controls the clock switching so as not to perform the clock switching.

[0008]

However, each of the above-mentioned conventional clock switching systems has the following problems.

JP-A-4-316234 and JP-A-5-1367
In the switching method described in Japanese Patent Publication No. 68, the phase adjustment of the clock and the frame pulse between the active system and the standby system is performed using a delay circuit. In the system switching method using such a delay circuit, since the MAX value of the phase shift is limited by the maximum delay amount of the delay circuit, it is possible to cope with a phase shift exceeding the maximum delay amount set in the delay circuit. I ca n’t,
It lacked scalability.

Further, when phase matching is performed using a delay circuit, it is not possible to completely eliminate the phase shift. For example, in the method described in Japanese Patent Application Laid-Open No. 5-136768, switching from the working system to the standby system is required. In the case where the switching is performed alternately with reference to one of the clocks, the phase adjustment by the delay circuit is gradually shifted in one direction (direction in which the phase is advanced or delayed) by the amount of the phase shift each time the system is switched. As a result, it is conceivable that the function does not operate normally because the range of adjustment by the delay circuit is exceeded.

An object of the present invention is to generate a clock and a frame pulse which are not affected by the phase shift even if a phase shift occurs when switching between the active system and the standby system without using a delay circuit. An object of the present invention is to provide a reliable system switching method that can be performed.

[0012]

In order to achieve the above object, a system switching system according to the present invention has two inputs, a working clock supply system and a backup clock supply system, and selectively supplies clocks from these systems. In a system switching system having clock switching means for switching, the clock switching means selects and outputs a clock and a frame pulse supplied from the working clock supply system and a clock and a frame pulse supplied from the backup clock supply system. Means, a voltage controlled oscillator for controlling the frequency of the output clock in accordance with the input control voltage, a first frequency divider for dividing the output of the voltage controlled oscillator and outputting a high frequency clock,
A second frequency divider for dividing the output clock of the first frequency divider to output a low-frequency clock; an output clock of the second frequency divider; and a clock selected by the selection means. And a phase comparison unit that obtains a control voltage for controlling the voltage-controlled oscillator from the comparison result, and a low-frequency clock output from the second frequency divider. Using a first frame pulse generating means for generating a second frame pulse synchronized with the selected frame pulse and a high frequency clock output from the first frequency divider, A second frame pulse generating means for generating a third frame pulse synchronized with the pulse, and a clock output from the first frequency divider and a second frame pulse generated by the second frame pulse generating means. Tafure Characterized by an output Muparusu.

In the above system switching method, the clock switching means monitors a result of the phase comparison by the phase comparing means, and determines whether a clock selected by the selecting means and an output clock of the second frequency divider are output. It may further include a phase monitoring unit that inhibits reading of data based on the clock and the frame pulse output from the clock switching unit to the lower-level device until complete synchronization.

Further, the clock switching means may have a redundant configuration including an active system and a standby system.

Further, the clock switching means has a redundant configuration comprising a working system and a protection system, and the phase monitoring means of each of the working and protection system clock switching means are linked to each other and selected by respective selection means. Until the output clock of the second frequency divider and the output clock of the second frequency divider are completely synchronized, the switching of the input from the working clock switching means and the input from the protection clock switching means to the lower-level device is prohibited. May be configured.

Further, the phase comparing means is configured to obtain a control voltage such that the phase difference between the output clock of the second frequency divider and the clock selected by the selecting means is 180 degrees. Is also good.

(Operation) In the present invention as described above, the reference clock selected by the selection means (the clock supplied from the working clock supply system or the spare clock supply system) and the first frequency divider The synchronization with the output clock (output clock of the clock switching means) is performed by synchronizing the low frequency clock (output clock of the second frequency divider) obtained by dividing the output clock of the first frequency divider with the reference clock. It is done by taking. In this way, by temporarily varying the frequency using a low-frequency clock, the phase with the reference clock is synchronized, so that when the reference clock is switched, a phase jump occurs. Also, phase adjustment can be performed without changing the number of peaks of the output clock of the first frequency divider.

The generation of the frame pulse synchronized with the reference frame pulse (the frame pulse supplied from the current clock supply system or the backup clock supply system) selected by the selection means is performed by first using the first frequency divider. After adjusting the phase using a low-frequency clock (output clock of the second frequency divider) obtained by further dividing the output clock of the second frequency divider, a frame pulse is generated using the high-frequency output clock of the first frequency divider. Since the phase shift is performed by generating, even if a phase shift of several clocks occurs in the high frequency output clock of the first frequency divider, the phase shift is compressed when the frequency is divided by the second frequency divider. Therefore, the frame pulse is not affected by the phase shift.

In the case where the clock switching means has a redundant configuration consisting of the working system and the standby system, the clock switching means of the standby system can be used even if one of the clock switching units becomes unusable for some reason. It will be more reliable. Further, in the case where the phase monitoring units are linked to each other, until the synchronization with the reference clock in each of the clock switching units of the working system and the standby system is completely achieved.
Since the switching of the input from the working system clock switching means and the input from the standby system clock switching means to the lower-level device is prohibited, the lower-level device reads data based on the unsynchronized clock and frame pulse. Never do.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the system switching system of the present invention. The system switching method of the present embodiment includes, for example, an active system and a standby system (hereinafter referred to as ACT system and SB system, respectively).
Described as Y system. ), And clock switching circuits 2 and 2 ′ for switching the system between an ACT system (active system) and an SBY system (standby system). The clock switching circuits 2 and 2 'have a redundant configuration. In this embodiment, the clock switching circuit 2 is used as a working system and the clock switching circuit 2' is used as a standby system.

The clock switching circuit 2 includes a clock CLK1 and a frame pulse FP1 outputted from the clock supply system 1 which is an ACT system and a clock CLK1 'and a frame pulse FP1' outputted from the clock supply system 1 'which is an SBY system. Selector 20 for selectively outputting
The clock selected by the selector 20 is used as an input,
PLO (Phase Locked O) that oscillates in synchronization with the input signal
A scillator) unit 30 synchronizes the frame pulse FP selected by the selector 20 with the clock oscillated by the PLO unit 30 and performs head alignment (a special code (synchronization code added before the information sequence) for synchronization. Pattern matching) between the input FP and the output FP) and the PLO.
Until the retraction in the unit 30 is completed,
3 ′ is provided with a phase monitoring unit 60 that inhibits switching between the active system and the standby system in 3 ′. Since the spare clock switching circuit 2 'has the same configuration as the clock switching circuit 2, the configuration of the clock switching circuit 2 will be specifically described here.

The selector 20 has a clock supply system 1, 1 '
The clock is selected based on the ACT signal and the ACT 'signal output from the CPU. When the ACT signal is input, the clock CLK1 and the frame pulse FP1 are selected, and when the ACT' signal is input. Select the clock CLK1 'and the frame pulse FP1'.

The PLO unit 30 is a voltage controlled oscillator (VCO)
31 and the output of the voltage controlled oscillator (VCO) 31
A frequency divider 32 for dividing the frequency by N and outputting a clock CLK2;
A frequency divider 33 for dividing the output clock CLK2 of the frequency divider 32 by 1 / N and outputting a clock CLK3;
3, a phase comparator 34 for comparing the phase of the output clock CLK3 with the clock selected by the selector 20, an output (phase information) of the phase comparator 34, and a control voltage based on the input phase information. And a low-pass filter (LPF) 35 for outputting to the voltage-controlled oscillator 31. In the PLO unit 30, the voltage controlled oscillator 31 is controlled such that the phase difference between the clock CLK1 and the clock CLK3 becomes 180 degrees.

The FP phase matching section 40 receives the output clock CLK3 of the frequency divider 33 and the frame pulse FP selected by the selector 20, and uses the clock CLK3 to synchronize the frame pulse FP with the frame pulse FP.
3 is generated. The FP generation unit 50 includes the FP phase matching unit 4
0 generated frame pulse FP3 and frequency divider 3
2 output clock CLK2 as an input and the clock CLK
2 to generate a frame pulse FP2 synchronized with the frame pulse FP3.

The phase monitoring unit 60 monitors the completion of the pull-in operation of the PLO unit 30 based on the result of the phase comparison between the clock CLK3 in the phase comparison unit 34 and the clock selected by the selector 20. The reading of data based on the clock and the frame pulse output from the clock switching circuit 2 is prohibited for the lower order devices 3 and 3 '.

The clock switching circuit 2 outputs the output clock CLK2 of the frequency divider 32 of the PLO unit 30 and the frame pulse FP2 generated by the FP generation unit 50. Similarly, in the clock switching circuit 2 ′, the PLO unit 3
The output clock CLK2 'of the frequency divider 32' of 0 'and the frame pulse FP2' generated by the FP generator 50 'are output. The outputs (clock and frame pulse) of these clock switching circuits 2 and 2 'are input to the lower devices 3 and 3', respectively, and the lower devices 3 and 3 'control the phase monitoring units 60 and 60'. The switching of the input from each of the clock switching circuits 2 and 2 'is controlled based on this. In the present embodiment, the phase monitoring units 60 and 60 'are linked, and control is performed so that the lower-level devices 3 and 3' do not perform input switching until the pull-in of the PLO units 30 and 30 'is completed.

Next, a specific operation of the system switching method will be described with reference to FIG. FIG. 2 is an operation time chart of the system switching system shown in FIG. 1, in which the clock CLK1 'and the frame pulse FP1 are supplied with the clock CLK1'.
Also, a state of synchronization at the time of system switching when the frame pulse FP1 'is delayed by about two clocks of the clock CLK2 is shown.

When the working system is used (the ACT signal is being output from the clock supply system 1 to each of the clock switching circuits 2 and 2 '), the clock supply system 1' and the clock switching circuits 2 and 2 are used. When the ACT signal is output to the clock switching circuits 2, 2 ', the selector 20,
20 'is a clock CLK1', a frame pulse FP1 '
Is selected and output. At this time, the clock CLK1 'and the frame pulse FP1' are changed to the clock CL1 as shown in FIG.
K1, clock CLK2 for frame pulse FP1
Is delayed by about two clocks, and a phase jump occurs.

In each of the clock switching circuits 2, 2 ', when the clock CLK1' and the frame pulse FP1 'are selectively output from the selectors 20, 20', the PLO units 30, 3 are output.
At 0 ', the clock CLK is based on the clock CLK1'.
3 and CLK3 ', and at the same time, FP
The clocks CLK3,
Frame pulses FP3 and FP3 'are generated using CLK3'. For example, the clock CLK
When synchronizing the phases of 1 'and the clock CLK3, as shown in FIG. 2, the phase of the clock CLK3 gradually shifts to synchronize with the phase of the clock CLK1', and the phase of the frame pulse FP3 also gradually shifts. Clock CLK3
(The clock CLK3 'and the frame pulse FP3' are also the same). This clock CLK3, CL
Frame pulse FP3, FP generated using K3 '
3 ′ is generated regardless of the phase jump. When the phases of the frame pulses FP3 and FP3 'gradually shift, the phases of the frame pulses FP2 and FP2' also gradually shift in accordance with the phase shift, and the clocks CLK3 and CLK3 ', respectively.
Synchronize with the phase of

As described above, each clock switching circuit 2, 2 '
In the above, when the clock is switched, the clock CLK obtained by dividing the output of the voltage controlled oscillators 31 and 31 'is used.
2, a low-frequency clock C obtained by further dividing CLK2 '
LK3, CLK3 'and clock CLK1' are phase-matched. In this case, even if there is a phase shift between the clock CLK1 and the clock CLK1 ′, the phase shift is compressed in the low-frequency clocks CLK3 and CLK3 ′, so that the clock peaks in the high-frequency clocks CLK2 and CLK2 ′. Does not fluctuate. Therefore, in this embodiment, even if a phase jump occurs due to clock switching, it is possible to generate a clock CLK that is not affected by the phase jump.

In this embodiment, first, the frame pulse FP is generated by using low-frequency clocks CLK3 and CLK3 '.
After generating the frame pulses FP3 and FP3 'synchronized with 1', the frame pulses FP2 and FP2 'synchronized with the frame pulses FP3 and FP3' are generated using the high-frequency clocks CLK2 and CLK2 '. The phase shift at the time of switching does not affect the generated frame pulses FP2 and FP2 '. Therefore, even if a phase change occurs at the time of clock switching, the clock C within one cycle of the frame pulses FP2 and FP2 '
No change occurs in the number of pulses of LK2, 2 '.

In the present embodiment, the clock switching circuits 2 and
2 'has a redundant configuration. For example, when the clock switching circuit 2 cannot be used for some reason, the system switching can be performed using the clock switching circuit 2'. In this case, the phase monitoring units 60 and 60 '
Since the lower devices 3, 3 'are controlled so as not to perform the switching operation to the standby clock switching circuit 2' until the pull-in of 0, 30 'is completely completed, the PLO unit 3
Before the 0, 30 'is completely retracted, the lower level device 3,
3 ′ does not perform input switching (input switching from the clock switching circuit 2 to the clock switching circuit 2 ′).

(Other Embodiments) In the above embodiment,
Although the clock switching circuit has a redundant configuration, the number of clock switching circuits may be one. For example, the configuration shown in FIG. 1 may include only the clock switching circuit 1. In this case, as an operation of the phase monitoring unit 60, reading of data based on the clock and the frame pulse output from the clock switching circuit 2 is prohibited for the lower order devices 3, 3 'until the pull-in in the PLO unit 30 is completed. You just have to.

Also in the present embodiment, it is possible to generate a clock CLK that is not affected by a phase jump caused by clock switching. Further, even if a phase change occurs during clock switching, the number of pulses of the clock CLK2 within one cycle of the frame pulse FP2 does not change.

[0036]

According to the present invention configured as described above, even if a phase shift occurs when switching from the current clock supply system to the spare clock supply system, a clock and a clock that are not affected by the phase shift are provided. Since a frame pulse can be generated, a highly reliable system switching method can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a system switching system according to the present invention.

FIG. 2 is an operation time chart of the system switching method shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional system switching method disclosed in Japanese Patent Application Laid-Open No. 4-316234.

4 is an operation time chart in the system switching method shown in FIG.

[Explanation of symbols]

 1, 1 'Clock supply system 2, 2' Clock switching circuit 3, 3 'Lower device 20, 20' Selector 30, 30 'PLO unit 31, 31' Voltage controlled oscillator 32, 32 ', 33, 33' Divider 34, 34 'phase comparison unit 35, 35' low-pass filter (LFP) 40, 40 'FP phase matching unit 50, 50' FP generator 60, 60 'phase monitoring unit

Claims (5)

[Claims] 1. A system switching system having two systems, an active clock supply system and a standby clock supply system, and having a clock switching means for selectively switching clock supply from these systems, wherein the clock switching means comprises: Selection means for selecting and outputting a clock and a frame pulse supplied from a clock supply system and a clock and a frame pulse supplied from the spare clock supply system; and a voltage controlled oscillator for controlling a frequency of an output clock in accordance with an input control voltage. A first frequency divider for dividing the output of the voltage controlled oscillator to output a high frequency clock; and dividing the output clock of the first frequency divider to output a low frequency clock. Comparing the phase of the output clock of the second frequency divider with the phase of the clock selected by the selection means; And a phase comparison unit for obtaining a control voltage for controlling the voltage-controlled oscillator from the result, and using a low-frequency clock output from the second frequency divider, synchronized with the frame pulse selected by the selection unit. A first frame pulse generating means for generating a second frame pulse, and a third frame pulse synchronized with the second frame pulse using a high frequency clock output from the first frequency divider And a frame pulse generated by the second frame pulse generating unit, and a clock output from the first frequency divider and a frame pulse generated by the second frame pulse generating unit. Characteristic system switching method. 2. The system switching system according to claim 1, wherein the clock switching unit monitors a result of the phase comparison by the phase comparing unit, and the clock selected by the selecting unit and the second frequency division. Further comprising phase monitoring means for prohibiting a lower-level device from reading data based on the clock and frame pulse output from the clock switching means until the output clock of the device is completely synchronized. method. 3. The system switching system according to claim 1, wherein said clock switching means has a redundant configuration including a working system and a standby system. 4. The system switching system according to claim 2, wherein the clock switching means has a redundant configuration including a working system and a protection system, and the phase monitoring means of each of the clock switching means of the working system and the protection system are mutually connected. Until the clock selected by the selection means and the output clock of the second frequency divider are completely synchronized, the input from the working clock switching means and the protection system clock to the lower-level device. A system switching method characterized in that switching of an input from a switching unit is prohibited. 5. The system switching method according to claim 1, wherein said phase comparing means determines that a phase difference between an output clock of said second frequency divider and a clock selected by said selecting means is one.
A system switching method characterized in that a control voltage of 80 degrees is obtained.