WO2003049356A1

WO2003049356A1 - Clock switching circuit and node device

Info

Publication number: WO2003049356A1
Application number: PCT/JP2001/010513
Authority: WO
Inventors: Nobuyuki Umeda; Akihiro Hata; Hiroyuki Sato; Hideo Tsuji; Satoshi Sumino
Original assignee: Fujitsu Limited
Priority date: 2001-11-30
Filing date: 2001-11-30
Publication date: 2003-06-12

Abstract

A clock switching circuit which is fed with clock signals corresponding to respective elements of a redundant system and outputs a clock signal corresponding to the system in operation while relaxing the phase fluctuation in response to a change in the system construction and a node device which is provided with the clock switching circuit. Useless accumulation of phase error is prevented with neither a drastic change in the construction nor a degradation of performance. Therefore, the clock switching circuit is constructed such that the phase of a synchronous clock signal synchronized with a clock signal corresponding to an element used antecedently is stepwise varied alternately in opposite directions each time the element being used is updated.

Description

Description Clock switching circuit and node device

According to the present invention, a clock signal corresponding to a plurality of elements constituting a redundant system is provided, and a clock signal corresponding to an active system is output while alleviating a phase change according to a change in the system configuration of the system. The present invention relates to a clock switching circuit and a node device provided with the clock switching circuit. Skill

In recent years, many private networks as well as public networks have been redundantly configured to achieve and maintain high quality of service and reliability, and network synchronization has been established based on highly advanced transmission and digital control technologies. It is planned.

FIG. 7 is a diagram illustrating a configuration example of a clock switching circuit provided in a node device of a redundantly configured network.

In the figure, a clock signal (hereinafter referred to as “clock signal 0”) is supplied to one input of a selector 60 p and a synchronous oscillator 61 via a transmission line 62-0. The other input of the selector 6 Op and the other input of the synchronous oscillator 61 are connected to a clock signal (hereinafter referred to as a “clock”) via a transmission line 62-0 that forms a duplex network with the transmission line 62-0 described above. Signal 1 ") is given. The output of the selector 6 Op is connected to the selector 60 s and one input of the phase comparator 63, and the output of the synchronous oscillator 61 is connected to the selector 60 s and the other input of the phase comparator 63. Connected to. The output of the phase comparator 63 is connected to one control input of the selector 60 s and the input of the phase controller 64, and the output of the phase controller 64 is connected to one control input of the synchronous oscillator 61. Is done. The output of the selector 60 s is connected to the input of the phase locked oscillator 65, and a “reference clock signal” is obtained at the output of the phase locked oscillator 65. The control input of the selector 60 p, the other control input of the selector 60 s, the other control input of the synchronous oscillator 61, and the control input of the phase comparator 63 are connected to a system component (not shown). The generated system configuration information is provided.

In the clock switching circuit having such a configuration, the transmission path (indicated by one of “6 2 -0” and “6 2 -1”) that is indicated by the system configuration information described above and that is to be used for the current operation In the following, for the sake of simplicity, when the “working transmission path” is updated, the selector 60 p will select the “working transmission path” of the clock signal 0 and the clock signal 1 described above. Select one of the clock signals given via In the following, the clock signal selected by the selector 60p in this manner is simply referred to as “provisional clock signal”.

Further, the synchronous oscillator 61 identifies “the time when the“ working transmission line ”is updated” (hereinafter, referred to as “system configuration time”) based on the system configuration information described above. However, at the time of the system configuration, the synchronous oscillator 61 synchronizes with the transmission line previously selected as the “working transmission line” (hereinafter referred to as “preceding working transmission line”), and has the clock signal 0 ( The clock signal whose frequency is the same as that of the clock signal 1) (hereinafter referred to as “synchronous clock signal”) is continuously generated.

For the sake of simplicity, the synchronous oscillator 61 will be described below as a variable divider that divides the clock in synchronization with the clock signal 0 (or clock signal 1) corresponding to the “preceding active transmission line” (see FIG. It is assumed that the above-mentioned “synchronous clock signal” is generated according to a predetermined frequency division ratio set in the variable frequency divider.

The selector 60 s selects the above-mentioned “synchronous clock signal” after the system configuration time (FIG. 8 (1)).

After the system configuration time, the phase comparison unit 63 measures, at a predetermined frequency, the phase difference (hereinafter, simply referred to as “phase difference”) between the “temporary clock signal” and the “synchronous clock signal” described above. I do.

The phase control unit 64 sends a command to the synchronous oscillator 61 indicating that the phase of the “synchronous clock signal” should be advanced (or delayed) as long as the phase difference exceeds a predetermined threshold. Give intermittently at a predetermined frequency.

The synchronous oscillator 61 advances (or delays) the phase of the “synchronous clock signal” as appropriate by intermittently setting the division ratio to a small (or large) value in response to this command. . Therefore, the phase difference measured by the phase comparison unit 63 decreases stepwise (FIG. 8 (2)).

The selector 60 s compares the phase difference with a predetermined threshold value, and after the time when the former falls below the latter (FIG. 8 (3)), replaces the “temporary clock signal” with the “synchronous clock signal”. Select ".

The phase locked oscillator 65 generates a “reference clock signal” having a desired frequency in synchronization with the “synchronous clock signal” or the “temporary clock signal” selected by the selector 60 s in this way.

In other words, even if the working transmission line is updated in a state where the phases of the clock signal 0 and the clock signal 1 are significantly different, the phase-locked oscillator 65 will output the “synchronous clock signal” and the “temporary clock”. The "temporary clock signal" is given after the phase difference with the "signal" is compressed stepwise.

As described above, in the above-described conventional example, the frequency of the clock signal input to the phase-locked oscillator 65 is stably maintained without excessively jumping the phase of the clock signal. At the output, a signal synchronized with the duplexed network and having the desired frequency can be obtained with high accuracy.

By the way, in such a conventional example, the frequency division ratio set in the variable frequency divider provided in the synchronous oscillator 61 is one of an intermittently large value and a small value in accordance with the above-mentioned command. Was set to the value of

Therefore, the phase of the “synchronous clock signal” advances (or delays) each time the “working transmission line” is updated, and in particular, the synchronous transfer mode is applied to the transmission lines 6 2 -0 and 6 2 -1. In this case, the more frequently the “working transmission line” is updated, the more unnecessary the slip occurs or the faster the transmission delay time increases, so the transmission quality and service quality may decrease. The nature was high. Disclosure of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock switching circuit and a node device that can avoid unnecessary accumulation of phase errors that occur when updating a system configuration without causing a significant change in the configuration and a decrease in performance. is there. Another object of the present invention is to prevent an excessive error in the phase of the output clock signal.

Further, an object of the present invention is to maintain a small error in the phase of a clock signal to be output, to have high responsiveness and high performance of a device or system that synchronizes with the clock signal or performs a predetermined process, And is maintained stably.

Also, an object of the present invention is to maintain the error occurring in the phase of the output clock signal at a small value with high accuracy, and to improve the responsiveness and performance of devices and systems that synchronize with the clock signal or perform predetermined processing. It is still higher and more stable. Further, an object of the present invention is to simplify the processing for determining the direction in which the phase of the synchronous clock is to be varied, and to stably maintain a suitable response to the system configuration.

Also, an object of the present invention is to change the phase of the clock signal until the period in which the phase of the synchronous clock signal should be changed first after the current element is updated based on the system configuration. Responsiveness is higher than when the direction is not changed.

A further object of the present invention is to enable flexible application to various devices and systems.

Further, an object of the present invention is to prevent the occurrence of slips due to the phase of the clock signal continuing to be varied only in a specific direction and the unnecessary integration of transmission delay times, thereby improving service quality and transmission quality. The point is that it is kept stable.

The above-described object is that each time the working element is updated, the phase of the synchronization clock signal synchronized with the clock signal corresponding to the element previously used in the work is alternately changed stepwise in the opposite direction. This is achieved by a clock switching circuit characterized in that

In such a clock switching circuit, the phase of the synchronous clock is prevented from being continuously varied in a specific direction.

Further, the above-mentioned object corresponds to a phase difference between a clock signal selected by the first selecting means and a synchronous clock signal generated by the clock reproducing means, and an element previously used for the current operation. Synchronous clock signal phase synchronized to clock Is achieved by the clock switching circuit characterized in that the phase of the synchronous clock signal is stepwise varied over the phase shift amount in which the sum of the phase shift amounts that have been varied as a result decreases. You.

In such a clock switching circuit, the phase of the synchronous clock is appropriately changed in such a direction that the integrated value of the phase shift amount actually changed before the phase does not increase. Further, the above-mentioned object is achieved by a clock switching circuit characterized in that the phase of a synchronous clock signal is varied more rapidly as the absolute value of the sum of the above-mentioned phase shift amounts is larger.

In such a clock switching circuit, the phase of the synchronous clock can be changed in such a direction that the integrated value of the phase shift amount that has been actually changed earlier becomes larger as the integrated value becomes larger. Is done.

Further, the above-mentioned object is achieved by that the phase of the synchronous clock signal is changed stepwise in a direction in which the phase difference monitored by the phase difference monitoring means is compressed in the shortest time every time the current element is updated. This is achieved by a clock switching circuit characterized in that In such a clock switching circuit, the redundancy due to the two directions in which the phase of the synchronous clock can be varied depends on the number of clock signals individually corresponding to the plurality of elements constituting the redundant system. The element that is currently used and the element that has been used before the element are eliminated based on the phase difference of the clock signal corresponding to the element.

Further, the above-mentioned object is to provide a system in which the system is configured as a dual system, and the difference between the phase of the clock signal individually corresponding to the element currently used and the element currently used prior to the element is determined. A clock characterized in that the phase of the synchronous clock signal is varied stepwise in the direction of the shortest compression, and the phase of the synchronous clock signal is varied stepwise each time the working element is updated. This is achieved by a switching circuit.

In such a clock switching circuit, the direction in which the phase of the synchronous clock should be varied depends on whether the current element is specified for the first time based on the system configuration, and one element used for the current operation and the other element And the phase difference of the clock signal corresponding to each is set in the direction to be compressed in the shortest time, and is inverted each time the working element is subsequently updated. Further, the above object is achieved by a clock switching circuit characterized in that the larger the absolute value of the phase difference monitored by the phase monitoring means, the faster the phase of the synchronous clock signal is changed.

In such a clock switching circuit, the difference between the phases of the synchronous clocks decreases as the phases of the clock signals individually corresponding to the two elements constituting the duplex system differ greatly. Variable at high speed. In addition, the above-described object is achieved in such a manner that, during a period in which the phase of the synchronous clock signal is varied, the direction in which the phase of the synchronous clock signal is to be varied is inverted at a time after the current element is updated. This is achieved by a clock switching circuit characterized by the point.

In such a clock switching circuit, even if the current element is updated based on the system configuration during the above-described period, the phase of the synchronous clock signal is changed during the remaining time of this period following that point. The direction to be changed is changed promptly and appropriately.

Further, the above-mentioned object is achieved by providing a frequency synthesizing unit which generates a signal by performing a frequency synthesizing process on the synchronous clock signal or the clock signal selected by the second selecting unit, and has a desired response. This is achieved by a clock switching circuit characterized by a point.

In such a clock switching circuit, even if the synchronous clock signal or the clock signal selected by the second selecting means cannot be directly applied to realize the desired processing or function, the clock switching circuit is suitable for the frequency synthesizing means. As long as a proper combination ratio is set, signals of the frequency and phase necessary for realizing these processes and functions synchronized with these clock signals can be obtained.

Further, the above-mentioned object is characterized in that a node device is characterized by taking an interface with a redundantly configured network and performing predetermined communication control in synchronization with a clock signal given by the above-described clock switching circuit. Achieved by

In the node device having such a configuration, even when the system configuration is frequently updated, and the phase of the clock signal individually corresponding to the plurality of elements described above fluctuates widely or is largely different, Communication control is performed stably. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a principle block diagram of a clock switching circuit according to the present invention. FIG. 2 is a principle block diagram of the node device according to the present invention.

FIG. 3 is a diagram showing first and second embodiments of the present invention.

FIG. 4 is an operation time chart of the first embodiment of the present invention.

FIG. 5 is a diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing a fourth embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration example of a clock switching circuit provided in a redundant network. FIG. 8 is an operation time chart of the conventional example. BEST MODE FOR CARRYING OUT THE INVENTION

First, the principle of the clock switching circuit according to the present invention will be described.

FIG. 1 is a principle block diagram of a clock switching circuit according to the present invention. The clock switching circuit shown in FIG. 1 includes first selection means 11 and 11 A, clock recovery means 12 and 12 A, phase difference measurement means 13 and 13 A second selection means 14 and 1 It comprises 4 A, phase difference monitoring means 15 and 15 A, and frequency synthesis means 16 and 16 A.

The principle of the first clock switching circuit according to the present invention is as follows. The first selecting means 11 selects a clock signal corresponding to a current element from among a plurality of clock signals individually corresponding to a plurality of elements constituting a redundant system based on the system configuration. The clock regenerating means 12 generates a synchronous clock signal synchronized with a clock signal corresponding to an element which has been used in advance among the plurality of clock signals. The phase difference between the clock signal selected by the means 11 and the synchronous clock signal generated by the clock recovery means 12 is measured. The second selecting means 14 selects the synchronous clock signal generated by the clock recovery means 12 when the current element is updated, and selects the phase difference measured by the phase difference measuring means 13. Is smaller than a predetermined threshold, the clock signal selected by the first selecting means 11 is selected. Clock recovery means 1 and 2 Each time the element is updated, the phase of the synchronous clock signal is changed stepwise in the opposite direction alternately, and the phase difference measured by the phase difference measuring means 13 is compressed.

Therefore, it is possible to prevent the phase error of the clock signal output by the clock switching circuit according to the present invention from becoming excessive, and to provide a device or system that synchronizes with the clock signal or performs a predetermined process with a high response. And the performance is maintained stably.

The principle of the second clock switching circuit according to the present invention is as follows. The first selecting means 11 selects a clock signal corresponding to a current element from among a plurality of clock signals individually corresponding to a plurality of elements constituting a redundant system based on the system configuration. The clock regenerating means 12 generates a synchronous clock signal synchronized with a clock signal corresponding to an element which has been used in advance among the plurality of clock signals. The phase difference between the clock signal selected by the selection unit 11 and the synchronous clock signal generated by the clock recovery unit 12 is measured. The second selecting means 14 selects the synchronous clock signal generated by the clock recovery means 12 when the current element is updated, and selects the phase difference measured by the phase difference measuring means 13. Is smaller than a predetermined threshold, the clock signal selected by the first selecting means 11 is selected. The clock regenerating means 12 converts the phase difference measured by the phase difference measuring means 13 and the phase shift amount at which the sum of the phase shift amounts actually changed earlier by the phase of the synchronous clock signal decreases. Then, the phase of the synchronous clock signal is varied stepwise.

In such a clock switching circuit, the phase of the synchronous clock is appropriately changed in such a direction that the integrated value of the phase shift amount actually changed before the phase does not increase. Therefore, the phase error of the clock signal output by the clock switching circuit according to the present invention is maintained at a small value, and in a device or system that synchronizes with the clock signal or performs a predetermined process, the response is low. And high performance and are maintained stably.

The principle of the third clock switching circuit according to the present invention is as follows. The clock recovery means 12 changes the phase of the synchronous clock signal at a higher speed as the absolute value of the sum of the phase shift amounts increases.

Therefore, the phase error of the clock signal output by the clock switching circuit according to the present invention is accurately maintained at a small value, and in a device or system that synchronizes with the clock signal or performs a predetermined process, the response is low. And performance are kept higher and stable.

The principle of the fourth clock switching circuit according to the present invention is as follows. The first selecting means 11 selects a clock signal corresponding to a current element from among a plurality of clock signals individually corresponding to a plurality of elements constituting a redundant system based on the system configuration. The clock regenerating means 12 is a _c phase difference measuring means 13 for generating a synchronous clock signal synchronized with a clock signal corresponding to an element which has been used in advance among a plurality of clock signals. The phase difference between the clock signal selected by the selecting means 11 and the synchronous clock signal generated by the clock reproducing means 12 is measured. The second selecting means 14 selects the synchronous clock signal generated by the clock recovery means 12 when the current element is updated, and selects the phase difference measured by the phase difference measuring means 13. When the clock signal falls below a predetermined threshold, the clock signal selected by the first selecting means 11 is selected. The phase difference monitoring means 15 monitors the phase difference between the clock signal individually corresponding to the currently used element and the element previously used for the element among the plurality of clock signals. . Each time the working element is updated, the clock recovery means 12 steps the phase of the synchronous clock signal in a direction to compress the phase difference monitored by the phase difference monitoring means 15 in the shortest time. variable, and it compresses the difference in phase of the I _u connexion measuring the phase difference measurement unit 1 3.

In such a clock switching circuit, the redundancy due to the two directions in which the phase of the synchronous clock can be varied depends on the number of clock signals individually corresponding to the plurality of elements constituting the redundant system. Based on the phase difference of the clock signal corresponding to the element currently used and the element previously used for the element that is currently used. Be excluded.

Therefore, the phase of the synchronous clock is maintained at a suitable value that enables rapid compression of the above-described phase difference, and the phase of the clock signal output by the clock switching circuit according to the present invention corresponds to each element. Even when the phase of the clock signal varies widely or is significantly different, the phase is properly and stably maintained without unnecessary fluctuation.

The principle of the fifth clock switching circuit according to the present invention is as follows. The first selecting means 11A selects a clock signal corresponding to the current element from the two clock signals individually corresponding to the two elements constituting the duplicated system based on the system configuration. The clock regenerating means 12A generates a synchronous clock signal synchronized with the clock signal corresponding to the element which has been used in advance of the two clock signals. The phase difference measuring means 13A measures a phase difference between the clock signal selected by the first selecting means 11A and the synchronous clock signal generated by the clock reproducing means 12A. The second selecting means 14A selects the synchronous clock signal generated by the clock regenerating means 12A when the current element is updated, and at the time of starting, and by the phase difference measuring means 13A. When the measured phase difference falls below a predetermined threshold, the clock signal selected by the first selecting means 11A is selected. The phase difference monitoring means 15A monitors a phase difference between clock signals individually corresponding to one element currently used and the other element among the two clock signals. The clock regenerating means 12 A gradually changes the phase of the synchronous clock signal in a direction in which the phase difference monitored by the phase difference monitoring means 15 A is compressed in the shortest time when the working element is determined for the first time. The phase difference measured by the phase difference measuring means 13 A is changed by changing the phase of the synchronous clock signal stepwise in the opposite direction alternately each time the working element is updated. Compress.

In such a clock switching circuit, the direction in which the phase of the synchronous clock should be changed depends on whether the current element is specified for the first time based on the system configuration, and one of the elements currently used and the other is used. The phase difference of the clock signal corresponding to each of the elements is set in the direction to be compressed in the shortest time, and is alternately inverted each time the working element is subsequently updated. Therefore, the process for determining the direction in which the phase of the synchronous clock should be varied is simplified while adapting to the above-described phase difference, and the suitable responsiveness to the system configuration is stably maintained.

The principle of the sixth clock switching circuit according to the present invention is as follows. The clock recovery means 12 changes the phase of the synchronous clock signal at a higher speed as the absolute value of the phase difference monitored by the phase monitoring means 15 and 15A increases.

In such a clock switching circuit, the difference between the phases of the synchronous clocks decreases as the phases of the clock signals individually corresponding to the two elements constituting the duplex system differ greatly. Variable at high speed.

The principle of the seventh clock switching circuit according to the present invention is as follows. The clock regenerating means 12 A inverts the direction in which the phase of the synchronous clock signal is to be varied during the period after the current element is updated during the period in which the phase of the synchronous clock signal is varied. .

Therefore, the responsiveness is improved compared to the case where the direction in which the phase of the clock signal is changed is not changed until the phase where the phase of the synchronous clock signal is changed first after the time when the working element is updated. Enhanced.

The principle of the eighth clock switching circuit according to the present invention is as follows. The frequency synthesizing means 16 and 16 A have desired responsiveness, and perform frequency synthesizing processing on the synchronous clock signal or the clock signal selected by the second selecting means 14 and 14 A. To generate a signal.

In such a clock switching circuit, the second selecting means 14 and 14 A Even if the selected synchronous clock signal or clock signal cannot be directly applied to achieve the desired processing or function, as long as the appropriate synthesizing ratio is set in the frequency synthesizing means 16 and 16 A, A signal having the frequency and phase necessary for realizing these processes and functions is obtained in synchronization with the clock signal.

Therefore, it can be flexibly applied to various devices and systems.

FIG. 2 is a principle block diagram of the node device according to the present invention.

The node device shown in FIG. 2 includes a network interface unit 21, a clock switching circuit 22, 22 A, 22 B, 22 C, and communication control units 23, 23 A, 23 B, 23 C. Composed 1

The principles of the first to fourth node devices according to the present invention are as follows. The network interface means 21 takes an interface with a redundantly configured network. The second selecting means 14 and 14 A are, like the clock switching circuit described above, the first selecting means 11 and 11 A, the clock generating means 12 and 12 A, and the phase difference measuring means 1 By linking with 3, 13 A and the phase difference monitoring means 15, 15 A, the current link among the plurality of clock signals individually corresponding to the plurality of links constituting the network described above Select the clock signal synchronized with the clock signal corresponding to, based on the system configuration. The communication control means 23, 23A, 23B, and 23C cooperate with the network interface means 21 in synchronization with the clock signal selected in this way to perform predetermined communication control.

In such a node device, the clock signal supplied to the above-described communication control by the network interface means 21 has a frequently updated system configuration, and further has a phase of the clock signal individually corresponding to the above-described plurality of elements. Even if is widely fluctuated or greatly different, it can be supplied stably without excessive jumps or errors in phase.

Therefore, in the communication control process described above, the occurrence of slip due to the phase of the clock signal being continuously varied only in the specific direction _u and the unnecessary integration of the transmission delay time are avoided, and the service quality and transmission quality are prevented. Is maintained high and stable.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Embodiment 1] FIG. 3 is a diagram showing first and second embodiments of the present invention.

In the first embodiment of the present invention, as shown in FIG. 3, the phase control shown in FIG. A phase control section 31 different from the section 64 is provided in place of the phase control section 64.

Hereinafter, the operation of the first embodiment of the present invention will be described with reference to FIGS. The phase controller 31 has a flip-flop (not shown) therein, and resets the flip-flop at the time of start-up, and further updates the “working transmission line” indicated by the system configuration information described above. By inverting the flip-flop every time (Fig. 4 (1)), binary control information (hereinafter referred to as “phase flag”) is generated.

The phase controller 31 gives the following command to the synchronous oscillator 61 at a predetermined frequency only during a period (FIG. 4 (2)) in which the phase difference measured by the phase comparator 63 exceeds the predetermined threshold. I can.

· If the logic value of the “phase flag” is “0”, a command P indicating that the phase of the “synchronous clock signal” should be advanced (or delayed) (Fig. 4 (3))

• If the logic value of the “phase flag” is “1”, a command N indicating that the phase of the “synchronous clock signal” should be delayed (or advanced) (Fig. 4 (4))

The synchronous oscillator 61 intermittently sets the above-described frequency division ratio to a small value or a large value in response to such a command, thereby advancing or delaying the phase of the “synchronous clock signal” as appropriate.

That is, the phase of the “synchronous clock” generated by the synchronous oscillator 61 is changed in the opposite direction each time the system configuration is updated.

As described above, according to the present embodiment, the phase of the “synchronous clock signal” is specific, regardless of how frequently the “working transmission line” is updated, as compared with the conventional example in which the direction is fixed as described above. A shift in the direction is avoided.

[Embodiment 2]

Hereinafter, a second embodiment of the present invention will be described.

In this embodiment, as shown in FIG. 3, a phase control unit 31 is used instead of the phase control unit 31. A is provided.

Hereinafter, the operation of the second embodiment of the present invention will be described with reference to FIG.

The phase controller 31A has an up / down counter (not shown) in addition to the above-mentioned flip-flop inside, resets the flip-flop and the up / down counter at the time of starting, and During the period in which the phase difference measured by the comparing unit 63 exceeds a predetermined threshold, the following processing is performed at a predetermined frequency.

-The logical value (hereinafter, referred to as “phase flag”) held in the flip-flop is “0”, and the count value of the up / down count (hereinafter, simply referred to as “count value”) is “default”. If the value falls below the lower limit value and is less than the predetermined upper limit value (hereinafter referred to as “intermediate value”), the “count value” is incremented and the synchronous oscillator 61 receives the “count value”. Command indicating that the phase of the “synchronous clock signal” should be advanced (or delayed) ”.

• If the “phase flag” is “0” and the “count value” is equal to the upper limit described above, the “phase flag” is inverted and the “count value” is decremented and synchronized. A command indicating that the phase of the “synchronous clock signal” should be delayed (or advanced) is given to the oscillator 61.

• If the “phase flag” is “1” and the “count value” corresponds to the “intermediate value”, the “count value” is decremented, and the “sync clock signal” is sent to the synchronous oscillator 61. To indicate that the phase of “should be delayed (or advanced)”.

• When the “phase flag” is “1” and the “count value” is equal to the lower limit described above, the “phase flag” is inverted and the “count value” is incremented, and the synchronous oscillator is used. 6 Give 1 a command to indicate that the phase of the “synchronous clock signal” should be advanced (or delayed).

That is, the phase of the “synchronous clock signal” generated by the synchronous oscillator 61 is within the range of the “count value” defined in advance as a pair of the upper limit value and the lower limit value described above. It is updated as appropriate according to the system configuration. Note that, for simplicity, these upper and lower limits are assumed to have different signs and the same absolute value in the following. As described above, according to the present embodiment, each time the “working transmission line” is updated according to the system configuration, the phase of the “synchronous clock signal” is simply changed in the opposite direction. Flexibly, the phase is kept from being updated in a particular direction. Furthermore, it is possible to apply various algorithms that can maintain the phase of the “synchronous clock signal” at a suitable value according to the phase fluctuation of the clock signal 0 and the clock signal 1 and the combination of these phases. .

Note that the present embodiment is configured by applying the present invention to the above-described first embodiment.

However, by applying the present invention to other embodiments described later, flexible adaptation to the various algorithms described above may be further achieved.

Further, in the present embodiment, the phase of the “synchronous clock signal” is updated at a constant speed according to the above-mentioned command.

However, the present invention is not limited to such a configuration. For example, the following frequency (or rate of change) adapted to the above-described count value of the down-counting and the direction in which the count value should be updated is used. The responsiveness may be improved by updating the phase of the “synchronous clock signal”.

• During periods when the count is positive and the count is incremented, the higher the count, the lower the frequency (or small rate of change).

■ During periods when the count is positive and the count is decremented, the greater the count, the greater the frequency (or the greater the rate of change).

• During periods when the count is negative and the count is decremented, the smaller the count, the lower the frequency (or the greater the rate of change).

· During periods when the count is negative and the count is incremented, the smaller the count, the greater the frequency (or small rate of change)

[Embodiment 3]

FIG. 5 is a diagram showing a third embodiment of the present invention.

In this embodiment, the above-described clock signal 0, clock signal 1, and system configuration information are used. A phase difference measuring section 41 is provided which is provided and whose output is connected to a corresponding control input of the phase control section 31.

Hereinafter, the operation of the third embodiment of the present invention will be described with reference to FIG.

The phase difference measuring unit 41 identifies the “working transmission line” based on the system configuration information, and selects one of the clock signal 0 and the clock signal 1 that does not correspond to the “working transmission line” ( It measures the phase difference (hereinafter, simply referred to as “phase deviation”) between the clock signal and the other clock signal at a predetermined frequency.

On the other hand, the phase control unit 31 has a flip-flop and inverts this flip-flop every time the “working transmission path” indicated by the system configuration information is updated, as in the first embodiment described above. This generates a binary “phase flag”.

During the period when the phase difference measured by the phase comparison unit 63 exceeds the predetermined lower limit, the phase control unit 31 determines the `` change rate '' to be added to the command described later according to the `` phase deviation '' described above. Calculated as follows.

• If the “phase deviation” is greater than or equal to 0 degrees and less than 180 degrees, the value given as a positive monotone non-decreasing function for that “phase deviation”

• If the “phase deviation” is greater than or equal to 180 degrees and less than 360 degrees, it is given as a positive monotone non-decreasing function for the difference between that “phase deviation” and 180 degrees value

Further, the phase controller 64 gives the following command to the synchronous oscillator 61 at a predetermined frequency during a period in which the phase difference measured by the phase comparator 63 exceeds a predetermined lower limit.

• If the logical value of the “phase flag” is “0” and the “phase deviation” is less than 180 degrees, the phase of the “synchronous clock signal” is advanced by the “change rate” described above. Or delay) Directive to indicate

• If the logic value of the “phase flag” is “0” and the “phase deviation” is 180 degrees or more, “delay the phase of the synchronous clock signal j with the“ change rate ”described above.

Directive to indicate (or proceed)

• If the logic value of the “phase flag” is “1” and the “phase deviation” is less than 180 degrees, the phase of the “synchronous clock signal” is delayed by the “change rate” described above.

Directive to indicate (or proceed) • If the logic value of the “phase flag” is “1” and the “phase deviation” is 180 degrees or more, the phase of the “synchronous clock signal” is advanced by the “change rate” described above. Or delay) Directive to indicate

The synchronous oscillator 61 intermittently sets the above-mentioned division ratio to a small value or a large value over a value corresponding to the above-mentioned “rate of change” included in such a command, thereby obtaining “ Advance or delay the phase of the “synchronous clock signal” as appropriate.

In other words, the phase of the “synchronous clock” generated by the synchronous oscillator 61 is not biased in a specific direction every time the system configuration is updated, and changes with a higher frequency or speed as the difference from the target value increases. Is done.

Therefore, according to the present embodiment, even if the “working transmission path” is updated frequently, it is constant based on the logical value of the “phase flag” regardless of the “phase deviation” described above. It is more accurate than in the first embodiment in which the "phase deviation" is compressed at the speed of, and the phase is prevented from being continuously updated in a specific direction.

In the present embodiment, the “phase deviation” is measured as the phase difference between the clock signal corresponding to the “working transmission line” and the “working transmission line” identified based on the system configuration information. Have been.

However, the present invention is not limited to such a configuration. For example, regardless of the system configuration information, “phase deviation” is measured as the difference between the phase of the clock signal 0 and the phase of the clock signal 1 and transmitted. According to the “preceding working transmission line” (“working transmission line”) indicated by the system configuration information, the “phase deviation” is the sum of 180 ° and 180 °. (Or a difference from 360 degrees), and then applied to the above-described operation, thereby simplifying the configuration or distributing functions and loads. In the present embodiment, the phase of the “synchronous clock signal” is changed at a different “change rate” adapted to the “phase deviation”.

However, the present invention is not limited to such a configuration. For example, if the “phase deviation” can be compressed with a desired accuracy, the “synchronization” can be performed at a constant “rate of change” regardless of the “phase deviation”. By changing the phase of the “clock signal”, the configuration may be simplified and the responsiveness may be improved.

Further, in the present embodiment, the present invention is applied to the above-described first embodiment. However, the present invention is not limited to such a configuration. For example, by applying the present invention to the second embodiment, the phase shift amount of the phase of the “synchronous clock signal” that is actually changed The phase may be updated at a higher speed as the integrated value of is larger. In the present embodiment, the “change rate” described above is updated according to the “phase deviation” measured by the phase difference measurement unit 41, and the phase of the “synchronous clock signal” is updated by the “change rate”. Have been.

However, the present invention is not limited to such a configuration. If the transmission delay time is kept constant with a desired accuracy and the occurrence of slip is avoided, for example, the phase difference as shown by the dotted line in FIG. The measuring unit 41 is added to the above-described first embodiment, and only at the time of start-up, the phase and / or value of the phase of the “synchronous clock signal” is determined for determining one or both values. By providing the “phase deviation” measured by the phase difference measurement unit 41, unnecessary decrease in responsiveness and increase in power consumption may be avoided.

Further, in each of the above-described embodiments, the “working transmission line” indicated by the system configuration information is identified at each time when the above-described command is generated.

However, the present invention is not limited to such a configuration. For example, if the “working transmission path” is updated during the period in which the “synchronous clock signal” is updated, the “system” The direction in which the phase of this “synchronous clock signal” should be updated during the period after the “configuration time” is independently autonomously by the synchronous oscillator 61 (or in cooperation with the phase control units 31 and 31A). By setting to, transmission quality and service quality may be further enhanced along with responsiveness.

[Embodiment 4]

FIG. 6 is a diagram showing a fourth embodiment of the present invention.

In the figure, the transmission directions are opposite to each other, and two links 51-0 and 51-1 laid in two adjacent transmission sections are cascaded interface sections 52 and communication These transmission sections are divided by the control section 53 and the interface section 54. An input of a clock recovery unit 55 is connected to an output provided in the interface unit 52 and corresponding to the link 51-0 described above. The output provided in the interface section 54 and corresponding to the link 51-1 described above is connected to the clock recovery section 56. Input is connected. The outputs of the clock recovery units 55 and 56 are connected to the corresponding inputs of the clock switching circuit 57, and the output of the clock switching circuit 57 is connected to the clock input of the communication control unit 53. System configuration information is given to control inputs of the communication control unit 53 and the clock switching circuit 57.

Hereinafter, the operation of the fourth embodiment of the present invention will be described with reference to FIG.

The interface section 52 supplies a signal (hereinafter, referred to as “signal 0”) received via the link 51-0 to the communication control section 53 and the clock recovery section 55, and the interface section. Numeral 54 gives a signal (hereinafter, referred to as "signal 1") received via the link 51-1 to the communication controller 53 and the clock reproducer 56.

The clock reproducing unit 55 reproduces a clock signal superimposed on the signal 0 in a predetermined format and synchronized with the signal 0 (hereinafter, referred to as “clock signal 0”).

The clock reproducing unit 56 reproduces a clock signal superimposed on the signal 1 in a predetermined format and synchronized with the signal 1 (hereinafter, referred to as “clock signal 1”).

The clock switching circuit 57 is configured as a clock switching circuit according to any of the first to third embodiments described above, and stably supplies a clock signal synchronized with the “working transmission line”.

The communication control unit 53 performs communication control in synchronization with the clock signal and based on a predetermined transmission method, communication method, and communication procedure.

Regarding such a clock signal, the system configuration (“working transmission line”) is frequently updated according to the system configuration information described above, or the phase difference between the clock signal 0 and the clock signal 1 described above. Even if can vary widely, this phase error and variation can be minimized without significant jumps in phase during system configuration. As described above, according to the present embodiment, in the process of the communication control performed by the communication control unit 53, the phase of the “synchronous clock signal” is changed only in a specific direction along with the unnecessary integration of the transmission delay time. Since the occurrence of a slip due to the transmission is avoided, the service quality and the transmission quality are maintained at a high level and stably.

In each of the above-described embodiments, in order to obtain a clock signal synchronized with the clock signal corresponding to the active system among the two transmission lines constituting the duplexed transmission line and the clock signal individually corresponding to the link, The present invention has been applied. However, the present invention is not limited to such a duplicated system, and is similarly applicable to a system configured redundantly based on the N + 1 system or another system.

Further, in each of the above-described embodiments, the present invention is applied to a duplex transmission system.

However, the present invention is not limited to such a transmission system, and a clock corresponding to each of the redundantly provided elements is provided, and any of these elements is provided for a current operation under a predetermined system configuration. In a variety of systems and devices, the same can be applied to any of packages, units, and shelves that can be detached, closed, or restored as needed in the course of maintenance and operation.

Further, in each of the above-described embodiments, the phase-locked oscillator 65 is provided after the selector 60 s.

However, the present invention is not limited to such a configuration, and when a clock signal of a desired frequency to be stably obtained in accordance with the system configuration is directly provided by the selector 60 s, the above-described phase-locked oscillator 6 5 need not be provided.

The phase-locked oscillator 65 is provided for the purpose of generating a clock signal that synchronizes with the “clock signal 0” and “clock signal 1” and provides a desired next-group speed higher in speed than the frequency of these clock signals. In this case, a circuit capable of securing a desired time constant and responsiveness and a method of frequency synthesis are applied to the phase-locked oscillator 65 in cooperation with the clock switching circuit disposed in the preceding stage. Good.

Further, in each of the above-described embodiments, in addition to the transmission method, the transfer mode, and the communication procedure applied to the transmission paths 62-0 and 62-1 and the links 51-0 and 51-1 described above, The topology of the network composed of these transmission paths 62-0, 62-1, and links 51-0, 51-1 is not specifically shown.

However, regarding these transmission methods, transfer modes, communication procedures, and topologies, transmission lines 62-0 and 62-1 and links 51-0 and „51-1 have redundant networks and transmission systems. Any element may be used as long as it is an element.

In each of the above-described embodiments, the supply sources of “clock signal 0” and “clock signal 1” are not specifically shown.

However, these “Clock signal 0” and “Clock signal 1” are redundantly configured. It can be supplied by any source as long as it is individually addressed and supplied in parallel.

Further, the transmission line used for supplying such “clock signal 0” and “clock signal 1” may be supplied for each transmission section or may not be supplied via DCS, and may be used for transmission systems and networks. It may be either a specific path or link formed or a dedicated link laid separately from these paths and links.

Further, in each of the above-described embodiments, the synchronous oscillator 61 is configured as a variable frequency divider.

However, such a synchronous oscillator 61 may be realized based on any frequency synthesizing method as long as a “synchronous clock signal” having a desired frequency can be generated in synchronization with the “preceding working transmission line”.

Further, in each of the above-described embodiments, the phase of the “synchronous clock signal” is updated by intermittently changing the above-described division ratio at a predetermined frequency.

However, the phase of such a “synchronous clock signal” is determined by, for example, the output terminal of the synchronous oscillator 61 or a delay circuit (an analog circuit that may be configured as an analog circuit, and a shift register or other digital circuit). It may be updated by changing the amount of delay of.

Further, the present invention is not limited to the above-described embodiments, and various embodiments can be made within the scope of the present invention, and any or all of the constituent devices can be improved in any way. May be done. Industrial applicability

In the first clock switching circuit according to the present invention, it is possible to prevent the phase error of the output clock signal from becoming too large according to the update of the system configuration.

In the second clock switching circuit according to the present invention, the phase error of the output clock signal is maintained at a small value.

Furthermore, in the third and sixth clock switching circuits according to the present invention, the phase error of the output clock signal is accurately maintained at a small value.

In the fourth clock switching circuit according to the present invention, each element is Even if the phase of the clock signal changes widely, and these phases differ greatly, the phase of the output clock signal is maintained properly and stably without unnecessary fluctuation.

Furthermore, in the fifth clock switching circuit according to the present invention, the processing for determining the direction in which the phase of the synchronous clock should be varied is simplified, and the responsiveness to the system configuration is stably maintained.

Further, in the seventh clock switching circuit according to the present invention, the response is improved.

Further, in the eighth clock switching circuit according to the present invention, it is possible to flexibly apply to various device systems.

Further, in the first to fourth node devices according to the present invention, it is possible to avoid the occurrence of slips due to the phase of the clock signal being continuously varied only in a specific direction and the unnecessary integration of the transmission delay time. The service quality and transmission quality are kept high and stable.

Therefore, in the device or system to which the present invention is applied, the overall reliability and performance are improved and the device is stably maintained.

Claims

The scope of the claims

(1) first selection means for selecting a clock signal corresponding to a working element based on the system configuration from among a plurality of connection signals individually corresponding to a plurality of elements constituting a redundant system;

Clock recovery means for generating a synchronous clock signal synchronized with a clock signal corresponding to a previously used element of the plurality of clock signals;

A phase difference measuring unit that measures a phase difference between a clock signal selected by the first selecting unit and a synchronous clock signal generated by the clock reproducing unit; and when the current element is updated, When the synchronous clock signal generated by the clock recovery means is selected and the phase difference measured by the phase difference measurement means falls below a predetermined threshold, the clock selected by the first selection means is selected. And a second selecting means for selecting a clock signal,

The clock reproducing means,

Each time the working element is updated, the phase of the synchronous clock signal is changed stepwise in the opposite direction alternately, and the phase difference measured by the phase difference measuring means is compressed.

A clock switching circuit, characterized in that:

(2) first selection means for selecting, based on the system configuration, a clock signal corresponding to a working element among a plurality of clock signals individually corresponding to a plurality of elements constituting a redundant system;

Clock recovery means for generating a synchronous clock signal synchronized with a clock signal corresponding to an element which has been used in advance among the plurality of clock signals;

A phase difference measuring unit that measures a phase difference between a clock signal selected by the first selecting unit and a synchronous clock signal generated by the clock reproducing unit; and when the current element is updated, When the synchronous clock signal generated by the clock recovery means is selected and the phase difference measured by the phase difference measurement means falls below a predetermined threshold, the clock selected by the first selection means is selected. And a second selecting means for selecting a clock signal, The clock reproducing means,

The phase of the synchronous clock signal over a phase shift amount in which the phase difference measured by the phase difference measuring means and the sum of the phase shift amounts actually changed in advance of the phase of the synchronous clock signal decrease. Step by step

A clock switching circuit, characterized in that:

(3) In the clock switching circuit according to claim 2,

The clock reproducing means,

The larger the absolute value of the sum of the phase shift amounts, the faster the phase of the synchronous clock signal is varied.

A clock switching circuit, characterized in that:

(4) first selection means for selecting, based on the system configuration, a clock signal corresponding to a working element among a plurality of clock signals individually corresponding to a plurality of elements constituting a redundant system;

A phase difference measuring unit that measures a phase difference between a clock signal selected by the first selecting unit and a synchronous clock signal generated by the clock reproducing unit; and when the current element is updated, When the synchronous clock signal generated by the clock recovery means is selected, and the phase difference measured by the phase difference measurement means falls below a predetermined threshold, the clock selected by the first selection means is selected. Second selection means for selecting a lock signal;

Among the plurality of clock signals, there is provided a phase difference monitoring means for monitoring a phase difference of a clock signal individually corresponding to an element currently used and an element currently used prior to the element. ,

The clock reproducing means includes:

Each time the working element is updated, the phase of the synchronous clock signal is varied stepwise in a direction in which the phase difference monitored by the phase difference monitoring means is compressed in the shortest time. The phase difference measured by

A clock switching circuit, characterized in that:

(5) First selection means for selecting, based on the system configuration, a clock signal corresponding to a working element among two clock signals individually corresponding to two elements constituting a duplicated system,

Clock recovery means for generating a synchronous clock signal synchronized with a clock signal corresponding to an element which has been provided for use in advance among the two clock signals;

A phase difference measuring unit that measures a phase difference between a clock signal selected by the first selecting unit and a synchronous clock signal generated by the clock reproducing unit; and when the current element is updated, Selecting the synchronous clock signal generated by the clock regenerating means, and at the time of starting, and when the phase difference measured by the phase difference measuring means falls below a predetermined threshold value, Second selecting means for selecting the selected clock signal,

And a phase difference monitoring means for monitoring a phase difference between the clock signal individually corresponding to the element currently used and the element currently used prior to the element among the two clock signals. ,

The clock reproducing means,

When the working element is determined for the first time, the phase of the synchronous clock signal is varied stepwise in a direction in which the phase difference monitored by the phase difference monitoring means is compressed in the shortest time, and the working element is Each time the phase difference is updated, the phase difference measured by the phase difference measuring means is compressed by changing the phase of the synchronous clock signal stepwise in the opposite direction.

A clock switching circuit, characterized in that:

(6) In the clock switching circuit according to claim 4,

The clock reproducing means,

The greater the absolute value of the phase difference monitored by the phase monitoring means, the faster the phase of the synchronous clock signal is varied.

A clock switching circuit, characterized in that:

(7) In the clock switching circuit according to claim 5,

The clock reproducing means,

The faster the absolute value of the phase difference monitored by the phase monitoring means, the faster Variable phase of the synchronous clock signal

A clock switching circuit, characterized in that:

(8) In the clock switching circuit according to claim 5,

The clock reproducing means,

In the period in which the phase of the synchronous clock signal is varied, the direction in which the phase of the synchronous clock signal should be varied is inverted at a time after the point at which the working element is updated.

A clock switching circuit, characterized in that:

(9) In the clock switching circuit according to claim 1,

A frequency synthesizing unit having a desired response and generating a signal by subjecting the synchronous clock signal or the clock signal selected by the second selecting unit to a frequency synthesizing process;

A clock switching circuit, characterized in that:

(10) In the clock switching circuit according to claim 2,

A clock switching circuit, characterized in that:

(11) In the clock switching circuit according to claim 4,

A clock switching circuit, characterized in that:

(1 2) In the clock switching circuit according to claim 5,

A clock switching circuit having a desired responsiveness and having a frequency synthesizing means for generating a signal by performing frequency synthesis on a synchronous clock generated by the clock reproducing means.

(13) network interface means for taking an interface with a redundantly configured network; First selecting means for selecting a clock signal corresponding to a working element from among a plurality of clock signals individually corresponding to a plurality of elements constituting the network based on a system configuration; and A clip reproducing means for generating a synchronous clip signal synchronized with a clip signal corresponding to the element which has been previously used in operation;

A phase difference measuring unit that measures a phase difference between a clock signal selected by the first selecting unit and a synchronous clock signal generated by the clock reproducing unit; and when the current element is updated, When the synchronous clock signal generated by the clock recovery means is selected and the phase difference measured by the phase difference measurement means falls below a predetermined threshold, the clock selected by the first selection means is selected. A second selecting means for selecting a clock signal;

Communication control means for performing predetermined communication control in cooperation with the network interface means in synchronization with the synchronous clock signal and the clock signal selected by the second selection means,

The clock reproducing means,

A node device characterized by the above-mentioned.

(14) network interface means for taking an interface with a redundantly configured network;

First selecting means for selecting a clock signal corresponding to a working element from among a plurality of clock signals individually corresponding to a plurality of elements constituting the network based on a system configuration; and A clock recovery means for generating a synchronous clock signal synchronized with a clock signal corresponding to the element previously used for the current operation;

The clock reproducing means,

A node device characterized by the above-mentioned.

(15) network interface means for interfacing with a redundantly configured network;

Phase difference monitoring means for monitoring the phase difference between the clock signal individually corresponding to the element currently used and the element previously used for the element among the plurality of clock signals,

The clock reproducing means,

Each time the working element is updated, the position monitored by the phase difference monitoring means The phase of the synchronous clock signal is varied stepwise in the direction in which the phase difference is compressed in the shortest time, and the phase difference measured by the phase difference measuring means is compressed.

A node device characterized by the above-mentioned.

(16) A network interface means for taking an interface with a duplicated network, and a clock element corresponding to a working element among two clock signals individually corresponding to the two elements constituting the network. First selecting means for selecting a clock signal based on a system configuration; and generating a synchronous clock signal synchronized with a clock signal corresponding to a previously used element of the two clock signals. Clock recovery means;

Phase difference monitoring means for monitoring the phase difference between the clock signal individually corresponding to the element currently used and the element currently used prior to the element of the two clock signals;

The clock reproducing means,

A node device characterized by the above-mentioned.