CN116366197A - Method, device and system for locking fast clock in switching between main clock and standby clock - Google Patents
Method, device and system for locking fast clock in switching between main clock and standby clock Download PDFInfo
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Abstract
The invention relates to a method, a device and a system for locking a master clock and a slave clock in quick switching, wherein the method comprises the following steps: after the primary clock signal and the standby clock signal are divided into two parts, carrying out phase discrimination processing on one primary clock signal and one standby clock signal to obtain a feedback signal; the feedback signal is applied to the primary clock signal or the backup clock signal through a phase locked loop to phase the primary clock signal and the backup clock signal. The time interval of clock locking during clock switching can be reduced, and smooth transition of main and standby switching is facilitated.
Description
Technical Field
The present invention relates to the field of optical transmission network clock synchronization technology, and in particular, to a method, an apparatus, and a system for fast clock locking during switching between a main clock and a standby clock.
Background
In the field of optical transmission networks, the synchronous clock of the network is very important for data transmission, so that a protection mode of a main clock unit and a standby clock unit is generally adopted. The service disc selects the system clock according to the main and standby states of the clock unit, and when the main uses fail or the main and standby are switched, the previous main use clock is switched to standby, and the previous standby clock is switched to the main use, so that the main and standby switching is completed once.
When the main use is faulty or the main and standby switches, the phase jump of the main and standby clocks can affect the service disk, so that the problems of pipe dropping, service interruption, error code and the like of the service disk are caused, and the stability of the service is seriously affected. In the related art, the main clock and the standby clock are sampled and phase-shifted through the high frequency multiplication clock, and the main clock and the standby clock are phase-aligned through frequency multiplication to reduce the alarms such as error codes, lof and the like generated in the switching process. But moving the standby clock to the same phase as the multiplied clock may have a phase error of 1-2 multiplied clocks. In other techniques, in order to achieve smooth transition, the phase is adjusted by analog devices such as analog phase detectors, DDS, DA, etc. At present, the approximate precision of the FPGA is 10-200ps, and the requirements of customers cannot be met well. Therefore, the time interval of clock switching and clock locking is reduced, so that the smooth transition of the main switching and the standby switching becomes a key technology which needs to be solved seriously at present.
Disclosure of Invention
The embodiment of the invention provides a method, a device and a system for locking a fast clock in switching between a main clock and a standby clock. The time interval of clock locking during clock switching can be reduced, and smooth transition of main and standby switching is facilitated.
In a first aspect, an embodiment of the present invention provides a method for locking a fast clock during switching between a master clock and a slave clock, which is characterized in that the method includes:
after the primary clock signal and the standby clock signal are divided into two parts, carrying out phase discrimination processing on one primary clock signal and one standby clock signal to obtain a feedback signal;
the feedback signal is applied to the primary clock signal or the backup clock signal through a phase locked loop to phase the primary clock signal and the backup clock signal.
In some embodiments, the dividing the primary clock signal and the standby clock signal into two, respectively, includes the steps of:
the method comprises the steps that after a main clock signal passes through a main phase-locked loop, two main clock sub-signals with the same frequency and phase are obtained;
and the standby clock signal is subjected to a standby phase-locked loop to obtain two standby clock sub-signals with the same frequency and phase.
In some embodiments, the step of performing the phase discrimination processing on one of the primary clock signals and one of the standby clock signals to obtain the feedback signal includes the steps of:
a main clock division signal and a standby clock division signal are subjected to phase discrimination processing through a main TDC to output a main clock feedback signal,
and carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal.
In some embodiments, the phase-discrimination process includes the steps of:
the main TDC outputs a main clock feedback signal capable of reducing the phase difference of the main clock sub-signal and the standby clock sub-signal according to the phase difference of the main clock sub-signal and the standby clock sub-signal;
the standby TDC outputs a standby clock feedback signal capable of reducing the phase difference of the other main clock sub-signal and the other standby clock sub-signal according to the phase difference.
In some embodiments, the applying the feedback signal to the primary clock signal or the backup clock signal through a phase locked loop to phase the primary clock signal and the backup clock signal comprises the steps of:
inputting the main clock feedback signal into the main phase-locked loop, wherein the main phase-locked loop is used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
and inputting the standby clock feedback signal into the standby phase-locked loop, wherein the standby phase-locked loop is used for adjusting the phase of the standby clock division signal according to the standby clock feedback signal to be consistent with the phase of the standby clock division signal.
In some embodiments, the method further comprises the step of:
taking the signal output by the main TDC as a final output signal of the main clock signal;
and taking the signal output by the standby TDC as a final output signal of the standby clock signal.
In some embodiments, the method further comprises the step of: and carrying out frequency division processing on the final output signal.
In a second aspect, an embodiment of the present invention further provides a fast clock locking device for switching between a master clock and a slave clock, which is characterized in that the fast clock locking device includes:
the main and standby phase adjustment modules are used for respectively dividing the main clock signal and the standby clock signal into two parts and then carrying out phase discrimination processing on one main clock signal and one standby clock signal to obtain a feedback signal;
and the phase feedback processing module is used for enabling the feedback signal to act on the main clock signal or the standby clock signal through a phase-locked loop so as to enable the phases of the main clock signal and the standby clock signal to be consistent.
In a third aspect, an embodiment of the present invention further provides a fast clock locking system for switching between a master clock and a slave clock, which is characterized in that the fast clock locking system includes:
the main phase-locked loop is used for dividing the main clock signal into two parts to obtain two main clock divided signals with the same frequency and phase;
a standby phase-locked loop for dividing the standby clock signal into two to obtain two standby clock divided signals with the same frequency and phase;
the main phase adjustment module is used for carrying out phase discrimination processing on a main clock sub-signal and a standby clock sub-signal through a main TDC to output a main clock feedback signal;
the standby phase adjustment module is used for carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal;
the main phase-locked loop is also used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
the standby phase-locked loop is also used for adjusting the phase of the standby clock division signal to be consistent with the standby clock division signal according to the standby clock feedback signal.
In some embodiments, the primary phase adjustment module is further configured to output a primary clock feedback signal capable of reducing a phase difference of the primary clock signal and the standby clock signal according to the phase difference;
the standby phase adjustment module is further configured to output a standby clock feedback signal capable of reducing a phase difference of the other main clock division signal and the other standby clock division signal according to the phase difference.
The embodiment of the invention provides a method and a device for locking a fast clock in switching between a main clock and a standby clock. The digital phase-locked loop is realized through the clock network offset correction model and the TDC time digital converter, so that the phase discrimination function can be realized, and meanwhile, the TDC also greatly improves the precision control of the phase difference, thereby solving the problem of long-time lock loss during the main and standby switching. The time-to-digital converter of the TDC is realized, namely a small counting module is inserted into the existing clock period of the FPGA, so that the existing clock is subdivided into one period, the precision is higher, and the phase difference between the two main clocks and the standby clocks after adjustment is smaller. In the related art, the FPGA is used for realizing the level of about 10-200ps, and under the same condition, the scheme provided by the embodiment of the invention has about 0-103ns (estimated by 19.44M clock), so that the time delay measurement precision is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a fast clock locking method for switching between a master clock and a slave clock according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a fast clock locking system for switching between active and standby clocks according to an embodiment of the present invention;
FIG. 3 is a phase-locked loop correction flow chart according to an embodiment of the present invention;
FIG. 4 is a timing diagram of phase locked loop correction according to an embodiment of the present invention;
fig. 5 is a schematic diagram of phase demodulation of a TDC according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a fast clock locking device for switching between a master clock and a slave clock according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, an embodiment of the present invention provides a fast clock locking method for switching between a master clock and a slave clock, which includes:
s100, dividing the main clock signal and the standby clock signal into two parts respectively, and carrying out phase discrimination processing on one part of the main clock signal and one part of the standby clock signal to obtain a feedback signal;
and S200, the feedback signal acts on the main clock signal or the standby clock signal through a phase-locked loop so as to enable the phases of the main clock signal and the standby clock signal to be consistent.
It can be understood that the phase-locked loop plays a role in frequency discrimination, so that the accuracy of the signal frequency after being divided into two parts can be ensured, and the problem that the accuracy cannot be ensured due to the distribution of the FPGA is avoided. The phase discrimination processing aims to obtain a processed clock with a phase close to the other direction, and then the processed clock is sent back to the phase-locked loop for feedback adjustment, so that the consistency of the final main phase and the final standby phase is ensured.
In the embodiment of the invention, the phase-locked loop and phase-discrimination processing are combined to form the function of the digital phase-locked loop, the phases of the main clock signal and the standby clock signal can be finally consistent through the adjustment of the feedback signals for many times, the interlocking of the main clock and the standby clock can be effectively realized, the smoothness and the stability of clock switching are effectively improved, the problem of long-time unlocking during the main-standby switching is solved, and higher-quality service can be provided for delay-sensitive clients, thereby having higher practical value. In addition, the embodiment provides a pure digital circuit FPGA implementation mode, compared with the mode based on oversampling phase discrimination or a phase-locked loop built by a digital circuit and a digital chip in the related art, the implementation mode can not depend on chip precision, can simplify the occupied circuit board area and reduce hardware cost, and can also ensure calibration precision.
In some embodiments, the step of splitting the primary clock signal and the secondary clock signal into two in S100 includes the steps of:
s110, obtaining two main clock sub-signals with the same frequency and phase after the main clock signal passes through a main phase-locked loop;
and S120, obtaining two standby clock division signals with the same frequency and phase after the standby clock signal passes through a standby phase-locked loop.
In some embodiments, in S100, the step of performing phase discrimination processing on one of the primary clock signals and one of the standby clock signals to obtain a feedback signal includes the steps of:
s130, carrying out phase discrimination processing on a main clock division signal and a standby clock division signal through a main TDC to output a main clock feedback signal,
and S140, carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal.
It can be understood that the TDC adopted in this embodiment can improve the accuracy control of the phase difference, and can be implemented by a TDC time-to-digital converter, which is equivalent to inserting a small counting module into the existing clock period of the FPGA, to implement the repartition of one period of the existing clock, so that the accuracy is higher, and thus the phase difference between the two main and standby clocks after adjustment is smaller. In the related art, the FPGA is used for realizing the level of about 10-200ps, and under the same condition, the scheme provided by the embodiment has about 0-103ns (estimated by 19.44M clock), so that the time delay measurement precision is effectively improved.
In some embodiments, during the phase demodulation process in S130 and S140, the main TDC outputs a main clock feedback signal capable of reducing the phase difference according to the phase difference between the main clock signal and the standby clock signal; the standby TDC outputs a standby clock feedback signal capable of reducing the phase difference of the other main clock sub-signal and the other standby clock sub-signal according to the phase difference.
As shown in fig. 5, T0 is a measured interval time, that is, a phase difference of the master clock signal and the slave clock signal, T1 is a measured start time, and T2 is a measured end time. Theoretically t0=t2-T1, but in reality, since FPGA sampling is clock rising edge sampling and T0 is 1 sampling clock, the calculated phase difference is t0=n×t0 (n=20 in fig. 5), and the calculated error is t1+t2. According to the calculated clock phase difference, a clock with any phase at the time of T1-T2 can be spliced.
Preferably, when the primary TDC performs phase discrimination processing, a primary clock feedback signal with halved phase difference is output, and when the standby TDC performs phase discrimination processing, a standby clock feedback signal with halved phase difference is output, for example, if the primary clock signal phase is 7.8, the standby clock signal phase is 7.2, the primary clock feedback signal with average phase (i.e., (7.8+7.2)/2=7.5) is output at the primary TDC, the standby clock feedback signal with average phase (i.e., (7.2+7.8)/2=7.5) is output at the standby TDC, and the phase difference of 1 half can be reduced after each feedback, so as to finally ensure that the primary and standby clock output phases are consistent.
In some embodiments, S200 comprises:
s210, inputting the main clock feedback signal into the main phase-locked loop, wherein the main phase-locked loop is used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
s220, inputting the standby clock feedback signal into the standby phase-locked loop, wherein the standby phase-locked loop is used for adjusting the phase of the standby clock division signal to be consistent with the phase of the standby clock division signal according to the standby clock feedback signal.
In some embodiments, the signal output by the primary TDC may be used as the final output signal of the primary clock signal; and taking the signal output by the standby TDC as the final output signal of the standby clock signal.
It will be appreciated that as shown in fig. 3 for signals 2 and 3, the final phase locked loop adjustment results in the master and slave input clocks being exactly in phase, and then the master and slave clocks being interlocked. Meanwhile, the stability can be improved by continuously maintaining the feedback mechanism, and the phase-locked loop is prevented from losing lock due to emergency.
In some embodiments, the final output signal is also frequency divided. In the communication system, the demand for clock is 8K, but the primary and standby input clocks are 19.44M, and the clock signal required by the system can be obtained through frequency division processing.
As shown in fig. 6, the embodiment of the present invention further provides a fast clock locking device for switching between a master clock and a slave clock, which includes:
the main and standby phase adjustment modules are used for respectively dividing the main clock signal and the standby clock signal into two parts and then carrying out phase discrimination processing on one main clock signal and one standby clock signal to obtain a feedback signal;
and the phase feedback processing module is used for enabling the feedback signal to act on the main clock signal or the standby clock signal through a phase-locked loop so as to enable the phases of the main clock signal and the standby clock signal to be consistent.
In some embodiments, the master-slave phase adjustment module is further configured to:
the method comprises the steps that after a main clock signal passes through a main phase-locked loop, two main clock sub-signals with the same frequency and phase are obtained;
and the standby clock signal is subjected to a standby phase-locked loop to obtain two standby clock sub-signals with the same frequency and phase.
In some embodiments, the master-slave phase adjustment module is further configured to:
a main clock division signal and a standby clock division signal are subjected to phase discrimination processing through a main TDC to output a main clock feedback signal,
and carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal.
In some embodiments, the primary and standby phase adjustment modules output a primary clock feedback signal capable of reducing the phase difference of the primary clock sub-signal and the standby clock sub-signal according to the phase difference of the primary clock sub-signal and the standby clock sub-signal during phase discrimination processing; the standby TDC outputs a standby clock feedback signal capable of reducing the phase difference of the other main clock sub-signal and the other standby clock sub-signal according to the phase difference.
In some embodiments, the phase feedback processing module is further configured to:
inputting the main clock feedback signal into the main phase-locked loop, wherein the main phase-locked loop is used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
and inputting the standby clock feedback signal into the standby phase-locked loop, wherein the standby phase-locked loop is used for adjusting the phase of the standby clock division signal according to the standby clock feedback signal to be consistent with the phase of the standby clock division signal.
In some embodiments, the signal output by the primary TDC may be used as the final output signal of the primary clock signal; and taking the signal output by the standby TDC as the final output signal of the standby clock signal.
In some embodiments, a frequency divider is further included for frequency dividing the final output signal.
As shown in fig. 2, a master-slave clock switching fast clock locking system includes:
the main phase-locked loop is used for dividing the main clock signal into two parts to obtain two main clock divided signals with the same frequency and phase;
a standby phase-locked loop for dividing the standby clock signal into two to obtain two standby clock divided signals with the same frequency and phase;
the main phase adjustment module is used for carrying out phase discrimination processing on a main clock sub-signal and a standby clock sub-signal through a main TDC to output a main clock feedback signal;
the standby phase adjustment module is used for carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal;
the main phase-locked loop is also used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
the standby phase-locked loop is also used for adjusting the phase of the standby clock division signal to be consistent with the standby clock division signal according to the standby clock feedback signal.
In some embodiments, the primary phase adjustment module is further configured to output a primary clock feedback signal capable of reducing a phase difference of the one primary clock sub-signal and the one standby clock sub-signal according to the phase difference;
the standby phase adjustment module is further configured to output a standby clock feedback signal capable of reducing a phase difference of the other primary clock division signal and the other standby clock division signal according to the phase difference.
In one embodiment, clk1ai is the active source clock sent from the active CCU and Clk1bi is the standby source clock sent from the standby CCU, as shown in FIG. 2. Specifically, the master clock Clk1ai enters the phase locked loop process and then is split into two (Clk 1ao and Clk1 ao_fbout), wherein Clk1ao is sent to the master TDC for phase processing and Clk1ao_fbout is sent to the standby TDC for phase processing. The clock signal Clk1ao_fbout sent to the standby TDC performs phase demodulation on the standby terminal and the standby clock Clk1bo, and outputs and feeds back the clock feedback signal Clk1bo_fbin after phase adjustment to the standby terminal phase-locked loop for clock offset correction. Similarly, among the divided standby clock signals (Clk 1bo and Clk1 bo_fbout) outputted from the standby-side phase locked loop, one standby clock signal Clk1bo_fbout is sent to the main TDC and phase-authenticated with the main clock Clk1ao at the main side, and the phase-adjusted clock feedback signal Clk1ao_fbin is outputted and fed back to the main-side phase locked loop to perform clock offset correction. After the cyclic processing of multiple clock inputs, the main end outputs a clock with the same phase as the standby clock, then divides the frequency and outputs the clock, and the standby end also outputs a clock with the same phase as the main clock, and divides the frequency and outputs the clock. Spare direction same management
In the offset correction process of the phase-locked loop to the clock network shown in fig. 3, the signal 1 is a main/standby clock, the signal 6 is a standby/main output clock, the main/standby clock signal 1 is sent to an input global buffer bufg (represented by a small triangle in the middle of 1 and 2) and generates a signal 2, then the signal 2 is sent to the phase-locked loop as an input clock, after being divided into two parts by the phase-locked loop, the signal 4 and the signal 6 with the same frequency and phase are obtained, and the phase of the input signal 2 of the phase-locked loop is consistent with the phase of the signal 3, and the phase of the output signal 4 of the phase-locked loop is consistent with the phase of the signal 5 as known from the characteristics of the phase-locked loop. Wherein 4 is the output clock of the main/standby clock phase-locked loop, and 5 is the feedback output clock of the main/standby clock phase-locked loop. The phase adjustment module is used for adjusting the standby/main output clock signal 6 and sending the standby/main output clock signal and the main/standby feedback output clock signal 5 to the phase adjustment module (TDC) so as to adjust the phase of the standby/main output clock signal to be consistent with the phase of the output of the signal 5, and outputting the main/standby feedback input clock signal 3 after phase adjustment, wherein the clock phases of the signal 3 and the signal 4 are consistent because the clock phases of the signal 4 and the signal 5 are consistent. Therefore, as shown in the timing chart of fig. 4, the signals 2, 3, 4, 5, and 6 are adjusted by repeated positive feedback to achieve the same clock phase. Finally, on the two feedback loops of the main clock and the standby clock, the main signal clock and the standby signal clock are completely interlocked, so that Zhong Ping slip transition is realized when the main clock and the standby clock are switched.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable storage media, which may include computer-readable storage media (or non-transitory media) and communication media (or transitory media).
It should be noted that in the present invention, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for locking a master clock and a slave clock in a fast switching manner is characterized by comprising the following steps:
after the primary clock signal and the standby clock signal are divided into two parts, carrying out phase discrimination processing on one primary clock signal and one standby clock signal to obtain a feedback signal;
the feedback signal is applied to the primary clock signal or the backup clock signal through a phase locked loop to phase the primary clock signal and the backup clock signal.
2. The method for fast clock locking in switching between a main clock and a standby clock according to claim 1, wherein the step of dividing the main clock signal and the standby clock signal into two parts comprises the steps of:
the method comprises the steps that after a main clock signal passes through a main phase-locked loop, two main clock sub-signals with the same frequency and phase are obtained;
and the standby clock signal is subjected to a standby phase-locked loop to obtain two standby clock sub-signals with the same frequency and phase.
3. The method for fast clock locking in switching between a primary clock and a standby clock according to claim 2, wherein the step of performing the phase discrimination processing on one of the primary clock signal and the standby clock signal to obtain the feedback signal comprises the steps of:
a main clock division signal and a standby clock division signal are subjected to phase discrimination processing through a main TDC to output a main clock feedback signal,
and carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal.
4. A method for fast clock locking in a master-slave clock switching system as defined in claim 3, wherein said phase discrimination process comprises the steps of:
the main TDC outputs a main clock feedback signal capable of reducing the phase difference of the main clock sub-signal and the standby clock sub-signal according to the phase difference of the main clock sub-signal and the standby clock sub-signal;
the standby TDC outputs a standby clock feedback signal capable of reducing the phase difference of the other main clock sub-signal and the other standby clock sub-signal according to the phase difference.
5. A method for fast clock locking in a master-slave clock switching system according to claim 3, wherein said applying said feedback signal to said master clock signal or said slave clock signal via a phase locked loop to phase said master clock signal and said slave clock signal comprises the steps of:
inputting the main clock feedback signal into the main phase-locked loop, wherein the main phase-locked loop is used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
and inputting the standby clock feedback signal into the standby phase-locked loop, wherein the standby phase-locked loop is used for adjusting the phase of the standby clock division signal according to the standby clock feedback signal to be consistent with the phase of the standby clock division signal.
6. The master-slave clock switching fast clock locking method according to claim 3, further comprising the steps of:
taking the signal output by the main TDC as a final output signal of the main clock signal;
and taking the signal output by the standby TDC as a final output signal of the standby clock signal.
7. The master-slave clock switching fast clock locking method according to claim 6, further comprising the steps of: and carrying out frequency division processing on the final output signal.
8. A master-slave clock switching fast clock locking apparatus, comprising:
the main and standby phase adjustment modules are used for respectively dividing the main clock signal and the standby clock signal into two parts and then carrying out phase discrimination processing on one main clock signal and one standby clock signal to obtain a feedback signal;
and the phase feedback processing module is used for enabling the feedback signal to act on the main clock signal or the standby clock signal through a phase-locked loop so as to enable the phases of the main clock signal and the standby clock signal to be consistent.
9. A master-slave clock switching fast clock locking system, comprising:
the main phase-locked loop is used for dividing the main clock signal into two parts to obtain two main clock divided signals with the same frequency and phase;
a standby phase-locked loop for dividing the standby clock signal into two to obtain two standby clock divided signals with the same frequency and phase;
the main phase adjustment module is used for carrying out phase discrimination processing on a main clock sub-signal and a standby clock sub-signal through a main TDC to output a main clock feedback signal;
the standby phase adjustment module is used for carrying out phase discrimination processing on the other main clock division signal and the other standby clock division signal through the standby TDC to output a standby clock feedback signal;
the main phase-locked loop is also used for adjusting the phase of the main clock sub-signal to be consistent with the main clock sub-signal according to the main clock feedback signal;
the standby phase-locked loop is also used for adjusting the phase of the standby clock division signal to be consistent with the standby clock division signal according to the standby clock feedback signal.
10. The master-slave clock switching fast clock locking system of claim 9,
the main phase adjustment module is further configured to output a main clock feedback signal capable of reducing a phase difference of the main clock sub-signal and the standby clock sub-signal according to the phase difference;
the standby phase adjustment module is further configured to output a standby clock feedback signal capable of reducing a phase difference of the other main clock division signal and the other standby clock division signal according to the phase difference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310316731.6A CN116366197A (en) | 2023-03-28 | 2023-03-28 | Method, device and system for locking fast clock in switching between main clock and standby clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310316731.6A CN116366197A (en) | 2023-03-28 | 2023-03-28 | Method, device and system for locking fast clock in switching between main clock and standby clock |
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| Publication Number | Publication Date |
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| CN116366197A true CN116366197A (en) | 2023-06-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310316731.6A Pending CN116366197A (en) | 2023-03-28 | 2023-03-28 | Method, device and system for locking fast clock in switching between main clock and standby clock |
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| Country | Link |
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| CN (1) | CN116366197A (en) |
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