WO2023004576A1

WO2023004576A1 - Clock synchronization method, apparatus and system, and chip

Info

Publication number: WO2023004576A1
Application number: PCT/CN2021/108624
Authority: WO
Inventors: 章成旻
Original assignee: 华为技术有限公司
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2023-02-02
Also published as: CN117716644A

Abstract

Disclosed in the present application are a clock synchronization method, apparatus and system, and a chip. The method comprises: receiving pulse-per-second signals and a clock synchronization protocol message, wherein timestamp information can be obtained by means of parsing the clock synchronization protocol; performing frequency division on a first reference clock signal by using a fractional frequency division phase-locked loop circuit, so as to obtain a plurality of first clock sub-signals; sampling the pulse-per-second signals by using the plurality of first clock sub-signals, so as to obtain a plurality of first sampled signals; taking first hop edges of the first sampled signals as sampling points, and determining a plurality of first sampling values of the plurality of first sampled signals at the sampling points; and realizing clock synchronization on the basis of the timestamp information and the plurality of first sampling values. In the present application, after frequency division is performed on a first reference clock signal by using a fractional frequency division phase-locked loop circuit, pulse-per-second signals can be sampled with a higher precision by using a plurality of first clock sub-signals, such that the sampling precision can be improved, thereby further improving the accuracy of clock synchronization.

Description

A clock synchronization method, device, system and chip

technical field

The present application relates to the technical field of distributed networks, in particular to a clock synchronization method, device, system and chip.

Background technique

The clock synchronization system can accurately synchronize the real-time clocks of each node in the distributed network communication to adopt the clock synchronization system of the standard for a precision clock synchronization protocol for networked measurement and control systems (IEEE 1588) As an example, in this clock synchronization system, each node of the distributed network is equipped with a clock module and a processing module, wherein the processing module is used to process related protocols of IEEE 1588 messages and collect time stamps, and convert the time stamps to It is sent to the clock module, and the clock module is used to calculate the clock information based on the time stamp sent by the processing module, and then adjust the local real-time clock to realize the clock synchronization of each node. The clock module periodically sends time stamp information and pulse per second (PPS) information to the processing module, so that the real-time clock of the processing module is synchronized with the clock module.

The IEEE 1588 synchronization system has very high requirements for sampling accuracy. Currently, the sampling accuracy required is at the nanosecond level. Among them, the sampling accuracy of second pulse information is an important factor affecting the accuracy of the entire IEEE 1588 synchronization system. The sampling accuracy of the second pulse information is completely dependent on the clock frequency of the sampling clock, that is, the sampling accuracy of the second pulse information can only be improved by increasing the clock frequency of the sampling clock. For example, to meet the accuracy requirements of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1 GHz is required to make the sampling accuracy of the second pulse information reach 1 ns. However, under the existing clock manufacturing process, the cost of implementing a 1GHz clock is too high, but the sampling accuracy of a clock with a lower cost process is difficult to meet the accuracy requirements of the IEEE 1588 synchronization system. In view of this, when the clock frequency of the sampling clock is low, how to ensure a higher precision sampling requirement is urgently to be solved by those skilled in the art.

Contents of the invention

The present application provides a clock synchronization method, device, system and chip, which can ensure higher precision sampling when the clock frequency of the sampling clock is low.

In the first aspect, the present application provides a clock synchronization method, including: receiving a second pulse signal and a clock synchronization protocol message, analyzing the clock synchronization protocol message to obtain timestamp information; The clock signal is frequency-divided to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same; the second pulse signal is sampled by using a plurality of first sub-clock signals to obtain a plurality of first sampling signals ; Taking the first jump edge of each first sampling signal as the sampling point, determine multiple first sampling values of the multiple first sampling signals at the sampling point; perform clock synchronization according to the timestamp information and the multiple first sampling values .

A clock synchronization method provided in the embodiment of the present application uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain N first sub-clock signals clk1~clkN; using the above-mentioned first sub-clock signal The second pulse signal is sampled to obtain first sampling signals Q1-QN. According to the first jump edge of different first sampling signals Q1~QN as the sampling point, determine the multiple first sampling values of the multiple first sampling signals at the sampling point; according to the multiple first sampling values, it can be more accurately determined The jump edge position of the second pulse signal, so that the current time can be determined more accurately. Therefore, compared with the prior art, only one first reference clock signal is used to sample the second pulse signal, the present application uses N first sub-clock signals , the sampling precision can be reduced to 1/N clock period of the first reference clock signal, and the sampling precision can be increased to N times of the original.

In some possible implementation manners, using multiple first sub-clock signals to sample the second pulse signal includes: using multiple first sub-clock signals to sample the second pulse signal N times, and determining N sets of sampling results; wherein, N is a positive integer; each group of sampling results includes multiple first sampling signals.

In practical applications, the phases of multiple first sub-clock signals obtained by frequency division of the first reference clock signal may drift or be inaccurate. After sampling the second pulse signal N times, if multiple first sub-clock signals If the phase of the clock signal does not drift, then among the N sets of sampling results, each set of sampling results is basically the same. If the phases of multiple first sub-clock signals drift, the sampling average can be determined by the total number of sampling results N and multiple sets of sampling results To avoid the problem that the sampling accuracy of the second pulse information is affected by the drift or inaccuracy of multiple first sub-clock signals obtained after frequency division.

As a possible implementation manner, using a fractional frequency-division phase-locked loop circuit to divide the first reference clock signal to obtain a plurality of first sub-clock signals includes: using a fractional frequency-division phase-locked loop circuit to divide the first reference clock signal The frequency of the signal is divided by four to obtain four first sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.

As a possible implementation manner, the fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider and a second frequency divider; the inverter is used to: generate and A signal with the opposite phase of the first reference clock signal; the first frequency divider is configured to divide the frequency of the first reference clock signal by two to obtain two first sub-clock signals, wherein the starting point of the two first sub-clock signals is The initial phases are respectively 0° and 180°; the second frequency divider is used to divide the frequency of the signal opposite to the phase of the first reference clock signal by two to obtain two first sub-clock signals, wherein the two first The starting phases of the sub clock signals are 90° and 270° respectively.

In practical applications, after the first reference clock signal is input to the inverter in the fractional frequency-division phase-locked loop, its 0° and 180° phase clock signals are obtained, and the 0° and 180° phase clock signals are respectively subjected to the first frequency division The second frequency divider and the second frequency divider obtain the first sub-clock signals with initial phases of 0°, 90°, 180° and 270° respectively. In addition, the structure of the fractional frequency division phase-locked loop circuit of the present application is not limited thereto. The inverter in the fractional frequency division phase-locked loop circuit can also be a phase separation circuit, and the phase separation circuit can also generate A signal that is in phase opposite to the first reference clock signal.

As a possible implementation manner, the first jump edge is a rising edge transitioning from a low level to a high level and/or a falling edge transitioning from a high level to a low level. The second pulse signal is sampled by using a plurality of first sub-clock signals, including: sampling the second pulse signal by using the second jump edge of a plurality of first sub-clock signals, and the second jump edge is a transition from a low level to Rising edge high, and/or falling edge transition from high to low.

As a possible implementation manner, after the multiple first sub-clock signals are obtained, the method further includes: generating a first multi-phase clock signal according to the multiple first sub-clock signals, and using the first multi-phase clock signal to compare the second pulse signal Take a sample.

As a possible implementation manner, determining the time stamp information according to a plurality of second sampling values and the local time includes: when a sampling value of a set size appears for the first time among the plurality of second sampling values, according to the pulse period of the second pulse signal As well as the local time, determine the timestamp information.

Because in a distributed network with high precision requirements, the sampling error stipulated in the clock synchronization protocol message used will also be low. As a possible implementation manner, the sampling error stipulated in the clock synchronization protocol message is not greater than ±0.5 ns.

If it is necessary to meet the accuracy requirements of the IEEE 1588 synchronization system, a sampling clock with a clock frequency of 1GHz is required to sample the second pulse signal. However, under the existing clock manufacturing process, the cost of producing a 1GHz clock is too high, and it is relatively common at present. The clock frequency is still a clock below 500MHz. In this aspect, the clock synchronization method provided by this application can also be completed by using a clock below 500MHz, which is relatively common in clock frequency and has relatively low requirements on clock manufacturing technology. As a possibility In an implementation manner, the clock frequency of the first reference clock signal is not higher than 500MHz.

In the second aspect, the present application provides a clock synchronization method, which is applied to a master synchronization device, and uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain multiple second sub-clock signals; wherein, each The period of the second sub-clock signal is the same; Utilize a plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; take the first jump edge of each second sampling signal as the sampling point, determine how many A plurality of second sampling values of a second sampling signal at the sampling point; determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, and the clock synchronization protocol message carries time stamp information. Wherein, the technical effect of the corresponding solution in the second aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail.

As a possible implementation manner, using multiple second sub-clock signals to sample the second pulse signal includes: using multiple second sub-clock signals to sample the second pulse signal N times, and determining N sets of sampling results; wherein, N is a positive integer; each group of sampling results includes multiple second sampling signals.

As a possible implementation manner, using a fractional frequency-division phase-locked loop circuit to divide the second reference clock signal to obtain a plurality of second sub-clock signals includes: using a fractional frequency-division phase-locked loop circuit to divide the second reference clock signal The frequency of the signal is divided by four to obtain four second sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.

As a possible implementation manner, the fractional frequency division phase-locked loop circuit includes: an inverter, a first frequency divider and a second frequency divider; the inverter is used to: generate and The signal with the opposite phase of the second reference clock signal; the first frequency divider is used to divide the frequency of the second reference clock signal by two to obtain two first sub-clock signals, wherein the starting point of the two first sub-clock signals The initial phases are respectively 0° and 180°; the second frequency divider is used to divide the frequency of the signal opposite to the phase of the second reference clock signal by two to obtain two first sub-clock signals, wherein the two first The starting phases of the sub clock signals are 90° and 270° respectively.

As a possible implementation manner, the first jump edge is a rising edge transitioning from a low level to a high level and/or a falling edge transitioning from a high level to a low level.

As a possible implementation manner, using multiple first sub-clock signals to sample the second pulse signal includes: using the second jump edges of the multiple first sub-clock signals to sample the second pulse signal, and the second jump edge is the rising edge from low to high, and/or the falling edge from high to low.

As a possible implementation manner, after the multiple first sub-clock signals are obtained, the method further includes: generating a second multi-phase clock signal according to the multiple second sub-clock signals, and using the second multi-phase clock signal to compare the second pulse signal Take a sample.

As a possible implementation manner, the sampling error stipulated in the clock synchronization protocol message is not greater than ±0.5 ns.

As a possible implementation manner, the clock frequency of the first reference clock signal is not higher than 500 MHz.

In the third aspect, the present application also provides a clock synchronization device, including a message and pulse-per-second signal receiving module, used to: receive the pulse-second signal and a clock synchronization protocol message, and analyze the clock synchronization protocol message to obtain time stamp information; The frequency division module is used to: use the fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same; the sampling module, It is used to: use a plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals; the sampling value determination module is used to: take the first jump edge of each first sampling signal as a sampling point, A plurality of first sampling values of the plurality of first sampling signals at the sampling point are determined; a clock synchronization module is configured to perform clock synchronization according to the time stamp information and the plurality of first sampling values. Among them, the technical effect of the corresponding solution in the third aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail.

In a fourth aspect, the present application also provides a clock synchronization device, including a frequency division module, configured to: use a fractional frequency division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain multiple second sub-clock signals; Wherein, the period of each second sub-clock signal is the same; the sampling module is used to: use a plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; the sampling value determination module is used to: Taking the first jump edge of each second sampling signal as the sampling point, determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point; the message generation module is used for: according to the plurality of second sampling values And the local time determines the time stamp information, sends the clock synchronization protocol message, and the clock synchronization protocol message carries the time stamp information. Wherein, the technical effect of the corresponding solution in the fourth aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail.

In a fifth aspect, the present application provides a chip, including: a processor and a memory, the processor is connected to the memory, and an instruction program is stored in the memory, and the processor, under the control of the instruction program, is used to perform the following steps: obtain the second pulse signal and a clock synchronization protocol message, analyzing the clock synchronization protocol message to obtain time stamp information; using a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, each The period of a sub-clock signal is the same; Utilize a plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals; take the first jump edge of each first sampling signal as a sampling point to determine a plurality of A plurality of first sampling values of the first sampling signal at the sampling point; clock synchronization is performed according to the time stamp information and the plurality of first sampling values. The technical effect of the corresponding solution in the fifth aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect, and the repeated parts will not be described in detail.

In a sixth aspect, the present application provides a chip, including: a processor and a memory, the processor is connected to the memory, and an instruction program is stored in the memory, and the processor is used to perform the following steps under the control of the instruction program: using fractional frequency division The phase-locked loop circuit divides the frequency of the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same; the second pulse signal is sampled by using a plurality of second sub-clock signals , to obtain a plurality of second sampling signals; taking the first jump edge of each second sampling signal as a sampling point, determine a plurality of second sampling values of a plurality of second sampling signals at the sampling point; according to a plurality of second sampling The value and the local time determine the time stamp information, and generate a clock synchronization protocol message, and the clock synchronization protocol message carries the time stamp information. The technical effect of the corresponding solution in the sixth aspect can refer to the technical effect that can be obtained by the corresponding solution in the second aspect, and the repeated parts will not be described in detail.

In the seventh aspect, the present application provides a clock synchronization system. The clock synchronization system includes: a second frequency division module, which is used to divide the frequency of the second reference clock signal by a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clocks. Clock signal; wherein, the period of each second sub-clock signal is the same; the second sampling module is used to sample the second pulse signal by using a plurality of second sub-clock signals to obtain a plurality of second sampling signals; the second sampling value The determination module is used to take the first jump edge of each second sampling signal as a sampling point to determine a plurality of second sampling values of a plurality of second sampling signals at the sampling point; The second sampling value and the local time determine the time stamp information, and send a clock synchronization protocol message to the message and second pulse signal receiving module, and the clock synchronization protocol message carries time stamp information; the message and second pulse signal receiving module is used to receive The second pulse signal sent by the message generation module and the clock synchronization protocol message are parsed to obtain the time stamp information; the first frequency division module is used to use the fractional frequency division phase-locked loop circuit to process the first reference clock signal frequency division to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same; the first sampling module is used to sample the second pulse signal by using a plurality of first sub-clock signals to obtain a plurality of The first sampled signal; the first sampled value determination module, which is used to take the first jump edge of each first sampled signal as the sampling point to determine a plurality of first sampled values of the multiple first sampled signals at the sampling point; clock A synchronization module, configured to perform clock synchronization according to time stamp information and multiple first sampling values. The technical effect of the corresponding solution in the seventh aspect can refer to the technical effect that can be obtained by the corresponding solution in the first aspect and the second aspect, and the repeated parts will not be described in detail.

These or other aspects of the present application will be more concise and understandable in the description of the following embodiments.

Description of drawings

FIG. 1 is a first schematic flow diagram of a clock synchronization method;

FIG. 2 is a timing diagram corresponding to a clock synchronization method;

Fig. 3 is a structural schematic diagram of a fractional frequency division phase-locked loop circuit;

FIG. 4 is a second schematic flow diagram of a clock synchronization method;

Fig. 5 is a schematic diagram of a clock synchronization device;

Fig. 6 is a schematic diagram of another clock synchronization device.

Detailed ways

Embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

In order to make the purpose, technical solution and advantages of the application clearer, the application will be further described in detail below in conjunction with the accompanying drawings. It should be noted that in this specification, similar numerals and letters denote similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be identified in subsequent drawings. for further definition and explanation.

In the description of the embodiments of the present application, "and/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which may mean: A exists alone, A and B exist simultaneously, and There are three cases of B. The character "/" generally indicates that the contextual objects are an "or" relationship. The at least one involved in this application refers to one or more; a plurality refers to two or more than two. In addition, it should be understood that in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or imply order.

In a distributed network, one of the multiple nodes acts as a master synchronization device (master), and the remaining nodes act as slave synchronization devices (slave). The master synchronization device can synchronize the reference time to all slave synchronization devices. The master synchronization device sends an IEEE 1588 protocol message, and the slave synchronization device can collect time stamp information according to the received protocol message. The real-time clock is adjusted so that the clock module of the slave synchronization device is synchronized with the time of the master synchronization device. Then, the slave synchronization device sends the time stamp information and the pulse-per-second information to the processing module, and the slave synchronization device adjusts its own real-time clock according to the time stamp information and the pulse-per-second information, and finally realizes clock synchronization.

However, in some distributed networks that require high precision, the sampling error specified in the clock synchronization protocol message used will be relatively low. For example, to meet the accuracy requirements of the IEEE 1588 synchronous system, a sampling clock with a clock frequency of 1 GHz is required to sample the second pulse signal in order to achieve a sampling accuracy of 1 ns. However, under the existing clock manufacturing process, the cost of producing a 1GHz clock is too high, and the clock frequency is less than 500MHz, but the sampling accuracy of the clock at a lower cost is difficult to meet the requirements of the IEEE 1588 synchronization system. Accuracy requirements. In view of this, when the clock frequency of the sampling clock used is low, how to ensure a higher precision sampling requirement is an urgent problem to be solved by those skilled in the art.

Figure 1 is a flow chart of the clock synchronization method provided by the embodiment of the application, and Figure 2 is a timing diagram corresponding to the clock synchronization method provided by the implementation of the application, in combination with Figure 1 and Figure 2, the clock synchronization method in the embodiment of the application is applied to When syncing from a device, you can include methods like:

S101: Receive a second pulse signal and a clock synchronization protocol message, and analyze the clock synchronization protocol message to obtain time stamp information.

Among them, the clock synchronization protocol message may include: a high-precision time synchronization protocol (precision time protocol, PTP) message, a generalized precision time protocol (generalized precision time protocol, 802.1AS) message, a sync synchronization message, and a follow_up following message , delay_req delay request message or delay_resp delay response message, etc. Among them, the sampling error stipulated in the clock synchronization protocol message may not be greater than ±0.5ns. Here, a PTP type message is used as an example, but it does not constitute a limitation to this application. Those skilled in the art should know that any All clock synchronization protocols (not greater than ±0.5ns) can be applied in this application, and are not limited here. The second pulse signal can be generated by an external clock device, and can also be sent together with the master synchronization device.

The time stamp information master synchronization device is determined based on the current time, and the current time is not limited to universal time coordinated (UTC) time and global positioning system (global positioning system, GPS) time, etc., which are not specifically limited here.

S102: Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals. The period of each first sub-clock signal is the same.

Wherein, the first reference clock signal may be generated by an internal clock, optionally, the internal clock may include: a crystal oscillator, a frequency multiplication circuit, a phase detector, a clock pulse circuit, an input digital-to-analog converter, a voltage-controlled oscillator, etc. . For example, the crystal oscillator can generate a clock signal with a reference frequency, and the reference frequency is related to the specific structure of the crystal oscillator; the frequency multiplication circuit is used to perform frequency multiplication processing on the reference frequency clock signal; The pulse circuit converts the phase detection signal into a clock pulse signal for the phase detection signal, and inputs the digital-analog converter to convert the clock pulse signal into an analog clock pulse signal, and the voltage-controlled oscillator outputs the first reference clock signal according to the analog clock pulse signal. The above-mentioned processing process of the clock signal of the reference frequency is only an example, and the device connection relationship in the internal clock is not limited. The purpose is to generate a clock signal of a specific frequency. The specific generation method is not limited, and those skilled in the art should know .

The existing frequency division circuit can use a delay loop (time to digital converter, TDC) to divide the frequency of the first reference clock signal. If TDC is used, the timing time after frequency division will be completely determined by the timing chip (cell), but the timing chip (cell) jitter and high uncertainty, and is greatly affected by process voltage temperature (precess voltage temperature, PVT) conditions, so the reliability of frequency division using TDC is low, and a delay jitter of up to 1.68% will be generated, and due to The structure of its delay loop will lead to the accumulation of delay jitter, resulting in greater errors.

However, this application uses analog devices to form a fractional frequency division phase-locked loop circuit, which is not affected by process angle deviation and temperature. A complex closed-loop structure is used to meet the requirements of high-speed clock scenarios, which has the advantages of low delay and high precision.

Continuing to refer to Fig. 2, as a possible implementation manner, the first reference clock signal is divided by four using a fractional frequency-division phase-locked loop circuit to obtain four first sub-clock signals; wherein, after frequency division, adjacent The phase difference between the two first sub-clock signals is 90°. In Fig. 2, a fractional frequency-division phase-locked loop circuit is used to divide the frequency of the first reference clock signal by four, thereby obtaining four first sub-clock signals: the first sub-clock signal clk1, the first sub-clock signal clk2, the first sub-clock The signal clk3 and the first sub-clock signal clk4; wherein, the phase difference between each adjacent clock signal is 90°. It should be noted that the phase difference between adjacent clock signals in the embodiment of the present application is 90° means, for example, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 may have a certain deviation range Or, in other words, the phase difference between the first sub-clock signal clk1 and the first sub-clock signal clk2 is approximately 90°, and each first sub-clock needs to be kept in sync. As a possible implementation manner, the clock frequency of the first reference clock signal is not higher than 500 MHz. Exemplarily, for the purpose of improving the sampling accuracy, the number of generated first sub-clock signals may be related to the clock frequency of the first reference clock signal, for example, when the clock frequency of the first reference clock signal is 500MHz, fractional frequency division The phase-locked loop circuit can divide the frequency of the first reference clock signal by four to obtain four first sub-clock signals, and when the clock frequency of the first reference clock signal is 250MHz, the fractional frequency-division phase-locked loop circuit can divide the first sub-clock signal A reference clock signal is divided by eight to obtain eight first sub-clock signals.

S103: Using multiple first sub-clock signals to sample the second pulse signal to obtain multiple first sampling signals.

It should be noted that, in the embodiment of the present application, the first sub-clock signal can use the second jump edge to sample the second pulse signal. For example, the second jump edge can be a rising edge, that is, from a low level (0) Jumping to the transition edge of high level (1), of course, the second transition edge can also be a falling edge, that is, the transition edge from high level (1) to low level (0), in order For ease of description, in this application, the second transition edge is taken as an example for illustration. Exemplarily, taking rising edge sampling as an example, after the second pulse signal is sampled by using the first sub-clock signal clk1, the first sampling signal Q1 can be obtained.

S104: Using the first jump edge of each first sampling signal as a sampling point, determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point.

Taking the first transition edge of the first sampling signal Q1 as the sampling point A, the first sampling value of the first sampling signal Q1 at the sampling point A is determined. It should be noted that, in the embodiments of the present application, the sampling point refers to the first transition edge of the first sampling signal, wherein the first transition edge is the transition edge from the first value to the second value, For example, the first transition edge can be a rising edge, that is, a transition edge that transitions from a low level (0) to a high level (1). Of course, the first transition edge can also be a falling edge, that is, a transition from a high level to For the convenience of description, the transition edge from the level (1) to the low level (0) is described in this application by taking the first transition edge as a rising edge as an example.

S105: Perform clock synchronization according to the time stamp information and multiple first sampling values.

After the multiple first sampling values are obtained, the current time is determined according to the sampling value at which the updated time is first collected among the multiple first sampling values and the time stamp information, so as to realize clock synchronization.

In a distributed network, each device may include a clock synchronization module and a processing module, and the above steps S101 to S105 may be performed in the processing module, that is, the clock synchronization module periodically receives time stamp information from the master synchronization device and second pulse information, and periodically send time stamp information and second pulse information to the processing module. After receiving the time stamp information and second pulse information, the processing module executes the above steps S101 to step S105, so that the master synchronization device and the slave synchronization Devices implement clock synchronization.

As a possible implementation, clock synchronization based on time stamp information and multiple first sampling values may be: when a sampling value of a set size appears for the first time in multiple first sampling values, according to the pulse of the second pulse signal Period and timestamp information to determine the current time. Exemplarily, continuing to refer to FIG. 2, the embodiment of the present application can obtain four first sub-clock signals clk1-clk4 by dividing the frequency of the first reference clock by four; The sampling of the signal can obtain the first sampling signals Q1-Q4, and obtain a plurality of first sampling values based on the first transition edges of the first sampling signals Q1-Q4. For example, the pulse period of the second pulse signal is 1s, and the time indicated by the time stamp information is 10:00:00. When a sampling value with a sampling value of 1 appears in multiple first sampling values, the current time change is determined from the synchronization device is 10:00:01. By using the above method, the edge position of the second pulse signal can be determined more accurately, so that the current time can be determined more accurately.

In addition, since the clock synchronization protocol message takes a certain amount of time to be sent from the master synchronization device to the slave synchronization device, when calculating the real-time time in this embodiment of the application, the sending time can be used as the compensation time, which is pre-added to the value carried by the time stamp. In the time, and then perform clock synchronization after compensating the sending time; and, because of the different ways of sending the clock synchronization protocol message, or the distance between the master synchronization device and the slave synchronization device, the corresponding sending time is also different.

Exemplarily, the clock synchronization method provided by the embodiment of the present application uses a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain the first sub-clock signals clk1-clk4; wherein, each adjacent clock signal The phase difference of each is 90°, and the second pulse signal is sampled by using the above-mentioned first sub-clock signal to obtain the first sampling signals Q1-Q4. According to the first sampling values corresponding to different first sampling signals Q1-Q4, therefore, compared with the prior art, only one first reference clock signal is used to sample the second pulse signal, the present application uses N first sub-clock signals , the sampling precision can be reduced to 1/N clock period of the first reference clock signal, and the sampling precision can be increased to N times of the original.

In actual scenarios, the phases of multiple first sub-clock signals obtained by frequency division of the first reference clock signal may drift or be inaccurate. As a possible implementation, the above-mentioned clock The synchronization method may further include: using a plurality of first sub-clock signals to sample the second pulse signal N times to determine N groups of sampling results; wherein, N is a positive integer; each group of sampling results includes a plurality of first sampling signals.

That is to say, in the embodiment of the present application, the above steps S103-S105 are executed N times, that is, after the second pulse signal is sampled N times by using a plurality of first sub-clock signals, if the phases of the plurality of first sub-clock signals do not drift, then Among the N groups of sampling results, each group of sampling results is basically the same. If the phases of multiple first sub-clock signals drift, the sampling average value can be determined by the total amount of sampling results N and multiple groups of sampling results, so as to avoid obtaining The drift or inaccuracy of multiple first sub-clock signals affects the sampling accuracy of the second pulse information.

Fig. 3 is a structural schematic diagram of a fractional frequency division PLL circuit; referring to Fig. 3, the first reference clock signal is first input into the inverter in the fractional frequency division PLL to obtain its 0° and 180° phase clocks CLK0 and CLK1, CLK0 passes through the first frequency divider to obtain CLK00 and CLK01 with a frequency of 1/2 and a phase of 0° and 180°; CLK1 passes through the second frequency divider to obtain a frequency of 1/2 2. CLK10 and CLK11 with phases of 90° and 270°.

In addition, the structure of the fractional frequency division phase-locked loop circuit of the present application is not limited thereto. The inverter in the fractional frequency division phase-locked loop circuit can also be a phase separation circuit, and the phase separation circuit can also be based on the first reference clock The signal generates 0° and 180° phase clocks CLK0 and CLK1. Compared with the inverter, the delay error of the phase separation circuit is smaller, and its value is generally less than 3ps, which is more suitable for the high-precision clock synchronization protocol scenario of this application.

As a possible implementation manner, after the multiple first sub-clock signals are obtained, the method further includes:

A first multi-phase clock signal is generated according to the plurality of first sub-clock signals, and the second pulse signal is sampled by using the first multi-phase clock signal.

Wherein, the fractional frequency-division phase-locked loop circuit may further include: an AND gate circuit for synthesizing a plurality of first sub-clock signals into a first multi-phase clock. Exemplarily, if CLK00, CLK01, CLK10, and CLK11 of the above embodiment are input to the AND gate circuit, the AND gate circuit can obtain a frequency half of the first reference clock signal, a duty cycle of 25%, and a starting phase of 0 °, 90°, 180° and 270° four-phase clock.

Figure 4 is a flow chart of the clock synchronization method provided by the embodiment of the present application. The clock synchronization method in the embodiment of the present application is applied to the master synchronization device, which may include:

S401: Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same;

S402: Use the multiple second sub-clock signals to sample the second pulse signal to obtain multiple second sampling signals;

S403: Using the first jump edge of each second sampling signal as a sampling point, determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point;

S404: Determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information. For the possible implementation manners and beneficial effects of the embodiment of the present application, refer to steps S101 to S105 in the above embodiment, and the repetition will not be repeated, and those skilled in the art should know it.

Referring to Fig. 5, the present application provides a clock synchronization device 500, which device includes: message and second pulse signal receiving module 501, used for: receiving second pulse signal and clock synchronization protocol message, and analyzing the clock synchronization protocol The time stamp information is obtained from the message; the frequency division module 502 is configured to: use a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, each first sub-clock The period of the signal is the same; the sampling module 503 is configured to: use the plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals; the sampling value determination module 504 is configured to: The first jump edge of the first sampling signal is a sampling point, and a plurality of first sampling values of the plurality of first sampling signals at the sampling point are determined; the clock synchronization module 505 is configured to: according to the time stamp Clock synchronization is performed on the information and the plurality of first sampled values.

Referring to FIG. 6, the present application also provides a clock synchronization device 600, which includes: a frequency division module 601, configured to: use a fractional frequency division phase-locked loop circuit to divide the second reference clock signal to obtain multiple The second sub-clock signal; wherein, the period of each second sub-clock signal is the same; the sampling module 602 is configured to: use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second Sampling signal; sampling value determination module 603, configured to: take the first jump edge of each second sampling signal as a sampling point, and determine multiple second sampling values of the multiple second sampling signals at the sampling point ; A message generating module 604, configured to: determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.

It should be noted that the division of modules in the embodiment of the present application is schematic, and is only a division of turbine functions. In actual implementation, there may be other division methods. In the example of this application, each functional module can be integrated in In one processing module, each module may exist independently, or two or more units may be integrated into one unit. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software function modules.

The present application also provides a clock synchronization system. The clock synchronization system includes: a second frequency division module, which is used to divide the frequency of the second reference clock signal by using a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clocks signal; wherein, the period of each second sub-clock signal is the same; the second sampling module is used to use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals; Two sampling value determination modules, used to take the first jump edge of each second sampling signal as a sampling point to determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point; message generation A module, configured to determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message to the message and second pulse signal receiving module, the clock synchronization protocol message carrying the time Stamp information; message and second pulse signal receiving module, used to receive the second pulse signal and clock synchronization protocol message sent by the message generation module, and analyze the clock synchronization protocol message to obtain time stamp information; the second frequency division The module is used to divide the frequency of the first reference clock signal by a fractional frequency-division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same; the second sampling module uses The second pulse signal is sampled by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; the second sampling value determination module is configured to use the first jump edge of each first sampling signal as A sampling point, determining a plurality of first sampling values of the plurality of first sampling signals at the sampling point; a clock synchronization module, configured to perform clock synchronization according to the timestamp information and the plurality of first sampling values .

The present application also provides a chip, a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to perform the following steps under the control of the instruction program : Obtain a second pulse signal and a clock synchronization protocol message, analyze the clock synchronization protocol message to obtain time stamp information; use a fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain multiple first sub-clocks signal; wherein, the period of each first sub-clock signal is the same; the second pulse signal is sampled by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals; The first jump edge is a sampling point, and determining a plurality of first sampling values of the plurality of first sampling signals at the sampling point; performing clock synchronization according to the time stamp information and the plurality of first sampling values.

The present application also provides a chip, including: a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to execute The following steps: use the fractional frequency division phase-locked loop circuit to divide the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same; using the plurality of second sub-clock signals The sub-clock signal samples the second pulse signal to obtain a plurality of second sampling signals; taking the first jump edge of each second sampling signal as a sampling point, and determining that the plurality of second sampling signals are at the sampling point multiple second sampled values at the same time; determine time stamp information according to the multiple second sampled values and local time, and generate a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.

Based on the above embodiments, an embodiment of the present application further provides a computer program, which causes the computer to execute the clock synchronization method provided in the above embodiments when the computer program is run on a computer.

Based on the above embodiments, the embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored in the computer-readable storage medium. When the computer program is executed by a computer, the computer executes the clock synchronization provided by the above embodiments. method.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

Apparently, those skilled in the art can make various changes and modifications to this application without departing from the protection scope of this application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A clock synchronization method applied to a slave synchronization device, wherein the method comprises:

receiving the second pulse signal and the clock synchronization protocol message, and analyzing the clock synchronization protocol message to obtain timestamp information;

Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;

sampling the second pulse signal by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

Using the first jump edge of each first sampling signal as a sampling point, determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point;

Clock synchronization is performed according to the time stamp information and the plurality of first sampling values.
The method according to claim 1, wherein the sampling of the second pulse signal by using the plurality of first sub-clock signals comprises:

The second pulse signal is sampled N times by using the plurality of first sub-clock signals to determine N groups of sampling results; wherein, the N is a positive integer; each group of the sampling results includes the plurality of first sub-clock signals sample signal.
The method according to claim 1 or 2, wherein the first reference clock signal is frequency-divided by a fractional frequency-division PLL circuit to obtain a plurality of first sub-clock signals, including:

The first reference clock signal is divided by four by using a fractional frequency-division phase-locked loop circuit to obtain four first sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
The method according to claim 3, wherein the fractional frequency division PLL circuit comprises: an inverter, a first frequency divider and a second frequency divider;

The inverter is configured to: generate a signal with an opposite phase to the first reference clock signal based on the first reference clock signal;

The first frequency divider is configured to divide the frequency of the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 0° and 180° respectively. °;

The second frequency divider is configured to divide the frequency of the signal opposite to the phase of the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively for 90° and 270°.
The method according to any one of claims 1-4, wherein the first jump edge is a rising edge from a low level to a high level and/or a transition from a high level to a low level the falling edge of .
The method according to any one of claims 1-5, wherein the sampling of the second pulse signal by using the plurality of first sub-clock signals comprises:

The second pulse signal is sampled by using the second jump edge of the plurality of first sub-clock signals, the second jump edge is a rising edge from a low level to a high level, and/or from Falling edge from high level to low level.
The method according to any one of claims 1-6, wherein after said obtaining a plurality of first sub-clock signals, said method further comprises:

A first multi-phase clock signal is generated according to the plurality of first sub-clock signals, and the second pulse signal is sampled by using the first multi-phase clock signal.
The method according to any one of claims 1-7, wherein the performing clock synchronization according to the time stamp information and the plurality of first sampling values comprises:

When a sampling value of a set size appears for the first time among the plurality of first sampling values, the current time is determined according to the pulse period of the second pulse signal and the time stamp information.
The method according to any one of claims 1-8, characterized in that the sampling error stipulated in the clock synchronization protocol message is not greater than ±0.5 ns.
The method according to any one of claims 1-9, wherein the clock frequency of the first reference clock signal is not higher than 500MHz.
A clock synchronization method applied to a master synchronization device, characterized in that the method comprises:

Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same;

sampling the second pulse signal by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

Using the first jump edge of each second sampling signal as a sampling point, determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point;

Determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.
The method according to claim 11, wherein the sampling of the second pulse signal by using the plurality of second sub-clock signals comprises:

The second pulse signal is sampled N times by using the plurality of second sub-clock signals to determine N groups of sampling results; wherein, the N is a positive integer; each group of the sampling results includes the plurality of second sub-clock signals sample signal.
The method according to claim 11 or 12, wherein the second reference clock signal is frequency-divided by a fractional frequency-division phase-locked loop circuit to obtain a plurality of second sub-clock signals, including:

The second reference clock signal is divided by four by using a fractional frequency-division phase-locked loop circuit to obtain four second sub-clock signals; wherein, after frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
The method according to claim 13, wherein the fractional frequency division PLL circuit comprises: an inverter, a first frequency divider and a second frequency divider;

The inverter is configured to: generate a signal with an opposite phase to the second reference clock signal based on the second reference clock signal;

The first frequency divider is configured to divide the frequency of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 0° and 180° respectively. °;

The second frequency divider is configured to divide the frequency of the signal opposite to the phase of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively for 90° and 270°.
The method according to any one of claims 11-14, wherein the first jump edge is a rising edge from a low level to a high level and/or a transition from a high level to a low level the falling edge of .
The method according to any one of claims 11-15, wherein the sampling of the second pulse signal by using the plurality of first sub-clock signals comprises:

The second pulse signal is sampled by using the second jump edge of the plurality of first sub-clock signals, the second jump edge is a rising edge from a low level to a high level, and/or from Falling edge from high level to low level.
The method according to any one of claims 11-16, wherein after said obtaining a plurality of first sub-clock signals, said method further comprises:

A second multi-phase clock signal is generated according to the plurality of second sub-clock signals, and the second pulse signal is sampled by using the second multi-phase clock signal.
The method according to any one of claims 11-17, wherein the determining time stamp information according to the plurality of second sampling values and local time includes:

When a sample value of a set size appears for the first time in the plurality of second sample values, time stamp information is determined according to the pulse period of the second pulse signal and the local time.
The method according to any one of claims 11-18, characterized in that the sampling error stipulated in the clock synchronization protocol message is not greater than ±0.5 ns.
The method according to any one of claims 11-19, wherein the clock frequency of the first reference clock signal is not higher than 500MHz.
A clock synchronization device, characterized in that the device comprises:

The message and second pulse signal receiving module is used to: receive the second pulse signal and clock synchronization protocol message, analyze the clock synchronization protocol message to obtain time stamp information;

The frequency division module is used for: using the fractional frequency division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;

A sampling module, configured to: use the plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals;

A sampling value determination module, configured to: take the first jump edge of each first sampling signal as a sampling point, and determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point;

A clock synchronization module, configured to: perform clock synchronization according to the time stamp information and the plurality of first sampling values.
The device according to claim 21, characterized in that said device comprises:

The sampling module is specifically used to: use the plurality of first sub-clock signals to sample the second pulse signal N times, and determine N sets of sampling results; wherein, the N is a positive integer; each set of The sampling result includes the plurality of first sampling signals.
The device according to claim 21 or 22, wherein the frequency division module is specifically used for:

The first reference clock signal is divided by four by using a fractional frequency-division phase-locked loop circuit to obtain four first sub-clock signals; wherein, after the frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
The device according to claim 23, wherein the fractional frequency division PLL circuit comprises: an inverter, a first frequency divider and a second frequency divider;

The inverter is configured to: generate a signal with an opposite phase to the first reference clock signal based on the first reference clock signal;

The first frequency divider is configured to divide the frequency of the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 0° and 180° respectively. °;

The second frequency divider is configured to divide the frequency of the signal opposite to the phase of the first reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively for 90° and 270°.
The device according to any one of claims 21-24, wherein the first jump edge is a rising edge from a low level to a high level and/or a transition from a high level to a low level the falling edge of .
The device according to any one of claims 21-25, wherein the sampling module is specifically used for:

The second pulse signal is sampled by using the second jump edge of the plurality of first sub-clock signals, the second jump edge is a rising edge from a low level to a high level, and/or from Falling edge from high level to low level.
The device according to any one of claims 21-26, wherein the clock synchronization device further comprises: a signal synthesis module, the signal synthesis module is configured to generate a first sub-clock signal according to the plurality of first sub-clock signals A multi-phase clock signal, using the first multi-phase clock signal to sample the second pulse signal.
The device according to any one of claims 21-27, wherein the clock synchronization module is specifically used for:

When a sampling value of a set size appears for the first time among the plurality of first sampling values, the current time is determined according to the pulse period of the second pulse signal and the time stamp information.
A clock synchronization device, characterized in that the device comprises:

The frequency dividing module is used for: dividing the frequency of the second reference clock signal by a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same;

A sampling module, configured to: use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals;

A sampling value determination module, configured to: take the first jump edge of each second sampling signal as a sampling point, and determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point;

A message generating module, configured to: determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.
The device according to claim 29, wherein the sampling module is specifically configured to: use the plurality of second sub-clock signals to sample the second pulse signal N times, and determine N sets of sampling results; wherein , the N is a positive integer; each group of the sampling results includes the plurality of second sampling signals.
The device according to claim 29 or 30, wherein the frequency division module is specifically used for:

The second reference clock signal is divided by four by using a fractional frequency-division phase-locked loop circuit to obtain four second sub-clock signals; wherein, after frequency division, the phase difference between two adjacent first sub-clock signals is 90°.
The device according to claim 31, wherein the fractional frequency division PLL circuit comprises: an inverter, a first frequency divider and a second frequency divider;

The inverter is configured to: generate a signal with an opposite phase to the second reference clock signal based on the second reference clock signal;

The first frequency divider is configured to divide the frequency of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are 0° and 180° respectively. °;

The second frequency divider is configured to divide the frequency of the signal opposite to the phase of the second reference clock signal by two to obtain two first sub-clock signals, wherein the initial phases of the two first sub-clock signals are respectively for 90° and 270°.
The device according to any one of claims 29-32, wherein the first jump edge is a rising edge from a low level to a high level and/or a transition from a high level to a low level the falling edge of .
The device according to any one of claims 29-33, wherein the sampling module is specifically used for:

The second pulse signal is sampled by using the second jump edge of the plurality of first sub-clock signals, the second jump edge is a rising edge from a low level to a high level, and/or from Falling edge from high level to low level.
The device according to any one of claims 29-34, wherein the clock synchronization device further comprises: a signal synthesis module, the signal synthesis module is configured to generate a second sub-clock signal according to the plurality of second sub-clock signals A multi-phase clock signal, using the second multi-phase clock signal to sample the second pulse signal.
The device according to any one of claims 29-35, wherein the message generating module is specifically used for:

When a sample value of a set size appears for the first time in the plurality of second sample values, time stamp information is determined according to the pulse period of the second pulse signal and the local time.
A chip, characterized in that it includes: a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to execute Follow the steps below:

Obtaining a second pulse signal and a clock synchronization protocol message, and parsing the clock synchronization protocol message to obtain timestamp information;

Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the first reference clock signal to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;

sampling the second pulse signal by using the plurality of first sub-clock signals to obtain a plurality of first sampling signals;

Using the first jump edge of each first sampling signal as a sampling point, determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point;

Clock synchronization is performed according to the time stamp information and the plurality of first sampling values.
A chip, characterized in that it includes: a processor and a memory, the processor is connected to the memory, an instruction program is stored in the memory, and the processor is used to execute Follow the steps below:

Using a fractional frequency-division phase-locked loop circuit to divide the frequency of the second reference clock signal to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same;

sampling the second pulse signal by using the plurality of second sub-clock signals to obtain a plurality of second sampling signals;

Using the first jump edge of each second sampling signal as a sampling point, determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point;

Determine time stamp information according to the plurality of second sampled values and local time, and generate a clock synchronization protocol message, where the clock synchronization protocol message carries the time stamp information.
A clock synchronization system, characterized in that the clock synchronization system comprises:

The second frequency division module is used to divide the frequency of the second reference clock signal by a fractional frequency division phase-locked loop circuit to obtain a plurality of second sub-clock signals; wherein, the period of each second sub-clock signal is the same;

A second sampling module, configured to use the plurality of second sub-clock signals to sample the second pulse signal to obtain a plurality of second sampling signals;

The second sampling value determination module is configured to use the first jump edge of each second sampling signal as a sampling point to determine a plurality of second sampling values of the plurality of second sampling signals at the sampling point;

A message generating module, configured to determine time stamp information according to the plurality of second sampling values and local time, and send a clock synchronization protocol message to the message and second pulse signal receiving module, the clock synchronization protocol message carrying said timestamp information;

The message and second pulse signal receiving module is used to receive the second pulse signal and the clock synchronization protocol message sent by the message generating module, and analyze the clock synchronization protocol message to obtain time stamp information;

The first frequency division module is used to divide the frequency of the first reference clock signal by a fractional frequency division phase-locked loop circuit to obtain a plurality of first sub-clock signals; wherein, the period of each first sub-clock signal is the same;

A first sampling module, configured to use the plurality of first sub-clock signals to sample the second pulse signal to obtain a plurality of first sampling signals;

A first sampling value determining module, configured to use the first jump edge of each first sampling signal as a sampling point to determine a plurality of first sampling values of the plurality of first sampling signals at the sampling point;

A clock synchronization module, configured to perform clock synchronization according to the time stamp information and the plurality of first sampling values.