CN109765583A - A kind of clock synchronizing method based on GNSS receiver pulse per second (PPS) - Google Patents
A kind of clock synchronizing method based on GNSS receiver pulse per second (PPS) Download PDFInfo
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Abstract
The invention discloses a kind of clock synchronizing methods based on GNSS receiver pulse per second (PPS), and GNSS receiver pulse per second (PPS) 1PPS signal is input to elimination shake and constraint pretreatment circuit, 1PPS stabilization signal is generated, prevents occurring multiple pulse per second (PPS)s in 1 second；1PPS stabilization signal is counted using the first counter, result is clock signal of system actual frequency values, and the result is input to fixed-point divider, obtains the totalizing step of the second counter by formula operation；Clock signal of system is generated into sampling operation clock by the second counter frequency dividing, wherein keep the digit of the second counter constant, change the frequency of sampling operation clock signal by the size of the totalizing step delta of change second counter；Phase compensation is carried out to the sampling operation clock, when each 1PPS stabilization signal arrives, the pressure of sampling operation clock is drawn high, sampling operation clock and 1PPS stabilization signal alignment are made；Delay compensation is carried out to the sampling operation clock.The present invention solves the problems, such as that the accumulated error of low-frequency sampling work clock causes the calculated result of real-time system and reality nonsynchronous very well.
Description
Technical field
The present invention relates to microelectronic integrated circuit clock field of synchronization, are based on GNSS receiver second arteries and veins more particularly to one kind
The clock synchronizing method of punching.
Background technique
Main work sampling clock in IC design input via external clock crystal oscillator using PLL inside FPGA or
The special clocks management module frequency multiplication such as MMCM or frequency dividing generate, when needs working clock frequency be lower than 1MHz in the case where,
At this moment the special clock management resource inside FPGA is then unable to satisfy demand.In answering for certain high precision low frequency clock particular requirements
In, general clock division circuits cannot provide high quality and the high reliability clock without accumulated error.Clock jitter, drift
Cause with the accumulation of error of clock delay the calculating error introduced in the real-time system of long endurance high-precision high-reliability requirement without
Method meets system index requirement, and the present invention provides a kind of clock synchronizing methods based on GNSS receiver pulse per second (PPS), to solve
The accumulated error of low-frequency sampling work clock causes the calculated result and practical nonsynchronous problem of real-time system.
Summary of the invention
In order to overcome the shortcomings of above-mentioned existing clock division circuits, the present invention provides one kind to be based on GNSS receiver second arteries and veins
The clock synchronizing method of punching, comprising:
GNSS receiver pulse per second (PPS) 1PPS signal is input to elimination shake and constraint pretreatment circuit, generates 1PPS stabilization
Signal prevents occurring multiple pulse per second (PPS)s in 1 second；
1PPS stabilization signal is counted using the first counter, result is clock signal of system actual frequency values, will
The result is input to fixed-point divider, obtains the totalizing step of the second counter by formula operation；
Clock signal of system is generated into sampling operation clock by the second counter frequency dividing, wherein keep the second counter
Digit it is constant, change sampling operation clock signal by changing the size of totalizing step delta of second counter
Frequency；
Phase compensation is carried out to the sampling operation clock, when each 1PPS stabilization signal arrives, when by sampling operation
Clock pressure is drawn high, and sampling operation clock and 1PPS stabilization signal alignment are made；
Delay compensation is carried out to the sampling operation clock.
Optionally, the elimination shake and constraint pretreatment circuit utilize sampling operation clock signal to the 1PPS seconds arteries and veins
It rushes signal and carries out continuous sampling, sampled result each time is sent to shift register, if continuous sampling result is all 1
Think that actual signal is exactly 1, it is on the contrary then be 0.
Optionally, the formula are as follows:
Delta=2n*fc/fs, wherein n is the digit of counter, fcFor sampling operation clock frequency, fsFor system clock letter
Number actual frequency values.
Optionally, the fixed-point divider is 64 word lengths, and 40 fixed points, i.e., fractional part has 40, and integer part is
24, it is to multiply 2 rounding methods that decimal, which is converted to binary mode,.
Optionally, the delay compensation method includes the following steps:
It records 1PPS and completes to calculate to divider, accumulative frequency n；
Define totalizing step difference DELTA=delta (k)-delta (k-1)；
After divider is completed to calculate, n Δ is calculated, adds n Δ to the second counter.
Compared with prior art, the beneficial effects of the invention are as follows improve frequency-dividing clock circuit output sampling operation clock
Clock accuracy and the long-term accumulation error and stability for improving output sampling operation clock, are allowed to the second arteries and veins with GNSS receiver
The stringent essence of punching output is synchronous, calculates error, institute of the present invention caused by the long time drift for effectively avoiding output sampling operation clock
State the system application that clock synchronizing method is suitable for having stringent real-time synchronization requirement to long endurance high precision low frequency acquisition clock.
Detailed description of the invention
Fig. 1 is a kind of flow chart of clock synchronizing method based on GNSS receiver pulse per second (PPS) of the invention.
Specific embodiment
1 the present invention is further described with reference to the accompanying drawing.
Shake is eliminated in 1PPS pulse per second (PPS) and constraint pretreatment circuit theory is the 1PPS second arteries and veins using clock signal to input
It rushes signal and carries out continuous n times sampling, sampled result each time is sent to shift register, if n times sampled result is all 1
Being considered as actual signal is exactly 1, it is on the contrary then be 0.GNSS receiver under normal circumstances, believe by 1 1PPS pulse per second (PPS) of output in every 1 second
Number, the precision of 1PPS signal is in ± 20ns, and when to prevent receiver from breaking down, 1PPS signal repeatedly occurs in 1 second, uses
Constraint pretreatment circuit module is for monitoring 1PPS signal.The method of detection is: it is counted in the lower jump of some pulse per second (PPS) along starting,
Current system time clock is counted, if there is new second arteries and veins before count value is not up to (99%* system clock frequency)
This abnormal pulse per second (PPS) is not then sent into system by punching, and with the lower jump of this abnormal pulse per second (PPS) along new counting is started, using the method
It prevents from occurring in 1 second multiple pulse per second (PPS)s to impact system sampling clock generation.
Local sampling operation clock generates and the realization of measuring circuit is based primarily upon adder circuit and fixed-point divider electricity
Road.It is generated when being worked using local system and measuring circuit module generates sampling operation clock.Assuming that system clock is 100MHz,
Required sampling operation clock is generated, the basic principle is that: under system clock driving, the second counter is opened by initial value of zero
To begin to count, each clock cycle is incremented by 1, and it is cumulative more not enough in the initial stage, therefore first of counter is 0, with
Constantly first end of summary counter can set 1, and since the digit of counter is limited, and cause counter to overflow cumulative
Reset after out, cumulative process before circulation is gone down, so first of counter export is exactly a cycle square wave, i.e., I
The sampling operation clock signal that needs.
The digit that the mentality of designing of local sampling operation clock generation and measuring circuit is to maintain counter is constant, by changing
Become the size of totalizing step delta to change the frequency of sampling operation clock signal, such mentality of designing is more flexible.Assuming that existing
It is 4KHz in the sampling operation clock frequency that we need, this frequency is 4K/100M=0.00004 times of clock cycle, i.e.,
The period of sampling operation clock signal should be 25000 times of clock cycle, i.e., to add up 25000 times could be entire counter counts
It is full, and the size of counter is 48 in program, therefore the size of totalizing step delta is exactly every time:
48 digit counters are div200_counter, and in the rising edge of each system clock, counter adds up delta with reality
The existing above-mentioned frequency dividing based on adder, delta is exactly the result (quotient [47:0]) of fixed-point divider circuit output.
The actual frequency of system clock has differences with its nominal frequency, it is necessary to have accurate system clock frequency ability
Obtain accurate 4KHz clock.1PPS signal is the pulse signal generated by receiver based on satellite time transfer, is produced within the signal 1 second
It is 1 time raw, because referred to herein as " second pulse signal " (one pulse per second, 1pps) is local as time reference measurement
System clock frequency, i.e., using the system clock number between 1PPS twice under the first counter records, when obtaining local with this
Clock measured value.After obtaining local clock, according to calculation formula
delta-2n*fc/fs(wherein n is the digit of counter, is sampling operation clock frequency, is that clock signal of system is real
Border frequency values) it local clock is sent in fixed-point divider calculates.
Due to system clock and generates sampling operation clock and be not necessarily integral multiple relation, multiple proportion mixed decimal, but
It is to add up when being cumulative by integral multiple, the limited bits of fixed-point divider, there are truncated errors by the quotient found out.Because this two
The presence of a error, it is therefore desirable to carry out phase compensation.It is aligned to force to generate sampling operation clock with 1PPS, each
When 1PPS arrives, the pressure of sampling operation clock will be generated and drawn high, the initial value of the second counter div200_counter is made
0x8000 0,000 0000, then exporting clock is 1 (high level).However due to the presence of above-mentioned two error, so that by 1 second
It is cumulative after, div200_counter is less than 0x8,000 0,000 0000, that is, there is phase difference, it is therefore desirable in 1 second new week
The phase error of accumulation in 1 second is eliminated when the phase, i.e., when 1PPS arrives, calculates current summary counter value 0x8,000 0000
0000 differs, this difference is exactly phase error, and when new accumulation period starts, this phase error is fallen in compensation.Pass through
Sampling operation clock phase compensation circuit, it is ensured that accumulated error does not exceed 1 second, as long as and accumulation error be no more than 1
A totalizing step would not influence the generation precision for generating work clock.
When 1PPS arrives, totalizing step delta is recalculated using this local clock measured, but due to divider
Calculating needs the time, therefore has arrived in 1PPS to divider and completed this period of time calculated, and actual use is to count for last 1 second
Obtained delta；After the completion of divider calculates, just added up using new delta, in order to compensate for divider time delay band
The influence come, the resolving ideas of sampling operation clock delay compensation circuit are as follows:
It records 1PPS and completes to calculate to divider, accumulative frequency n；
Define totalizing step difference DELTA=delta (k)-delta (k-1)；
After divider is completed to calculate, n Δ is calculated, adds n Δ to accumulator register；
Realize above-mentioned compensation method particularly includes:
Using register div_cnt, under the control of enable signal div_cnt_en, arrives 1PPS to divider and complete
Computing interval, the cumulative number of the second counter are counted to obtain n.After divider is completed to calculate, this is calculated and is tied
Fruit and last computation result make difference to obtain Δ, compare size first when calculating, and guarantee always to subtract small with big, avoid
There is the case where negative.After Δ has been calculated, the delta of this calculating is latched, so that next time asks official post to use.Use Xilinx
IP kernel constructs multiplier, n and Δ is multiplied to obtain compensation rate n Δ, and compensate into the second counter.
Claims (5)
1. a kind of clock synchronizing method based on GNSS receiver pulse per second (PPS), which comprises the following steps:
GNSS receiver pulse per second (PPS) 1PPS signal is input to elimination shake and constraint pretreatment circuit, generates 1PPS stabilization letter
Number, prevent occurring multiple pulse per second (PPS)s in 1 second；
1PPS stabilization signal is counted using the first counter, result is clock signal of system actual frequency values, will be described
As a result it is input to fixed-point divider, the totalizing step of the second counter is obtained by formula operation；
Clock signal of system is generated into sampling operation clock by the second counter frequency dividing, wherein keep the position of the second counter
Number is constant, changes the frequency of sampling operation clock signal by the size of the totalizing step delta of change second counter
Rate；
Phase compensation is carried out to the sampling operation clock, it is when each 1PPS stabilization signal arrives, sampling operation clock is strong
System is drawn high, and sampling operation clock and 1PPS stabilization signal alignment are made；
Delay compensation is carried out to the sampling operation clock.
2. the method according to claim 1, wherein elimination shake and constraint pretreatment circuit utilize sampling
Operating clock signals carry out continuous sampling to the 1PPS second pulse signal, and sampled result each time is sent to shift LD
Device, it is on the contrary then be 0 if continuous sampling result is all that 1 to be considered as actual signal be exactly 1.
3. according to the method described in claim 2, it is characterized in that, the formula are as follows:
Delta=2n·fc/fs, wherein n is the digit of counter, fcFor sampling operation clock frequency, fsFor clock signal of system
Actual frequency values.
4. according to the method described in claim 3,40 pinpoint, i.e., it is characterized in that, the fixed-point divider is 64 word lengths
Fractional part has 40, and integer part is 24, and it is to multiply 2 rounding methods that decimal, which is converted to binary mode,.
5. according to the method described in claim 3, it is characterized in that, the delay compensation method includes the following steps:
It records 1PPS and completes to calculate to divider, accumulative frequency n；
Define totalizing step difference DELTA=delta (k)-delta (k-1)；
After divider is completed to calculate, n Δ is calculated, adds n Δ to the second counter.
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| CN111208539A (en) * | 2019-12-18 | 2020-05-29 | 中国航空工业集团公司成都飞机设计研究所 | High-precision GNSS simulator time synchronization method |
| CN111641490A (en) * | 2020-05-20 | 2020-09-08 | 中国人民解放军国防科技大学 | High-precision phase calibration and time reference determination method for sampling clock |
| CN112257368A (en) * | 2019-07-02 | 2021-01-22 | 上海复旦微电子集团股份有限公司 | Clock layout method, device, EDA tool and computer readable storage medium |
| CN112951134A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| CN114363125A (en) * | 2021-12-07 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Method for generating sampling pulse in digital asynchronous communication system |
| WO2023004576A1 (en) * | 2021-07-27 | 2023-02-02 | 华为技术有限公司 | Clock synchronization method, apparatus and system, and chip |
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| CN112257368A (en) * | 2019-07-02 | 2021-01-22 | 上海复旦微电子集团股份有限公司 | Clock layout method, device, EDA tool and computer readable storage medium |
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| CN111208539B (en) * | 2019-12-18 | 2023-06-23 | 中国航空工业集团公司成都飞机设计研究所 | High-precision GNSS simulator time synchronization method |
| CN111641490A (en) * | 2020-05-20 | 2020-09-08 | 中国人民解放军国防科技大学 | High-precision phase calibration and time reference determination method for sampling clock |
| CN111641490B (en) * | 2020-05-20 | 2021-07-09 | 中国人民解放军国防科技大学 | High-precision phase calibration and time reference determination method for sampling clock |
| CN112951134A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| WO2023004576A1 (en) * | 2021-07-27 | 2023-02-02 | 华为技术有限公司 | Clock synchronization method, apparatus and system, and chip |
| CN114363125A (en) * | 2021-12-07 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Method for generating sampling pulse in digital asynchronous communication system |
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