CN114363125A

CN114363125A - Method for generating sampling pulse in digital asynchronous communication system

Info

Publication number: CN114363125A
Application number: CN202111485076.4A
Authority: CN
Inventors: 周健恺; 李捷
Original assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Shanghai Huahong Integrated Circuit Co Ltd; Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2021-12-07
Filing date: 2021-12-07
Publication date: 2022-04-15

Abstract

The invention discloses a method for generating sampling pulses in a digital asynchronous communication system, which is mainly used for sampling transceiving data in a data communication process. The technology can flexibly generate required sampling pulses for transceiving data for asynchronous communication within a certain rate range. Meanwhile, the technology utilizes the error integrator to realize fractional frequency division so as to ensure that the error of each sampling period is controlled within one clock period through the adjustment of the numerical value of the error integrator under the condition that the time of each sampling period cannot be completely and evenly distributed, and finally ensure that the sampling error of each frame of data is controlled within an extremely low range. The technology has practical application value in the field of digital communication.

Description

Method for generating sampling pulse in digital asynchronous communication system

Technical Field

The invention relates to a sampling technology in the field of digital communication, in particular to a sampling pulse generation method in a universal asynchronous receiver-transmitter for receiving and transmitting data.

Background

In asynchronous communication, the midpoint of the transmitted and received data is typically sampled to obtain the logical value of the bit data. If the communication is in a noisy environment, the signal obtained by single sampling may be interfered by noise to cause an erroneous result, and at this time, oversampling needs to be added to perform "voting" determination, so as to eliminate the noise interference to the maximum extent, and obtain the optimal balance between the communication rate and the anti-noise. During single sampling, the midpoint of a data bit needs to be found; in the case of multiple sampling, for example, 8 times and 16 times, it is necessary to accurately find the 8-fold and 16-fold points of the data bits. Whether single sampling or multiple sampling, it is first necessary to locate the data bit equal division point and generate the sampling clock pulse. If the clock is used for frequency division to generate sampling pulses under a certain condition, a new problem is faced. If the time interval between sampling halves is not an integer multiple of the current clock period, i.e. the halves are located between two clock pulses. One of the alternatives at this time is to introduce a frequency multiplier circuit to obtain a higher frequency clock to approximate the sampling point to solve the problem, but this inevitably makes the circuit complicated and greatly increases the power consumption. The patent aims at the problem that an error integrator is introduced to realize fractional frequency division, under the condition that a clock is fixed, if the time interval between equal division points is not in an integral multiple relation relative to the current clock period, the error compensation is introduced to support a wider transmission baud rate range, and finally the infinite accumulation of errors can not be caused.

Disclosure of Invention

a) In the process of asynchronous communication, the time length of 1bit data can change along with the change of the baud rate aiming at different communication rates or baud rates. And meanwhile, the duration of the 1-bit data is evenly distributed according to the sampling times so as to generate sampling pulses in uniform time intervals. The invention realizes fractional frequency division by introducing an error integrator, realizes the generation of sampling pulses at extremely small error cost by an error compensation mode, and has ideal effects through simulation and fpga actual measurement.

b) The schematic block diagram of the invention is shown in fig. 1. Comprises a baud rate counter, an error integrator, a multiplexer MUX and a pulse generator. The baud rate counter is connected with the multiplexer MUX; the multiplexer MUX is connected with the pulse generator; the error integrator is connected to the sampling pulse and brr baud rate register values, the output of which is connected to the multiplexer MUX, which controls the clock period for the next cycle count. The UART CLK is an internal clock of asynchronous communication and is used for generating sampling pulses; BRR is baud rate information used to adjust the baud rate value. During each communication, the baud rate counter can calculate the equally divided sampling points of the single-bit data according to the current baud rate and the sampling times; because the distance between the equal division points may not be an integer value, the generation of sampling pulses at the point cannot be realized, so the baud rate counter can search a clock pulse closest to the equal division points to be used as the sampling pulse of the point, and meanwhile, the error is accumulated by the error integrator; when the accumulated error is larger than one UART CLK after multiple sampling, the MUX selects the calculation result compensated for one UART CLK for generating the sampling pulse. Finally, the time interval between each sampling pulse and the sampling halving point is smaller than one UART CLK. Along with the transmission of data, sampling will be accompanied by error compensation, so the error will not be infinitely accumulated, and finally the average error of transceiving of each frame data can be made small. When the UART CLK is 32.768K Hz, the baud rate is set to 9600, and each bit is sampled once, the theoretical error value for sending a single frame of data using this technique is only 0.1949%.

Drawings

FIG. 1: invention patent principle block diagram

FIG. 2: sampling pulse simulation diagram for setting 16 times sampling

FIG. 3: sampling pulse simulation result when error integrator does not need compensation

FIG. 4: sampling pulse simulation result when error integrator needs compensation

Detailed Description

FIG. 1 is a schematic diagram of the present invention including a baud rate counter, an error integrator, a MUX, and a pulse generator. The value of brr baud rate register is used as the input of baud rate counter and error integrator to control the clock period count value and accumulated value of error integrator in each sampling period. The multiplexer MUX is controlled by the output of the error integrator to select whether the counter needs to count one more clock cycle depending on whether it overflows. The output of the MUX controls the generation of sampling pulses, and the generated sampling pulses are fed back to the error integrator to clear the overflow value of the error integrator.

The sampling pulse signal is widely applied to communication protocols such as USART, and by taking an asynchronous communication part uart in the USART as an example, a communication baud rate is defined as a ratio of a communication clock frequency to brr, and when the clock frequency is fixed, the communication baud rate can be adjusted by modifying brr values. When the baud rate is divided completely, the sampling pulse is generated when the baud rate is accumulated to brr/sampling multiple only by a counter. Assuming that 16 samples are currently being taken, i.e., 16 equally spaced sample pulses are generated per bit of data, brr may now be considered the number of clock cycles contained within each data bit. When brr is exactly an integer multiple of 16, the baud rate counter will generate one sample pulse every brr/16 clock pulses, and will continue to cycle. When brr is not an integer multiple of 16, and the number of clock cycles involved in each sample interval is not an integer, the baud rate counter initially generates a sample at brr/16 (round-down) clock pulses and simultaneously enables the error integrator to accumulate the error in the fractional part that is not divisible by 16. When the current accumulated value of the integrator overflows, the distance between the sampling pulse and the equal division point exceeds one clock period, and as compensation, the baud rate counter can count one more period and select and output through the MUX, so that the ideal sampling equal division point of each actual sampling pulse is ensured to be smaller than one clock period. The following obtains a simulation waveform diagram after the specific implementation by writing RTL codes. The brr register is first configured as a decimal 521, which is obviously not an integer multiple of 16. It can be calculated that the sampling halving point is located at the integral multiple of 32.5625 of the clock period number. Therefore, the sampling pulse signal is generated by fractional division with the aid of an error integrator. Meanwhile, since 512 is an integer multiple of 16, the excess 521-512-9 clock cycles need to be distributed in 16 sampling cycles, that is, 9 sampling cycles are compensation cycles including 33 clock cycles, and the remaining 7 sampling cycles are uncompensated cycles including 32 clock cycles. In fig. 2, "ubdiv _ frac _ acc _ rx" is an error integral value, the error integral value is increased by 9 in each sampling period, when the error integral value is greater than or equal to 16, the overflow signal "ubdiv _ frac _ acc _ overflow _ rx" of the error integrator will give a flag, and at this time, error compensation will occur once, and the sampling pulse at the compensation will be compensated by one more clock period, that is, the sampling period is 33 clock periods. The 2 nd and 3 rd sampling periods are further selected to amplify the waveforms, as shown in fig. 3 and 4. The integrator value is a in fig. 3, so the counter counts from 0 to 1f, generating a sampling pulse baud _ x16_ pl at the 32 th clock cycle; in fig. 4, the integrator value is 1, so the counter counts from 0 to 20, generating a sampling pulse baud _ x16_ pl at the 33 th clock cycle. The above results are expected to be consistent with the present invention. The invention is not only suitable for the middle point sampling of asynchronous data transmission, but also is suitable for sampling of 4 equally divided points, 8 equally divided points, 16 equally divided points of data bits, even 1/(2^ n) equally divided points.

Claims

1. A method for generating sampling pulse in digital asynchronous communication system is characterized in that the method comprises an error integrator, fractional frequency division is realized in a certain baud rate variation range, and finally sampling pulse signals are generated, wherein the method comprises the following steps:

1) when the sampling period and the clock period are in integral multiple relation, the sampling pulse is generated when the counting is accumulated to the Baud rate register value/sampling multiple through a counter, and the cycle is performed.

2) When the sampling period is not integral multiple of the clock period, an error integrator is introduced, and a counter reaches a baud rate register value/sampling multiple and generates sampling pulses after rounding down; meanwhile, the error is accumulated in the error integrator, and when the error accumulated value of the error integrator overflows, the sampling pulse is generated by adding one more cycle.

2. A circuit for sampling pulses in a digital asynchronous communication system for implementing the method of claim 1, characterized in that said circuit comprises a baud rate counter, a multiplexer MUX and a pulse generator, and further comprises an error integrator, the output of said error integrator being connected to the multiplexer MUX for controlling the clock period counted in the next cycle.