CN103618501A - Alternating current sampling synchronous frequency multiplier based on FPGA - Google Patents
Alternating current sampling synchronous frequency multiplier based on FPGA Download PDFInfo
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- CN103618501A CN103618501A CN201310572201.4A CN201310572201A CN103618501A CN 103618501 A CN103618501 A CN 103618501A CN 201310572201 A CN201310572201 A CN 201310572201A CN 103618501 A CN103618501 A CN 103618501A
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Abstract
The invention relates to an alternating current sampling synchronous frequency multiplier based on an FPGA. In order to ensure accuracy of electric parameters in an electric energy quality monitoring system, alternating current sampling needs to be conducted on the electric energy quality monitoring system, in the alternating current sampling process, synchronous frequency multiplication needs to be conducted, and frequency multiplication multiples are difficult to change when a traditional frequency tracking circuit made of a CD4046 phase-locked loop is utilized to conduct frequency multiplication. According to the alternating current sampling synchronous frequency multiplier, a verilogHDL is utilized, specific to the limitation of a traditional frequency multiplication circuit, a frequency multiplication algorithm of a dither signal source, any low-frequency frequency multiplication algorithm and any high-power frequency multiplication algorithm are achieved in a counting frequency division mode, eventually, after a hardware circuit is built through matlab simulation and a provided FPGA device, an oscilloscope is used for test, and correctness and usability of the algorithms are verified. The method is good in compatibility, high in transportability, suitable for various occasions where frequency multiplication signals are needed, low in cost and good in economic benefits.
Description
Technical field
The present invention relates to random frequency multiplication algorithm and Error Compensation Algorithm two parts based on FPGA.Especially in Error Compensation Algorithm, the whole compensation to truncated error part have been realized.
Background technology
Along with the fast development of electric power system, all there is huge variation in the capacity of electrical network, structure, and instrument and meter industry is also constantly being improved.In electric energy quality monitoring, the method for firm power parameter sampling and calculating is generally had to two kinds, be respectively ac sampling method and direct current sampling method.Direct current sampling method is only done a transformation of scale to sampled value, and its certainty of measurement is limited more, and error is large, unstable, so conventionally want to obtain the electrical quantity of high-precision and high-stability, need to carry out AC sampling.
AC sampling is according to certain rules the instantaneous value of signal to be sampled, and according to the fundamental theorem of sampling, sample frequency need to be higher than the more than 2 times of measured signal highest frequency.What in electric power system, commonly use is synchronous AC sampling.It is traditional that with hardware, to realize synchronized sampling be to use special hardware circuit to produce the lock-out pulse that is synchronized with measured signal.Application phase-locked loop chip CD4046 realizes synchronous equal interval sampling and is difficult to frequency multiplication multiple to carry out random change.
In order to address such a problem, the invention provides a kind of random frequency multiplication algorithm based on FPGA.The present invention has adopted the larger feature of FPGA reference clock, utilizes scale clock frequency division to obtain the mode of input signal frequency multiplication, and by the remainder part of non-integer division of frequency intercepting, has realized whole compensation.The present invention can realize any change of frequency multiplication multiple, and precision is higher, and availability is strong, can be applied to the multiple occasion that needs frequency multiplication.
Summary of the invention
In order to solve frequency multiplication multiple in frequency doubling system, cannot change easily, and the problems such as requirement to input signal source frequency, the invention provides a kind of random frequency multiplication algorithm based on FPGA.It is by synchronization module, counter module, and division module and compensating module four parts form.
Described synchronization module is responsible for input signal to synchronize with clock signal of system, wherein input signal is the initialize signal that needs frequency multiplication, synchronization module makes the clock signal starting point of input signal and system at synchronization, even if there is error, error is also within a system clock cycle.Signal after described counter module receives synchronously, take system clock as benchmark, and input clock signal is counted.Look in other words in the one-period of input signal, comprised how many clock signal of system cycles.Count value after described division module utilizes rolling counters forward to complete, frequency multiplication multiple and clock signal of system and count value are sent into wherein in the lump, division module carries out exporting the signal after frequency multiplication after a series of algorithm flow according to count value and frequency multiplication multiple simultaneously.Described compensating module carries out suitable compensation according to the truncated error of signal after frequency multiplication to remainder, thereby reduces the impact that truncated error is brought.
The present invention has adopted the dual input list way of output, and two input signals are respectively will the primary signal of frequency multiplication and the clock signal of system, and single output is exactly the signal that will use after frequency multiplication.Utilize verilog HDL language, through the inner complicated gate of FPGA, obtain and need output signal.The present invention has realized dither signal source, arbitrarily low-frequency input signal frequency multiplication and any high multiple (signal frequency after frequency multiplication is no more than reference clock frequency) frequency multiplication.Compatibility of the present invention is good, portable strong, is applicable to the various occasions that need frequency multiplication.
Accompanying drawing explanation
Fig. 1 is AC synchronous sampling frequency multiplication algorithm structure figure.
Embodiment
Embodiment is with reference to accompanying drawing 1, first input signal and clock signal of system are carried out to Synchronous Pre processing, make input signal and system clock synchronous, wherein input signal is the initialize signal that needs frequency multiplication, synchronization module makes the clock signal starting point of input signal and system at synchronization, even if there is error, error is also within a system clock cycle.Signal after synchronous is sent into counter, take system clock as benchmark, and input clock signal is counted.Look in other words in the one-period of input signal, comprised how many clock signal of system cycles.Give an example, the clock signal of supposing the system is 5MHz, and system clock cycle is probably 2ns so, and input signal is 50Hz, and its cycle is 0.02s.Numeral, can find out merely, in an input signal cycle, comprise 10
5individual system clock cycle.So between two rising edges of input signal, rolling counters forward value also should be 10
5.
The system clock cycle number that input signal comprises is a changeless number, so the system clock cycle number that the output signal after frequency multiplication comprises should be also a changeless number
[4].Above example is example, supposes that frequency multiplication multiple is 100 times, and the system clock cycle number that output signal comprises so should be just 10
3individual.
After rolling counters forward completes, frequency multiplication multiple, clock signal of system and count value are sent into division module simultaneously, division module carries out exporting the signal after frequency multiplication after a series of algorithm flow according to count value and frequency multiplication multiple.From principle, can find out, the frequency after input signal frequency multiplication can not be greater than system clock frequency, because this algorithm is finally summed up as the frequency division problem to clock signal of system to the frequency multiplication problem of input clock frequency.If frequency multiplication multiple is
k, first take system clock as benchmark is to counting between two of input signal rising edges, obtain the count value of an input signal cycle
n, obtain frequency multiplication
ksignal doubly, with
n/
knumber (round numbers), as the divide ratio of next cycle system clock, is called frequency division counter word by this value, be designated as [
n/
k].Describe the derivation of frequency division counter word below in detail.
Consider the jitter of input signal, frequency division counter word is not one and stablizes constant numeral.Along with the shake of input signal, frequency division counter word also can fluctuate in a number range.Suppose mains frequency fluctuation 10% with interior, input signal frequency range is between 45Hz ~ 55Hz.In an input signal cycle, the number that multipotency is adopted system clock is in theory 10
5* (1+10%)=110000, the minimum system clock number that can adopt is 10
5* (1-10%)=90000.If want 1024 times of frequencys multiplication, the value of frequency division counter word should be at 90000/1024=87.89 between 110000/1024=107.42.Here our round numbers is as the frequency division counter word in next cycle.For the processing of remainder part, in backoff algorithm below, introduce in detail.
According to algorithm, the count value of input signal one-period
ndivide ratio divided by the integer value obtaining after Clock Multiplier Factor K as next cycle, therefore next cycle output signal comprises
kthe pulse that individual interval is equal.Because the system clock of standard is constant, the shake of a upper periodic input signal frequency can directly cause the variation of Counter Value, therefore the output signal in this cycle is only relevant with the input signal in a upper cycle.Because each frequency division counter word is all got
n/
kinteger part, can find out that error is mainly derived from the truncated error after rounding.Pass to frequency divider value [
n/
k] ([
k] represent to get to be not more than
kinteger) be always less than or equal to
n/
kactual value.If remainder
l=Mod (
n/
k), so
lone fixes between 0 to K-1.So the multiple of frequency multiplication is larger, the value of [N/K] is less, remainder
llarger, will occur like this
l>[
n/K] situation, so frequency multiplication multiple will be greater than
k.Example in reference 2.2, supposes that now frequency input signal is 45Hz, and counter sampled value in input signal one-period is
n=110000, for 1024 times of frequency divisions, [
n/
k]=107, remainder is 432, is greater than the business 107 who obtains, if now press 107 frequency divisions in next cycle, the pulse number so in fact obtaining is [110000/107]=1028>1024.Consider in the most extreme situation remainder
l=
k-1, now output frequency is to the maximum:
Wherein
for system clock frequency, if desirable output frequency is
, so maximum relative error is
From (2), can find out, when N mono-timing, K is larger, and relative error is larger.Especially, the Algorithm Error of blocking like this frequency division output is to have accumulative total, and As time goes on, cumulative errors cause, and to affect meeting increasing.
As known from the above, after frequency multiplication, the output error of signal is mainly derived from truncated error, therefore proposes in frequency multiplier, to introduce a backoff algorithm, remainder is carried out to suitable compensation, thereby reduce the impact that truncated error is brought
[9].Its basic thought is, a upper cycle remainder be take and 1 compensated in the pulse in next cycle as unit.Give an example, if the business who obtained in a upper cycle [
n/
k]=
m, remainder is
l,, in front L the pulse in next cycle, each pulse duration is M+1, a pulse from L to K, and each pulse duration is M, so just can realize the whole compensation to remainder L.Be exemplified below:
Pulse train: pulse 1 ... pulse L pulse L+1 ... pulse n
Pulse duration: M+1 ... M+1 M ... M
Compare with the frequency multiplication algorithm of uncompensated circuit, the pulse of output will be extended down to a system clock cycle.Suppose under extreme case remainder
l=
k-1, the frequency of exporting so pulse is at most
Maximum relative error is:
This shows, the circuit after overcompensation, its error and frequency multiplication multiple K are irrelevant, do not have deviation accumulation, have solved the shortcoming of deviation accumulation in traditional uncompensated frequency doubling system.
The present invention adopts programmable device FPGA as carrier, utilizes verilog HDL language to programme to it.By the mutual cooperation of four modules, realized any low frequency in dither signal source, arbitrarily the frequency multiplication output signal of high power.Compatibility of the present invention is good, and portable strong, cost is low good in economic efficiency.
Claims (4)
1. the AC sampling synchronizing and frequency doubling device based on FPGA, it comprises synchronizing and frequency doubling algorithm and error compensation two parts, it is characterized in that realizing any multiple frequency multiplication (after frequency multiplication, frequency is no more than FPGA clock frequency) in any low frequency dither signal source, error after overcompensation can be controlled in 0.1%, it comprises four main modular, respectively synchronization module, counter module, division module and compensating module.
2. synchronizing and frequency doubling device according to claim 1, its frequency multiplication algorithm gets from FPGA system reference clock frequency division.
3. synchronizing and frequency doubling device according to claim 1, its backoff algorithm is different according to remainder, selects the pulse of corresponding remainder, increases respectively a width, whole compensation of carrying out.
4. synchronizing and frequency doubling device according to claim 1, its counter module is to take system clock input primary signal to be counted in one-period as benchmark.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270095A (en) * | 2014-09-29 | 2015-01-07 | 武汉理工大学 | CPLD-based single-chip square signal frequency doubler and method for outputting any frequency doubling signal |
| CN108055006A (en) * | 2017-12-29 | 2018-05-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
| CN109283864A (en) * | 2017-07-21 | 2019-01-29 | 北京智云芯科技有限公司 | A kind of time synchronization of data sampling, calibration method and system |
| CN109597297A (en) * | 2018-12-11 | 2019-04-09 | 烟台持久钟表有限公司 | A kind of crystal oscillator compensation method and device |
| CN114363125A (en) * | 2021-12-07 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Method for generating sampling pulse in digital asynchronous communication system |
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| US20050197848A1 (en) * | 2004-03-08 | 2005-09-08 | Chou Y. H. | Airport customer support dispatch system and method for operation for the same |
| CN100456630C (en) * | 2005-03-22 | 2009-01-28 | 杭州华三通信技术有限公司 | Low frequency clock signal generating method and low frequency cloc ksignal generator |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104270095A (en) * | 2014-09-29 | 2015-01-07 | 武汉理工大学 | CPLD-based single-chip square signal frequency doubler and method for outputting any frequency doubling signal |
| CN104270095B (en) * | 2014-09-29 | 2017-05-24 | 武汉理工大学 | CPLD-based single-chip square signal frequency doubler and method for outputting any frequency doubling signal |
| CN109283864A (en) * | 2017-07-21 | 2019-01-29 | 北京智云芯科技有限公司 | A kind of time synchronization of data sampling, calibration method and system |
| CN109283864B (en) * | 2017-07-21 | 2020-05-05 | 北京智云芯科技有限公司 | Time synchronization and calibration method and system for data sampling |
| CN108055006A (en) * | 2017-12-29 | 2018-05-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
| CN109597297A (en) * | 2018-12-11 | 2019-04-09 | 烟台持久钟表有限公司 | A kind of crystal oscillator compensation method and device |
| CN114363125A (en) * | 2021-12-07 | 2022-04-15 | 上海华虹集成电路有限责任公司 | Method for generating sampling pulse in digital asynchronous communication system |
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Application publication date: 20140305 |