CN108055006A - A kind of digital frequency multiplier - Google Patents
A kind of digital frequency multiplier Download PDFInfo
- Publication number
- CN108055006A CN108055006A CN201711474472.0A CN201711474472A CN108055006A CN 108055006 A CN108055006 A CN 108055006A CN 201711474472 A CN201711474472 A CN 201711474472A CN 108055006 A CN108055006 A CN 108055006A
- Authority
- CN
- China
- Prior art keywords
- module
- frequency
- clock signal
- high frequency
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
Abstract
The invention discloses a kind of digital frequency multipliers, are related to technical field of integrated circuits.The digital frequency multiplier includes input module, receives externally input high frequency clock signal and Clock Multiplier Factor, and the high frequency clock signal is carried out scaling down processing；Control module receives the source clock signal of input；Computing module receives the high frequency clock signal after the input module scaling down processing, receives the control signal that the control module is sent and is calculated or resetted, the computing module is calculated frequency division coefficient and exports；Output module receives the frequency division coefficient of the computing module output, receives the high frequency clock signal, and the output module exports frequency-doubled signal after being divided according to the frequency division coefficient to the high frequency clock signal.Technical solution of the present invention can realize the frequency multiplication process of different multiples by changing the value of Clock Multiplier Factor, since the digital frequency multiplier of the present invention is simple in structure, has very strong operability, and improve reliability and stability.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of digital frequency multiplier.
Background technology
Frequency multiplier（frequency multiplier）It is the electricity that output signal frequency is equal to frequency input signal integral multiple
Road.Frequency multiplier is widely used, and frequency stability can be improved after using frequency multiplier such as transmitter；Frequency modulation equipment is increased with frequency multiplier
Frequency shift (FS)；In phase keying communication equipment, frequency multiplier is an important composition unit of carrier recovery circuit.
Current most common frequency multiplier is phase-locked loop circuit.But relatively ripe phase-locked loop circuit, there is also fortune
Row overlong time is present with the situation of losing lock.In addition, when Clock Multiplier Factor requirement is very big, phase-locked loop circuit is difficult to realize,
Software side realizes method, and there is also the problem of cost is higher, reliability is low.
The content of the invention
It is a primary object of the present invention to provide a kind of digital frequency multiplier, it is intended to improve the reliability and stabilization of frequency multiplier
Property.
To achieve the above object, the present invention provides a kind of digital frequency multiplier, including：
Input module receives externally input high frequency clock signal and Clock Multiplier Factor, and the high frequency clock signal is divided
Frequency is handled；
Control module receives the source clock signal of input；
Computing module receives the high frequency clock signal after the input module scaling down processing, receives what the control module was sent
Control signal is calculated or resetted, and the computing module is calculated frequency division coefficient and exports；
Output module receives the frequency division coefficient of the computing module output, receives the high frequency clock signal, the output module
Frequency-doubled signal is exported after being divided according to the frequency division coefficient to the high frequency clock signal.
Preferably, the frequency division coefficient includes integer value A and remainder values B, the output module according to the integer value A and
The remainder values B determines the cycle of the frequency-doubled signal C：B is described times as count value and C-B by count value of A using A+1
The a cycle of frequency signal.
Preferably, it is 2 to preset the Clock Multiplier FactorN, the cycle of source clock signal is M times of the high frequency clock signal cycle,
The computing module calculates M/2NValue, to obtain frequency division coefficient.
Preferably, the computing module includes integer module and remainder module, and the integer module is to the high frequency clock
Signal carries out 2NIt is counted to obtain integer value A after frequency dividing, the remainder module counts the high frequency clock signal
To obtain remainder values B, when the count value of the remainder module is equal to the integer module count value, the remainder module is again
It is counted.
Preferably, the control module further includes clock synchronization module, for by the source clock signal synchronization to described
On high frequency clock signal, and by the signal after synchronization by outputing control signals to the computing module with door.
Preferably, the computing module further includes counter module, for integer module count and remainder module count；When
When control signal is effective, the counting module resets, and exports effective count value to the output module.
Technical solution of the present invention calculates Clock Multiplier Factor to obtain frequency division coefficient by computing module, and output module is according to frequency division coefficient
It is exported after being divided to high-frequency signal, the frequency multiplication process of different multiples can be realized by the value for changing Clock Multiplier Factor, due to
The digital frequency multiplier of the present invention is simple in structure, has very strong operability, and improves reliability and stability.
Description of the drawings
Fig. 1 is the principle schematic of digital frequency multiplier of the present invention；
Fig. 2 is the principle schematic of input module in digital frequency multiplier of the present invention；
Fig. 3 is the principle schematic of control module in digital frequency multiplier of the present invention；
Fig. 4 is the control logic sequence diagram of control module in digital frequency multiplier of the present invention；
Fig. 5 is the principle schematic of computing module in digital frequency multiplier of the present invention；
Fig. 6 is the principle schematic of output module in digital frequency multiplier of the present invention.
The embodiments will be further described with reference to the accompanying drawings for the realization, the function and the advantages of the object of the present invention.
Specific embodiment
It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not intended to limit the present invention.
The present invention is further described below in conjunction with the accompanying drawings.
The present invention provides a kind of digital frequency multiplier, as shown in Figure 1, the digital frequency multiplier include input module, control module,
Computing module and output module, modules are realized using Digital Logical Circuits：
As shown in Fig. 2, input module, receives externally input high frequency clock signal clk_G and Clock Multiplier Factor 2N, and by the height
Frequency clock signal clk_G carries out scaling down processing；High frequency clock signal clk_div after output frequency division.
Specifically, stable high frequency clock signal clk_G, which is inputted to digital frequency multiplier, can maintain the system to operate substantially, right
It is 2 controlled according to Clock Multiplier Factor that the high frequency clock signal, which carries out frequency dividing,N, wherein, N is positive integer.In general, current sets
It is standby to support that N value ranges are 1 to 10.In further embodiments, the value of N can be according to the N that needs voluntarily to set of user
Positive integer more than 10.
As shown in figure 3, control module, the source clock signal clk_A of input is received.
Preferably, the control module further includes clock synchronization module, for by the source clock signal synchronization to described
On high frequency clock signal clk_G, and by the signal after synchronization by outputing control signals to the computing module with door.
Specifically, control module generates control signal according to source clock signal clk_A, for controlling the counting of computing module
The reset of device or output count value.After input source clock clk_A effective impulses arrive, control logic module is to dividing module
Counter, which is sent, resets control and output count value control.During the control signal that clk_G, clk_A and control logic module export
For sequence as shown in figure 4, wherein rst_n is systematic reset signal, when low level, resets counter；Clk_dly1 is clk_A
The signal of clk_G clock domains is synchronized to, clk_dly2 is the signal in clk_dly1 1 clk_G cycle of delay, and clk_dly3 is
The signal in clk_dly2 1 clk_G cycle of delay, ctr_out count length control signal for counter, and ctr_clr is counting
Device removes control signal.
As shown in figure 5, computing module, receives the high frequency clock signal clk_G after the input module scaling down processing, receive
The control signal that the control module is sent is calculated or resetted, and the computing module is calculated frequency division coefficient and exports.
Preferably, it is 2 to preset the Clock Multiplier FactorN, the cycle of source clock signal is the high frequency clock signal clk_G cycles
M times, the computing module calculates M/2NValue, to obtain frequency division coefficient.
Specifically, the cycle of clk_A is M times of the cycle of clk_G, is tclk_A = M*tclk_GIf Clock Multiplier Factor K=
2N, it is tclk_A= tclk_out* K, then tclk_out= tclk_G*（M/K）.Being worth to for M/K is calculated by computing module and divides system
Number, and export to output module.
Preferably, the computing module includes integer module and remainder module, and the integer module is to the high frequency clock
Signal clk_G carries out 2NIt is counted to obtain integer value A after frequency dividing, the remainder module is to the high frequency clock signal clk_
G is counted to obtain remainder values B, described remaining when the count value of the remainder module is equal to the integer module count value
Digital-to-analogue block re-starts counting.
Computing module is divided into integer module and remainder module.Integer module is counted after clk_G carries out K frequency dividings, ctrl_
When clr control signals are effective, counter resets；When ctrl_out signals are effective, count value is exported.Remainder module is clk_G
As the counting clock of counter, the effective hour counters of ctrl_clr reset, and ctrl_out signals export count value when effective.
When the count value of remainder module is equal to the output valve of integer module, counter counts again.
Preferably, the computing module further includes counter module, for integer module count and remainder module count；When
When control signal is effective, the counting module resets, and exports effective count value to the output module.
As shown in fig. 6, output module, receives the frequency division coefficient of the computing module output, receives the high frequency clock letter
Number clk_G, the output module export frequency multiplication after being divided according to the frequency division coefficient to the high frequency clock signal clk_G
Signal.
Output module exports after high frequency clock signal clk_G is divided, and is the echo signal after frequency multiplication.Described point
Frequency coefficient include integer value A and remainder values B, the output module according to the integer value A and the remainder values B are determined again
The cycle of frequency signal C：B is a cycle of the frequency-doubled signal by count value and C-B of A+1 by count value of A.Specifically
Ground is divided into integral frequency divisioil and fractional frequency division in output module.If the integer value of frequency division coefficient is A, remainder values B, frequency multiplication value is
C, then it is count value and the C-B appearance using A as the pulse period property of count value that frequency-doubled signal, which is exactly B using A+1, wherein B<
C。
Source clock frequency is low, Clock Multiplier Factor is larger suitable for inputting for digital frequency multiplier of the present invention（Frequency-doubled signal.Input
The high frequency clock signal clk_G cycles are 1/M times of input source clock signal clk_A cycles, and Clock Multiplier Factor is K=2N, computing module
The integer and remainder of M/K is calculated, output module exports frequency-doubled signal using the value of computing module.Control module control counts
The counting step of device module.By changing the value of Clock Multiplier Factor, the frequency multiplication process of different multiples can be realized.Number times of the invention
Frequency device is completed by digital logic circuit, simple in structure, is had very strong operability, is improved reliability and stability, can be with
It is described with verilog language, and passes through FPGA can very easily realize.
It should be appreciated that it these are only the preferred embodiment of the present invention, it is impossible to therefore the scope of the claims of the limitation present invention,
Every equivalent structure or equivalent flow shift made using description of the invention and accompanying drawing content, is directly or indirectly used
In other related technical areas, it is included within the scope of the present invention.
Claims (6)
1. a kind of digital frequency multiplier, which is characterized in that including：
Input module receives externally input high frequency clock signal and Clock Multiplier Factor, and the high frequency clock signal is divided
Frequency is handled；
Control module receives the source clock signal of input；
Computing module receives the high frequency clock signal after the input module scaling down processing, receives what the control module was sent
Control signal is calculated or resetted, and the computing module is calculated frequency division coefficient and exports；
Output module receives the frequency division coefficient of the computing module output, receives the high frequency clock signal, the output module
Frequency-doubled signal is exported after being divided according to the frequency division coefficient to the high frequency clock signal.
2. digital frequency multiplier according to claim 1, which is characterized in that the frequency division coefficient includes integer value A and remainder
Value B, the output module determine the cycle of the frequency-doubled signal C according to the integer value A and the remainder values B：B with A+1
It is a cycle of the frequency-doubled signal by count value of A for count value and C-B.
3. digital frequency multiplier according to claim 2, which is characterized in that it is 2 to preset the Clock Multiplier FactorN, source clock signal
Cycle be M times of the high frequency clock signal cycle, the computing module calculating M/2NValue, to obtain frequency division coefficient.
4. digital frequency multiplier according to claim 3, which is characterized in that the computing module includes integer module and remainder
Module, the integer module carry out 2 to the high frequency clock signalNIt is counted to obtain integer value A, the remainder after frequency dividing
Module counts the high frequency clock signal to obtain remainder values B, when the count value of the remainder module is equal to described whole
During digital-to-analogue block counting values, the remainder module re-starts counting.
5. digital frequency multiplier according to claim 4, which is characterized in that the control module further includes clock synchronization mould
Block, for passing through the source clock signal synchronization with door with defeated to the high frequency clock signal, and by the signal after synchronization
Go out control signal to the computing module.
6. digital frequency multiplier according to claim 5, which is characterized in that the computing module further includes counter module,
For integer module count and remainder module count；When control signal is effective, the counting module resets, and exports effectively meter
Numerical value is to the output module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711474472.0A CN108055006A (en) | 2017-12-29 | 2017-12-29 | A kind of digital frequency multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711474472.0A CN108055006A (en) | 2017-12-29 | 2017-12-29 | A kind of digital frequency multiplier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108055006A true CN108055006A (en) | 2018-05-18 |
Family
ID=62128913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711474472.0A Pending CN108055006A (en) | 2017-12-29 | 2017-12-29 | A kind of digital frequency multiplier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108055006A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110212916A (en) * | 2019-06-04 | 2019-09-06 | 中国工程物理研究院激光聚变研究中心 | A kind of extensively distribution low jitter synchronised clock dissemination system and method |
| CN116094513A (en) * | 2023-04-04 | 2023-05-09 | 苏州萨沙迈半导体有限公司 | Decimal frequency dividing system, decimal frequency dividing method and decimal frequency dividing chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102035472A (en) * | 2010-10-29 | 2011-04-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable digital frequency multiplier |
| CN103618501A (en) * | 2013-11-13 | 2014-03-05 | 哈尔滨电工仪表研究所 | Alternating current sampling synchronous frequency multiplier based on FPGA |
| CN104660220A (en) * | 2015-02-04 | 2015-05-27 | 武汉华中数控股份有限公司 | Signal generator and signal generation method for generating integer frequency pulses |
| CN207884576U (en) * | 2017-12-29 | 2018-09-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
-
2017
- 2017-12-29 CN CN201711474472.0A patent/CN108055006A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102035472A (en) * | 2010-10-29 | 2011-04-27 | 中国兵器工业集团第二一四研究所苏州研发中心 | Programmable digital frequency multiplier |
| CN103618501A (en) * | 2013-11-13 | 2014-03-05 | 哈尔滨电工仪表研究所 | Alternating current sampling synchronous frequency multiplier based on FPGA |
| CN104660220A (en) * | 2015-02-04 | 2015-05-27 | 武汉华中数控股份有限公司 | Signal generator and signal generation method for generating integer frequency pulses |
| CN207884576U (en) * | 2017-12-29 | 2018-09-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110212916A (en) * | 2019-06-04 | 2019-09-06 | 中国工程物理研究院激光聚变研究中心 | A kind of extensively distribution low jitter synchronised clock dissemination system and method |
| CN110212916B (en) * | 2019-06-04 | 2022-04-19 | 中国工程物理研究院激光聚变研究中心 | Wide-distribution low-jitter synchronous clock distribution system and method |
| CN116094513A (en) * | 2023-04-04 | 2023-05-09 | 苏州萨沙迈半导体有限公司 | Decimal frequency dividing system, decimal frequency dividing method and decimal frequency dividing chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103297046B (en) | A kind of phaselocked loop and its clock generation method and circuit | |
| US8559582B2 (en) | Techniques for varying a periodic signal based on changes in a data rate | |
| CN101478308B (en) | Configurable frequency synthesizer circuit based on time-delay lock loop | |
| CN102035472B (en) | Programmable digital frequency multiplier | |
| CN106533401A (en) | DPWM module for synchronous segmentation delay chain based on FPGA | |
| CN104954015B (en) | Clock generation method and semiconductor device | |
| CN201663588U (en) | Device realizing multi-phase clock fractional division | |
| US8368436B1 (en) | Programmable frequency synthesizer with I/Q outputs | |
| US20140197867A1 (en) | Circuits and Methods for Using a Flying-Adder Synthesizer as a Fractional Frequency Divider | |
| TWI505642B (en) | All - digital Spread Spectrum Clock Generation Circuit with Electromagnetic Interference Effect Decay and Its Control Method | |
| CN101572543A (en) | Method and device for stabilizing clock | |
| CN103427835A (en) | Frequency modulator | |
| CN103427798B (en) | A kind of multiphase clock generation circuit | |
| CN207884576U (en) | A kind of digital frequency multiplier | |
| CN108055006A (en) | A kind of digital frequency multiplier | |
| CN107005243B (en) | The phaselocked loop for preventing function is locked with subharmonic | |
| CN203313155U (en) | Phase-locked loop and clock generation circuit thereof | |
| CN101421930A (en) | Method and system for configuration of a phase-locked loop circuit | |
| US8710893B2 (en) | Method and device for generating low-jitter clock | |
| CN106549667A (en) | Digital decimal frequency divider and its dividing method | |
| CN111262578B (en) | Multi-chip synchronization circuit, system and method for high-speed AD/DA (analog-to-digital/digital) chip | |
| CN105024701B (en) | A kind of frequency dividing ratio modulator for spurious reduction | |
| CN107565956A (en) | Applied to the VCO frequency bands switching circuit and its loop switching method in double loop clock data recovery circuit | |
| CN104133409A (en) | Triangular wave combining device with adjustable symmetry | |
| CN108540128A (en) | A kind of clock division circuits and its dividing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |