CN104660220A - Signal generator and signal generation method for generating integer frequency pulses - Google Patents
Signal generator and signal generation method for generating integer frequency pulses Download PDFInfo
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- CN104660220A CN104660220A CN201510058501.XA CN201510058501A CN104660220A CN 104660220 A CN104660220 A CN 104660220A CN 201510058501 A CN201510058501 A CN 201510058501A CN 104660220 A CN104660220 A CN 104660220A
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Abstract
The invention discloses a signal generator and a signal generation method for generating integer frequency pulses. The signal generator comprises a detection module, a division module and a waveform generation module which are connected in sequence. The signal generation method comprises the following steps: detecting the state of an input frequency value according to the frequency of a system clock through the signal generator, according to change of the input frequency value, outputting a division enabling signal, after the division module receives the division enabling signal, implementing division calculation on the system clock frequency and the input frequency value, generating the integer frequency pulses which are uniformly distributed within unit time according to the quotient and the remainder, and determining whether the integer frequency pulse signal is output or not according to a pulse output enabling signal. By adopting the signal generator and the signal generation method, conversion of a non-integer period to an integer period can be completed, the problem that non-integer periodic counting can be caused by integer frequency input values under the condition that the frequency of the system clock is fixed can be solved, and the signal generator and the signal generation method have the characteristics of high precision and high easiness in realization.
Description
Technical field
The invention belongs to signal transacting field, more specifically, relate to a kind of signal generator and the signal generating method that produce integer frequency pulse.
Background technology
At present pulse number modulator on the market, produces mainly with the frequency multiplication mode that thinking or counter carry out frequency division output according to weight coefficient that adds up.Although the former design is simple, when frequency control word can not be divided exactly by frequency summary counter, can there is irregular waveform in each clearing moment of frequency accumulator in waveform, can affect the pulse square wave number in the unit interval; Although the design of the latter can export the impulse wave of non-integer clock cycle count, its precision affects comparatively large by reference frequency, for sixteen bit signal generator, if crystal oscillator is 50MHz, is then difficult to produce 2 accurately
16=65536Hz is reference frequency accurately.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of signal generator and the signal generating method that produce integer frequency pulses generation, its object is to carry out the conversion of non-integer to number of cycles, when resolution system clock frequency is fixed thus, integer frequency input value can cause the problem exporting pulse non-integer counting.
For achieving the above object, according to one aspect of the present invention, provide a kind of signal generator producing integer frequency pulse, described signal generator comprises the detection module, dividing module and the waveform generation module that connect successively, and described detection module, dividing module and waveform generation module all receive same clock signal of system;
Incoming frequency value and preset value, for detecting incoming frequency value, compare by detection module, export division enable signal and pulse output enable signal according to comparative result;
Dividing module is used for, under the triggering of division enable signal, the frequency values of clock signal of system and incoming frequency value are carried out division arithmetic, exports business, remainder and division and completes enable signal;
Waveform generation module is used for generating integer frequency pulse signal according to described quotient and the remainder under division completes the triggering of enable signal, and determines whether to export described integer frequency pulse signal according to pulse output enable signal; When the pulse output enable signal received is high level, output pulse signal; When the pulse output enable signal received is low level, stop output pulse signal.
Preferably, detection module export division enable signal and pulse output enable signal be all that high level is effective.
Preferably, detection module is preset with and maximumly allows incoming frequency value f
max; If the incoming frequency value that detection module receives is zero, then pulse output enable signal and division enable signal are low level; If incoming frequency value is greater than 0 and is less than or equal to f
max, then pulse output enable signal and division enable signal are high level.
Preferred further, if the incoming frequency value that detection module receives is greater than f
max, pulse output enable signal and division enable signal are high level and incoming frequency value are considered as invalid input, by f
maxfrequency values as incoming frequency value and clock signal of system carries out division arithmetic.
Further preferred, what detection module was preset maximumly allows incoming frequency value f
maxfor being less than the integer value of system clock frequency.
Preferred further, the integer frequency pulse signal that waveform generation module generates according to described quotient and the remainder is specific as follows: represent business with Q, remainder is represented with R, R the pulse being the count cycle with (Q+1) in the generation unit interval, take Q as (f-R) individual pulse of count cycle, the integer frequency pulse of two kinds of count cycles is uniformly distributed.
For realizing the object of the invention, according to another aspect of the present invention, provide a kind of signal generating method producing integer frequency pulse, described signal generating method adopts the signal generator of generation integer frequency provided by the invention pulse, specific as follows:
(1) judge whether incoming frequency value f is zero, is if so, then set low by pulse output enable signal; If not, then pulse output enable signal is set high, and enter step (2);
(2) judge whether incoming frequency value f exceeds and default maximumly allow incoming frequency value, if not, then generate division enable signal, enter step (3); If so, then incoming frequency value f is considered as invalid input, allows that incoming frequency value is as incoming frequency value using maximum, and generate division enable signal, enter step (3);
(3) after receiving described division enable signal, the frequency values of clock signal of system and incoming frequency value f are carried out division arithmetic, and the frequency values of described clock signal of system makes dividend, obtains business Q, remainder R and division and completes enable signal;
(4) receive after described division completes enable signal, integer frequency pulse signal is produced: the pulse signal generated in the unit interval is divided into two parts according to described business Q and remainder R value, wherein R pulse is using (Q+1) as the count cycle, (f-R) individual pulse is using Q as the count cycle, and the pulse of two kinds of count cycles is uniformly distributed; If pulse output enable signal is high level, then the integer frequency output of pulse signal will produced; If pulse output enable signal is low level, then stop pulse signal exports;
(5) detect incoming frequency value f whether to change, if not, R the pulse being then the count cycle with (Q+1) in the lasting output unit time, take Q as (f-R) individual pulse of count cycle, the pulse of two kinds of count cycles is uniformly distributed; If so, step (1) is then entered.
Preferably, in described step (5), detect incoming frequency value at the rising edge time of clock signal of system or trailing edge moment whether to change, if detect that incoming frequency value f changes at the rising edge time of clock signal of system, then produce input value at the next rising edge time of clock signal of system and change flag bit and enter step (1); If detect that incoming frequency value f changes in the trailing edge moment of clock signal of system, then produce input value in the next trailing edge moment of clock signal of system and change flag bit and enter step (1).
Further preferred, in the vicissitudinous situation of incoming frequency value f, described division enable signal changes flag bit by described pulse output enable signal and input value and carries out logical AND and operate and obtain.
In general, the above technical scheme conceived by the present invention compared with prior art, can obtain following beneficial effect:
(1) because signal generator provided by the invention has carried out the conversion of non-integer to number of cycles according to the result of division arithmetic, therefore no matter can incoming frequency pass through system clock frequency integral frequency divisioil, can continuously number is equal with incoming frequency numerical value in the output unit time at uniform intervals pulse;
(2) the present invention effectively solves under system clock frequency fixing situation, and the problem that integer frequency input value can cause non-integer to count has precision high, is easy to the feature realized.
Accompanying drawing explanation
Fig. 1 is a kind of overall structure block diagram producing the signal generator of integer frequency pulse signal provided by the invention;
Fig. 2 is a kind of main input/output relation connection layout of each intermodule signal producing the signal generator of integer frequency pulse signal that the embodiment of the present invention 1 provides;
Fig. 3 is a kind of flow chart producing the signal generating method of integer frequency pulse signal that the embodiment of the present invention 2 provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
As shown in Figure 1, signal generator of the present invention comprises the detection module, dividing module and the waveform generation module that connect successively; Three modules receive the input of same clock signal of system;
Detection module receives incoming frequency value f, and detect incoming frequency value f, if detect, incoming frequency value is 0, is set low by the pulse output enable signal being sent to waveform generation module; Waveform generation module exports with regard to stop pulse after receiving low level pulse output enable signal; As detected, incoming frequency value is not 0 and changes, then set high by pulse output enable signal, and export division enable signal;
Detection module is preset with maximumly allows incoming frequency value, if incoming frequency value f is greater than and describedly maximumly allows incoming frequency value, is then considered as invalid input, incoming frequency value f is allowed the process of incoming frequency value according to maximum; Describedly maximumly allow that incoming frequency value is the integer value being less than system clock frequency;
Such as, when system clock frequency is 50MHz, allow that incoming frequency value is 500KHz if default maximum, when incoming frequency value is greater than 500KHz, incoming frequency value is considered as invalid input, equals 500KHz according to f and carry out division arithmetic, produce integer frequency pulse signal.
Described dividing module receives division enable signal, carries out the frequency of system clock and the division arithmetic of incoming frequency value, exports business Q, remainder R and division and completes enable signal;
Described waveform generation module completes the triggering of enable signal by division, according to described quotient and the remainder production burst signal, the pulse signal generated in unit interval is divided into two parts, wherein R pulse is using (Q+1) as the count cycle, and (f-R) individual pulse is using Q as the count cycle.
As shown in Figure 2, wherein, Clk is clock signal of system to each intermodule signal annexation of embodiment 1, Rst_n is systematic reset signal, and Div_en is division enable signal, and Div_done is that division completes enabling pulse signal, Run is pulse output enable signal, and pnm is pulse output end mouth;
F is incoming frequency, and incoming frequency value f is with arranging according to demand; The division enable signal Div_en that detection module exports, as the driving enable signal of dividing module;
After dividing module receives division enable signal Div_en, carry out division calculation at the rising edge of next system clock cycle, dividend is the frequency values of the clock signal of system of write dividing module, and divisor is incoming frequency value f;
After dividing module completes division calculation, export division at next system clock cycle rising edge and complete enable signal Div_done, business Q, remainder R; These three signals all input to waveform generation module, complete enabling pulse signal Div_done whenever waveform generation module receives division, then produce integer frequency pulse signal according to corresponding Q, R value received; When the pulse output enable signal that waveform generation module receives is high level, the integer frequency pulse signal generated is exported through pnm port; When the pulse output enable signal received is low level, then stop pulse signal exports.
As shown in Figure 3, the flow process of the signal generating method of the embodiment of the present invention 2 is specific as follows:
(1) judge whether incoming frequency value f is zero, is if so, then set low by pulse output enable signal; If not, then pulse output enable signal is set high, and enter step (2);
(2) judge whether incoming frequency value f exceeds and default maximumly allow incoming frequency value, if not, then generate division enable signal, enter step (3); If so, then incoming frequency value f is considered as invalid input, allows that incoming frequency value is as incoming frequency value using maximum, and generate division enable signal, enter step (3);
(3) after receiving described division enable signal, the frequency values of clock signal of system and incoming frequency value f are carried out division arithmetic, and the frequency values of described clock signal of system makes dividend, obtains business Q, remainder R and division and completes enable signal;
(4) receive after described division completes enable signal, integer frequency pulse signal is produced: the pulse signal generated in the unit interval is divided into two parts according to described business Q and remainder R value, wherein R pulse is using (Q+1) as the count cycle, (f-R) individual pulse is using Q as the count cycle, and the pulse of two kinds of count cycles is uniformly distributed; If pulse output enable signal is high, then the integer frequency output of pulse signal will produced; If pulse output enable signal is low, then stop pulse signal exports;
(5) detect incoming frequency value f whether to change, if not, R the pulse being then the count cycle with (Q+1) in the lasting output unit time, take Q as (f-R) individual pulse of count cycle, the pulse of two kinds of count cycles is uniformly distributed; If so, step (1) is then entered.
Below in conjunction with specific embodiment 1 and embodiment 2, operation principle of the present invention is specifically described below:
When remainder R is non-zero, show that the count cycle of the pulse corresponding to incoming frequency should be and be greater than Q, be less than the decimal of (Q+1), be set to A; The object of the invention is described decimal A to be converted into R integer (Q+1) and (f-R) individual integer Q mean value, i.e. A=[R* (Q+1)+(f-R) Q]/f; R the pulse being the count cycle with (Q+1) in the output unit time, take Q as (f-R) individual pulse of count cycle, the pulse signal of two kinds of count cycles of output is uniformly distributed;
When remainder R is zero, export R the pulse being the count cycle with (Q+1) in the unit interval, take Q as (f-R) individual pulse of count cycle, the pulse signal of two kinds of count cycles of output is uniformly distributed;
If system for use in carrying clock frequency is f
clk, the clock cycle is T
clk;, then the cycle exporting integer frequency pulse signal is: the cycle of R pulse is (Q+1) * T
clk, the cycle of (f-R) individual pulse is Q*T
clk.
The present invention effectively solve system clock signal frequency fixing when, the problem that integer frequency input value can cause non-integer to count.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. one kind produces the signal generator of integer frequency pulse, it is characterized in that, described signal generator comprises the detection module, dividing module and the waveform generation module that connect successively, and described detection module, dividing module and waveform generation module all receive same clock signal of system;
Incoming frequency value and preset value, for detecting incoming frequency value, compare by described detection module, export division enable signal and pulse output enable signal according to comparative result;
Described dividing module is used for, under the triggering of division enable signal, the frequency values of clock signal of system and incoming frequency value are carried out division arithmetic, exports business, remainder and division and completes enable signal;
Described waveform generation module is used for generating integer frequency pulse signal according to described quotient and the remainder under division completes the triggering of enable signal, and determines whether to export described integer frequency pulse signal according to pulse output enable signal.
2. signal generator as claimed in claim 1, it is characterized in that, described division enable signal and pulse output enable signal are all that high level is effective.
3. signal generator as claimed in claim 2, is characterized in that, described detection module is preset with maximumly allows incoming frequency value f
max; If incoming frequency value is zero, then pulse output enable signal and division enable signal are low level; If incoming frequency value is greater than 0 and is less than or equal to f
max, then pulse output enable signal and division enable signal are high level.
4. signal generator as claimed in claim 3, is characterized in that, if incoming frequency value is greater than f
max, pulse output enable signal and division enable signal are high level and incoming frequency value are considered as invalid input, by f
maxfrequency values as incoming frequency value and clock signal of system carries out division arithmetic.
5. the signal generator as described in claim 3 or 4, is characterized in that, describedly maximumly allows incoming frequency value f
maxfor being less than the integer value of system clock frequency.
6. the signal generator as described in any one of claim 1 to 5, it is characterized in that, the integer frequency pulse signal that described waveform generation module generates according to described quotient and the remainder is specific as follows: represent business with Q, remainder is represented with R, R the pulse being the count cycle with (Q+1) in the generation unit interval, take Q as (f-R) individual pulse of count cycle, the integer frequency pulse of two kinds of count cycles is uniformly distributed.
7. adopt a signal generating method for the signal generator described in any one of claim 1 to 6, it is characterized in that, described method is specific as follows:
(1) judge whether incoming frequency value f is zero, is if so, then set low by pulse output enable signal; If not, then pulse output enable signal is set high, and enter step (2);
(2) judge whether incoming frequency value f exceeds and default maximumly allow incoming frequency value, if not, then generate division enable signal, enter step (3); If so, then incoming frequency value f is considered as invalid input, allows that incoming frequency value is as incoming frequency value using maximum, and generate division enable signal, enter step (3);
(3) after receiving described division enable signal, the frequency values of clock signal of system and incoming frequency value f are carried out division arithmetic, and the frequency values of described clock signal of system makes dividend, obtains business Q, remainder R and division and completes enable signal;
(4) receive after described division completes enable signal, integer frequency pulse signal is produced: the pulse signal generated in the unit interval is divided into two parts according to described business Q and remainder R value, wherein R pulse is using (Q+1) as the count cycle, (f-R) individual pulse is using Q as the count cycle, and the pulse of two kinds of count cycles is uniformly distributed; If pulse output enable signal is high level, then the integer frequency output of pulse signal will produced; If pulse output enable signal is low level, then stop pulse signal exports;
(5) detect incoming frequency value f whether to change, if not, R the pulse being then the count cycle with (Q+1) in the lasting output unit time, take Q as (f-R) individual pulse of count cycle, the pulse of two kinds of count cycles is uniformly distributed; If so, step (1) is then entered.
8. signal generating method as claimed in claim 7, it is characterized in that, in described step (5), detect incoming frequency value at the rising edge time of clock signal of system or trailing edge moment whether to change, if detect that incoming frequency value f changes at the rising edge time of clock signal of system, then produce input value at the next rising edge time of clock signal of system and change flag bit and enter step (1); If detect that incoming frequency value f changes in the trailing edge moment of clock signal of system, then produce input value in the next trailing edge moment of clock signal of system and change flag bit and enter step (1).
9. signal generating method as claimed in claim 8, is characterized in that, in the vicissitudinous situation of incoming frequency value f, described division enable signal changes flag bit by described pulse output enable signal and input value and carries out logical AND and operate and obtain.
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Cited By (6)
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| CN105549681A (en) * | 2015-12-22 | 2016-05-04 | 武汉华中数控股份有限公司 | Method and system for accurately outputting pulse number in clock domain crossing manner |
| CN107153352A (en) * | 2017-04-25 | 2017-09-12 | 华南理工大学 | A kind of pulse generation method based on digital frequency synthesis technology |
| CN108055006A (en) * | 2017-12-29 | 2018-05-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
| CN109327210A (en) * | 2018-09-29 | 2019-02-12 | 深圳市新川电气技术有限公司 | Pulse signal production method and device |
| CN110635854A (en) * | 2019-10-24 | 2019-12-31 | 深圳市富满电子集团股份有限公司 | Transmission protocol self-adaptive decoding system and method |
| CN111257628A (en) * | 2020-03-05 | 2020-06-09 | 成都飞机工业（集团）有限责任公司 | Anti-interference method for converting alternating current signal into pulse signal |
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| US20050036564A1 (en) * | 2003-08-14 | 2005-02-17 | Stefan Peter | Method for processing an OFDM signal |
| CN1773980A (en) * | 2004-11-09 | 2006-05-17 | 华为技术有限公司 | Orthogonal frequency division multiplexing integer frequency synchronizing method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105549681A (en) * | 2015-12-22 | 2016-05-04 | 武汉华中数控股份有限公司 | Method and system for accurately outputting pulse number in clock domain crossing manner |
| CN107153352A (en) * | 2017-04-25 | 2017-09-12 | 华南理工大学 | A kind of pulse generation method based on digital frequency synthesis technology |
| CN108055006A (en) * | 2017-12-29 | 2018-05-18 | 成都锐成芯微科技股份有限公司 | A kind of digital frequency multiplier |
| CN109327210A (en) * | 2018-09-29 | 2019-02-12 | 深圳市新川电气技术有限公司 | Pulse signal production method and device |
| CN110635854A (en) * | 2019-10-24 | 2019-12-31 | 深圳市富满电子集团股份有限公司 | Transmission protocol self-adaptive decoding system and method |
| CN111257628A (en) * | 2020-03-05 | 2020-06-09 | 成都飞机工业（集团）有限责任公司 | Anti-interference method for converting alternating current signal into pulse signal |
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