CN102195638A - Low-delay digital clock frequency division method - Google Patents
Low-delay digital clock frequency division method Download PDFInfo
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- CN102195638A CN102195638A CN2011100748998A CN201110074899A CN102195638A CN 102195638 A CN102195638 A CN 102195638A CN 2011100748998 A CN2011100748998 A CN 2011100748998A CN 201110074899 A CN201110074899 A CN 201110074899A CN 102195638 A CN102195638 A CN 102195638A
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- frequency division
- division parameter
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Abstract
The invention discloses a low-delay digital clock frequency division method, which is provided with multistage frequency dividers. Each stage of frequency divider comprises one stage of register and a counting logic device; the multistage frequency dividers are arrayed in a parallel form, namely input clocks of the multistage frequency dividers are all first-stage input clocks; a frequency division parameter change detecting circuit and a frequency division parameter conversion logic circuit are arranged; an XOR circuit is used as the frequency division parameter change detecting circuit, and the output of the circuit is connected with a clearing port of the counting logic device of each stage of the frequency divider; the output of the frequency division parameter conversion logic circuit is connected with a frequency division parameter input end of the counting logic device of each stage of the frequency divider; the frequency division parameters a, b, c, ... of a series structure are converted into the frequency division parameters a, a*b, a*b*c, ..., of a parallel structure; and the frequency division parameters are provided for each stage of the frequency divider, and the multistage frequency division is realized by converting the frequency dividing parameters of each stage after the first stage.
Description
Technical field
The present invention relates to be used for asic chip multi-level clock frequency dividing circuit in the digital integrated circuit field, relate in particular to a kind of low delay digital dock dividing method, more traditional multistage frequency dividing circuit has the advantage of low delay.
Background technology
Along with the high speed development of SoC and asic technology, the complexity and the integrated level of design also increase substantially, and be also just more and more higher for the rate request of circuit.Based on the consideration of power consumption aspect, in the design of complexity, often can use multistage frequency dividing circuit in the synchronous circuit.Traditional multistage frequency divider is simply being in series by the single-stage frequency divider just, be the input clock of the output clock of prime frequency division as back level frequency division, like this, the output clock of afterbody and the input clock of the first order have just differed the register time-delay that number equals frequency divider progression, the frequency division time-delay that will produce what registers of how many levels is arranged, in High Speed System, can become the bottleneck of speed herein, greatly limit the speed of whole system.As shown in Figure 3, with three grades of frequency division structures is example, input clock is through first order frequency divider, the output terminal of clock of first order frequency divider is linked the input end of clock of second level frequency divider, the output terminal of clock of second level frequency divider is linked the input end of clock of third level frequency divider, output clock 1 is than the lagged behind time-delay of a register of input clock like this, and output clock 2 is than the lagged behind time-delay of two registers of input clock, and output clock 3 is than the lagged behind time-delay of three registers of input clock.Obtain the time-delay Delay of afterbody output clock like this with respect to first order input clock
Outclk_nFor:
Delay
Outclk_n=n*Delay (n is a frequency division progression, and Delay is the time-delay of one-level register).
Traditional integer frequency divider is divided into even number divider and frequency division by odd integers device, for the even number Fractional-N frequency, normally realize that by mould N/2 counter a duty ratio is 1: 1 a Fractional-N frequency device, when the automatic negate of frequency division output signal time of counter meter to N/2, for odd number (2N+1) frequency division, typically use that the counter of two moulds (2N+1) finishes, sample with rising edge clock for one, another is sampled with the clock trailing edge, when counter meter the time to N, the result who promptly obtains frequency division by odd integers is done or operated to each counter-rotating of the output signal of two counter correspondences once with two output signals then.Fig. 1 and Fig. 2 are respectively the structural representation of odd even frequency divider and even number divider, as can be seen from the figure two kinds of frequency dividers all drive the one-level register by input clock and obtain exporting clock, the data input pin of this grade register (D end) is controlled by a counter logic, the count value of counter is by the frequency division parameter decision of input, so the output clock is compared the time-delay that has differed a register with input clock.
Summary of the invention
The objective of the invention is to improve, a kind of low delay digital dock dividing method is provided, time-delay is shortened to the time-delay of a register at the shortcoming of the high time-delay of the multistage frequency divider of tradition.
Technical solution of the present invention is as follows: a kind of low delay digital dock dividing method, be provided with multistage frequency divider, frequency dividers at different levels all contain one-level register and a counting logic device, it is characterized in that: multistage frequency divider is arranged with parallel form, the input clock that is multistage frequency divider all is the input clock of the first order, frequency division parameter is set changes testing circuit and frequency division parameter converted logic circuit, frequency division parameter changes testing circuit and adopts XOR circuit, its output connects the zero clearing port of counting logic device in the frequency dividers at different levels respectively, be responsible for the variation of monitoring frequency divider frequency division parameters at different levels, when wherein the one-level frequency division parameter changes arbitrarily, promptly produce the counter O reset signal that is used for frequency dividers at different levels, this signal is through the Synchronous Processing of input clock, with the counter zero clearing simultaneously of all frequency dividers; The output of frequency division parameter converted logic circuit connects the frequency division parameter input of counting logic device in the frequency dividers at different levels, with frequency division parameter a, the b of cascaded structure, c ... convert to parallel-connection structure frequency division parameter a, a*b, a*b*c ... export to frequency dividers at different levels, realize multistage frequency division by the later frequency division parameter step by step of the conversion first order.
Advantage of the present invention and remarkable result: core concept of the present invention is that the plural serial stage frequency divider is become structure in parallel, by the frequency division parameter change-over circuit series multistage frequency division parameter is translated into the frequency division parameter of parallel frequency divider, the time-delay of multistage frequency dividing circuit can be reduced to minimum one-level register time-delay.
Description of drawings
Fig. 1 is existing odd even fraction frequency device schematic diagram;
Fig. 2 is existing even number divider structural representation;
Fig. 3 is traditional multistage fraction frequency device figure;
Fig. 4 is the multistage frequency division system structured flowchart of the present invention;
Fig. 5 is the multistage frequency division system structure chart of the present invention.
Embodiment
Referring to Fig. 4,5, be multistage frequency division structure of the present invention, with three grades of frequency division structures is example, three grades of frequency divisions are arranged with parallel form, promptly the input clock of three grades of frequency dividers all is the input clock of the first order, realize the function of multistage frequency division by two or three grades the frequency division parameter of converting, export clock 1, output clock 2, output clock 3 like this and compare the time-delay of all having only a register with input clock.For example, make up an output clock 1 for input clock 2 frequency divisions, output clock 2 for 6 frequency divisions of input clock with to export clock be 24 frequency divisions of input clock, above-mentioned frequency division value is maximum frequency division value, promptly 2 frequency divisions are adjustable 0,1,2 frequency divisions, and 6 frequency divisions are adjustable 0,1,2,3,4,5,6 frequency divisions.Compare with traditional structure, greatly reduce the time-delay of multistage frequency divider
The multistage frequency division system of the present invention comprises three parts: (1) frequency divider: with three grades is example, the structure of frequency dividers at different levels is identical with existing frequency divider, all contain one-level register and a configurable counter, the structure of existing frequency divider is shown in Fig. 1 (odd even frequency divider) and Fig. 2 (even number divider), the odd even frequency divider is formed the counting logic by register 1 and combinational logic, be connected register 2,3 data input pin (D end), register 2,3 input end of clock connects the reverse of input clock and input clock respectively, register 2,3 output (Q end) be connected or the door input, or the output (Q end) of the output of door and register 2 is connected the input of clock selector 1, the output of clock selector 1 and input clock are connected the input of clock selector 2, and the output of clock selector is the output clock of odd even frequency divider; Even number divider is formed the counting logic by register 1 and combinational logic, be connected the data input pin (D end) of register 2, output of register 2 (Q end) and input clock are connected to the input of clock selector, and the output of clock selector is the output clock of even number divider.(2) frequency division parameter changes testing circuit: be responsible for the variation of monitoring frequency division parameters at different levels, when wherein arbitrarily the one-level frequency division parameter change, generation is used for the counter O reset signal of frequency dividers at different levels, be connected the zero clearing port of counting logical circuit, this signal will be through the Synchronous Processing of input clock, and frequency division parameter changes the available XOR of detection to be realized.The counter O reset signal of Chan Shenging can effectively guarantee like this that with the counter zero clearing simultaneously of all frequency dividers the phase place of frequency division parameter change back frequency divisions output at different levels clocks is consistent herein.(3) frequency division parameter converted logic circuit: the frequency division parameter that is used for the frequency division parameter of cascaded structure is converted to parallel-connection structure, be connected to the frequency division parameter input of counting logical circuit in the frequency dividers at different levels, for frequency division topics at different levels provide frequency division parameter, it is as cost with the number of counter bits that increases back level frequency dividing circuit that design in parallel exchanges low delay for, be that the required counter maximum of current level frequency divider is connected to take advantage of by front all grades counter maximum and obtains, so when sum of series single-stage frequency division parameter is bigger, hardware consumption for counter also is sizable, so the user should take all factors into consideration the compromise of speed and area two aspects.
When the frequency division value of traditional cascaded structure first order is a, second level frequency division value on the basis of the first order is b, and the third level is when frequency division value is c on partial basis ..., the first order frequency division value of parallel-connection structure of the present invention is a, second level frequency division value is a
*B, the third level is a
*b
*C, by that analogy, the frequency division value of afterbody is the product of front all grades frequency division value.A, b, c ... be natural number.
Adopting traditional series multistage fraction frequency device can obtain the circuit of structure as shown in Figure 3, is 2 frequency division frequency dividers as frequency divider 1, and frequency divider 2 is 3 frequency division frequency dividers, and frequency divider 3 is 4 frequency division frequency dividers.The plural parallel stage frequency divider that adopts the present invention to propose, structure is built circuit as shown in Figure 5, frequency divider 1 is 2 frequency division frequency dividers, frequency divider 2 is 6 frequency division frequency dividers, frequency divider 3 is 24 frequency division frequency dividers, input clock is connected on the input end of clock of frequency divider 1,2,3 respectively, and the output clock of frequency divider 1,2,3 is respectively output clock 1, output clock 2 and output clock 3.
Frequency divider 1,2,3 inside all are made of one-level register and a configurable counter, and the maximum count value of frequency divider 1 is 2, and the maximum count value of frequency divider 2 is 6, and the maximum count value of frequency divider 3 is 24.Since traditional habit, general all form configurations in the time of the configuration frequency division value to connect, as, output clock 2 need be 2 frequency divisions of output clock 1, output clock 1 need be 2 frequency divisions of input clock, exports 4 frequency divisions that clock 2 is exactly an input clock so at this moment.The frequency division parameter converted logic is exactly that the configuration parameter of series connection cascade is converted to the configuration parameter of parallel-connection structure, if be fixing frequency division parameter, this part circuit can remove so.In this example, the frequency division parameter 2,3,4 of series multistage divider circuit is converted to the frequency division parameter 2,6,24 (6=2*3,24=2*3*4) of the multistage divider circuit of parallel-connection structure.
Claims (1)
1. low delay digital dock dividing method, be provided with multistage frequency divider, frequency dividers at different levels all contain one-level register and a counting logic device, it is characterized in that: multistage frequency divider is arranged with parallel form, the input clock that is multistage frequency divider all is the input clock of the first order, frequency division parameter is set changes testing circuit and frequency division parameter converted logic circuit, frequency division parameter changes testing circuit and adopts XOR circuit, its output connects the zero clearing port of counting logic device in the frequency dividers at different levels respectively, be responsible for the variation of monitoring frequency divider frequency division parameters at different levels, when wherein the one-level frequency division parameter changes arbitrarily, promptly produce the counter O reset signal that is used for frequency dividers at different levels, this signal is through the Synchronous Processing of input clock, with the counter zero clearing simultaneously of all frequency dividers; Frequency division parameter converted logic circuit output connects the frequency division parameter input of counting logic device in the frequency dividers at different levels, with frequency division parameter a, the b of cascaded structure, c ... convert frequency division parameter a, a of parallel-connection structure to
*B, a
*b
*C ..., export to frequency dividers at different levels, realize multistage frequency division by the later frequency division parameter step by step of the conversion first order.
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| CN2011100748998A CN102195638A (en) | 2011-03-28 | 2011-03-28 | Low-delay digital clock frequency division method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579318A (en) * | 2013-10-21 | 2015-04-29 | 安凯(广州)微电子技术有限公司 | Multichannel clock buffer |
| WO2017121228A1 (en) * | 2016-01-15 | 2017-07-20 | 深圳市中兴微电子技术有限公司 | Method for keeping phases of frequency division clocks consistent and frequency division circuit |
| CN110445492A (en) * | 2019-09-09 | 2019-11-12 | Oppo广东移动通信有限公司 | Cross clock domain frequency-dividing clock protects circuit, frequency dividing circuit, method and terminal device |
| CN111934671A (en) * | 2020-09-14 | 2020-11-13 | 四川科道芯国智能技术股份有限公司 | Multi-frequency-point frequency eliminator and control circuit |
| CN112613260A (en) * | 2020-12-18 | 2021-04-06 | 中国电子科技集团公司第四十七研究所 | Asynchronous clock synchronization constraint method in chip design |
| US11522546B2 (en) | 2020-07-16 | 2022-12-06 | Shenzhen Microbt Electronics Technology Co., Ltd. | Clock tree, hash engine, computing chip, hash board and data processing device |
| CN112613260B (en) * | 2020-12-18 | 2024-04-23 | 中国电子科技集团公司第四十七研究所 | Asynchronous clock synchronization constraint method in chip design |
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| US7359475B2 (en) * | 2005-01-14 | 2008-04-15 | Nec Electronics Corporation | Counter circuit and semiconductor device containing the same |
| CN101291149A (en) * | 2008-06-18 | 2008-10-22 | 北京中星微电子有限公司 | Clock frequency dividing method based on trigger ring and clock frequency dividing circuit thereof |
| CN101330285A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院电子学研究所 | Signal time-delay integrated circuit |
| CN201584959U (en) * | 2009-08-03 | 2010-09-15 | 杭州国芯科技股份有限公司 | Clock circuit for eliminating path time delay |
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| US7359475B2 (en) * | 2005-01-14 | 2008-04-15 | Nec Electronics Corporation | Counter circuit and semiconductor device containing the same |
| US20070159226A1 (en) * | 2006-01-11 | 2007-07-12 | Nobuhiro Hayakawa | Clock generator |
| CN101330285A (en) * | 2007-06-20 | 2008-12-24 | 中国科学院电子学研究所 | Signal time-delay integrated circuit |
| CN101291149A (en) * | 2008-06-18 | 2008-10-22 | 北京中星微电子有限公司 | Clock frequency dividing method based on trigger ring and clock frequency dividing circuit thereof |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104579318A (en) * | 2013-10-21 | 2015-04-29 | 安凯(广州)微电子技术有限公司 | Multichannel clock buffer |
| CN104579318B (en) * | 2013-10-21 | 2018-05-29 | 安凯(广州)微电子技术有限公司 | A kind of multipath clock buffer |
| WO2017121228A1 (en) * | 2016-01-15 | 2017-07-20 | 深圳市中兴微电子技术有限公司 | Method for keeping phases of frequency division clocks consistent and frequency division circuit |
| CN110445492A (en) * | 2019-09-09 | 2019-11-12 | Oppo广东移动通信有限公司 | Cross clock domain frequency-dividing clock protects circuit, frequency dividing circuit, method and terminal device |
| CN110445492B (en) * | 2019-09-09 | 2023-04-07 | Oppo广东移动通信有限公司 | Cross-clock-domain frequency division clock protection circuit, frequency division circuit, method and terminal equipment |
| US11522546B2 (en) | 2020-07-16 | 2022-12-06 | Shenzhen Microbt Electronics Technology Co., Ltd. | Clock tree, hash engine, computing chip, hash board and data processing device |
| TWI804890B (en) * | 2020-07-16 | 2023-06-11 | 大陸商深圳比特微電子科技有限公司 | Clock tree circuits, hash engines, computing chips, hash boards and data processing equipment |
| CN111934671A (en) * | 2020-09-14 | 2020-11-13 | 四川科道芯国智能技术股份有限公司 | Multi-frequency-point frequency eliminator and control circuit |
| CN112613260A (en) * | 2020-12-18 | 2021-04-06 | 中国电子科技集团公司第四十七研究所 | Asynchronous clock synchronization constraint method in chip design |
| CN112613260B (en) * | 2020-12-18 | 2024-04-23 | 中国电子科技集团公司第四十七研究所 | Asynchronous clock synchronization constraint method in chip design |
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Application publication date: 20110921 |