CN101330285A - Signal time-delay integrated circuit - Google Patents
Signal time-delay integrated circuit Download PDFInfo
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- CN101330285A CN101330285A CN 200710117610 CN200710117610A CN101330285A CN 101330285 A CN101330285 A CN 101330285A CN 200710117610 CN200710117610 CN 200710117610 CN 200710117610 A CN200710117610 A CN 200710117610A CN 101330285 A CN101330285 A CN 101330285A
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Abstract
The invention discloses a signal time delay integrated circuit. Input signals of the time delay circuit are respectively connected to a setting terminal of a RS trigger, reset terminals of a frequency division phase and the circuit, and an input terminal of a logic or a gate ; the other input terminal of the logic or gate is connected with a reversal output terminal of the trigger; the output terminal of the logic or the gate is connected to the input terminal of an annular oscillator; the output terminal of the annular oscillator is connected to the clock terminals of the frequency division phase and the circuit; the output terminals of the frequency division phase and the circuit are connected to the reset terminal of the RS trigger; and the positive output terminal of the RS trigger outputs the output signals of the time delay circuit. The signal time delay integrated circuit aims to solve the problem that the territory area of a chip is large. The time delay of tens of milliseconds, in particular to hundreds of milliseconds, can be easily achieved by adopting the time delay circuit under the condition that the smaller territory area of the chip is occupied. Therefore, the time delay circuit is convenient to be integrated with other single chips of other circuits, and particularly needs to integrate a programmable logic device with a microprocessor of the power-up reset circuit.
Description
Technical field
The invention belongs to technical field of integrated circuits, relate to a kind of delay circuit of realizing inhibit signal.
Background technology
Along with the continuous evolution of integrated circuit technique, SOC (system on a chip) SOC technology is arisen at the historic moment, and more circuit need be integrated in the one chip.This circuit that just requires integrated circuit (IC) design person to design takies less chip area as far as possible when realizing function.Because how just to mean higher flow cost with some chip areas.Wherein, delay circuit just need reduce chip area as far as possible when realizing bigger time-delay, and and other chips in circuit be integrated in the one chip.For example, accounting for the larger area delay circuit in the electrification reset chip, can to postpone time of power-on reset signal longer, guarantees chip in the reliable reset system.Yet now a lot of chips need be integrated into the electrify restoration circuit of script as single chip wherein, such as programmable logic device and microprocessor etc.This just need guarantee this chip reliable reset with the delay circuit that can realize enough big time-delay, and the chip layout area that this delay circuit takies can not be too big.
In circuit design, to realize certain time-delay, at first can expect with resistance and capacitance series.Usually in PCB version level circuit design, this method not only simply but also effective.But in integrated circuit (IC) design, if realize bigger time-delay, this but is not a good selection.Mainly be because big time-delay needs very big resistance and electric capacity, and big resistance and electric capacity can take too big chip layout area.
In integrated circuit, realize the time-delay except resistance and electric capacity with little value, can also realize time-delay with the reverser cascade usually.But also only be suitable for realizing less time-delay, normally nanosecond.
Summary of the invention
In order to solve prior art owing to big time-delay needs very big resistance and electric capacity, and big resistance and electric capacity can take the problem of too big chip layout area, the purpose of this invention is to provide a kind of less chip layout area that takies, and can realize the delay circuit form of bigger time-delay, for this reason, the invention provides a kind of signal time-delay integrated circuit of under the limited situation of chip area, realizing.
In order to realize above-mentioned purpose, the technical scheme of a kind of signal time-delay integrated circuit of the present invention comprises:
Circular oscillator, frequency division and circuit, rest-set flip-flop and logic sum gate, wherein:
The input signal of delay circuit is received set end, the frequency division and the clear terminal of circuit and an input of logic sum gate of rest-set flip-flop respectively;
Another input of logic sum gate meets the inverse output terminal Q of trigger;
The output of logic sum gate is received the input ctrl of circular oscillator;
The output of circular oscillator is received the input clk of frequency division and circuit;
Frequency division and the output of circuit are received the reset terminal of rest-set flip-flop;
The output signal S of the positive output end output delay circuit of rest-set flip-flop
Delay
According to embodiments of the invention, described circular oscillator adopts the circular oscillator with the control end whether control vibrate.
According to embodiments of the invention, described circular oscillator comprises: first circular oscillator or second circular oscillator are made up of 2n reverser and 2n+1 electric capacity respectively.
According to embodiments of the invention, described first circular oscillator comprises: 2 input NOR gate, a 2n reverser, and 2n+1 electric capacity, wherein:
The control end the ctrl whether control of first circular oscillator vibrates connects an input of 2 input NOR gate; The output of 2 input NOR gate is received the input of first reverser;
The output of first reverser is received the input of second reverser;
The output of 2n reverser is received another input of 2 input NOR gate;
One of first electric capacity terminates to the output of 2 input NOR gate, and the other end is received ground;
One of second electric capacity terminates to the output of first reverser, and the other end is received ground;
One of 2n+1 electric capacity terminates to the output of 2n reverser, and the other end is received ground;
The output of 2n reverser is the output of circular oscillator.
According to embodiments of the invention, described second circular oscillator, 2 input nand gates, input reverser, a 2n reverser, and 2n+1 electric capacity, wherein:
The input of the control termination input the reverser whether control of second circular oscillator vibrates;
An input of output termination 2 input nand gates of input reverser;
The output of 2 input nand gates is received the input of the 1st reverser;
The output of the 1st reverser is received the input of the 2nd reverser;
The output of 2n reverser is received another input of 2 input nand gates;
One of the 1st electric capacity terminates to the output of 2 input nand gates, and the other end is received ground;
One of the 2nd electric capacity terminates to the output of the 1st reverser, and the other end is received ground;
One of 2n+1 electric capacity terminates to the output of 2n reverser, and the other end is received ground;
The output of 2n reverser is the output of circular oscillator.
According to embodiments of the invention, described frequency division comprises with circuit: N+1 2 input and door, and N+1 d type flip flop with reset terminal, wherein:
Frequency division and the input of circuit are received the reset terminal of N+1 d type flip flop;
The N+1 of N+1 d type flip flop inverse output terminal Q receives its input D respectively accordingly;
Frequency division and the input (clk) of circuit connect the input end of clock of first d type flip flop;
Frequency division and the input (clk) of circuit are received an input of the one 2 input and door again;
Positive output termination the one 2 input of first d type flip flop and another input of door;
The positive output end of first d type flip flop is received the input end of clock of second d type flip flop again;
The output of the one 2 input and door is received an input of the 22 input and door;
Positive output termination the 22 input of second d type flip flop and another input of door;
The positive output end of second d type flip flop is received the input end of clock of 3d flip-flop again;
The output of the 22 input and door is received an input of the 32 input and door;
The positive output end of 3d flip-flop is received another input of the 32 input and door;
The input end of clock of the positive output termination N+1D trigger of ND trigger;
The output of N2 input and door is received an input of N+12 input and door;
The positive output end of N+1D trigger is received another input of N+12 input and door;
N+12 input with output be frequency division and the output of circuit.
According to embodiments of the invention, described electric capacity adopts the equivalent function unit to comprise: the grid oxygen electric capacity of NMOS pipe, wherein, the source electrode of NMOS pipe, drain electrode and substrate connect together as an end of grid oxygen electric capacity, grid is as the other end of grid oxygen electric capacity, or with the grid oxygen electric capacity of PMOS pipe, or the source electrode of PMOS pipe, drain electrode and substrate connect together as an end of grid oxygen electric capacity, and grid is as the other end of grid oxygen electric capacity.
Delay circuit of the present invention is easy to just can realize a few tens of milliseconds under the situation that takies less chip layout area, even up to a hundred milliseconds time-delay.Therefore, this delay circuit is convenient to other circuit single-chips integrated, particularly needs the programmable logic device and the microprocessor of integrated electrify restoration circuit.
Description of drawings
In order to help to understand better the present invention, specific embodiments of the present invention is described below with reference to the accompanying drawings for example, in the accompanying drawings:
Fig. 1 is the schematic diagram according to the delay circuit of embodiment of the present invention;
Fig. 2 A is the schematic diagram that is used in a specific embodiments of the circular oscillator among Fig. 1;
Fig. 2 B is the schematic diagram that is used in another specific embodiments of the circular oscillator among Fig. 1;
Fig. 3 is the schematic diagram that is used in frequency division and a specific embodiments of circuit among Fig. 1;
Fig. 4 A is the sequential chart that adopts delay circuit among the Fig. 1 of the circular oscillator among Fig. 2 A;
Fig. 4 B is the sequential chart that adopts delay circuit among the Fig. 1 of the circular oscillator among Fig. 2 B;
Fig. 5 is a specific embodiments of the equivalent function unit that electric capacity can be replaced among Fig. 2 A and Fig. 2 B.
Specific embodiments
Describe each related detailed problem in the technical solution of the present invention in detail below in conjunction with accompanying drawing.Be to be noted that described embodiment only is intended to be convenient to the understanding of the present invention, and it is not played any qualification effect.
With reference to figure 1, show schematic diagram according to the delay circuit of embodiment of the present invention, delay circuit 10 comprises: circular oscillator 12, frequency division and circuit 14, rest-set flip-flop 16 with the control end whether control vibrate, and 2 input logic or the door 18, wherein, has the schematic diagram of the schematic diagram of a specific embodiments of circular oscillator 12 of the control end whether control vibrate and another specific embodiments respectively as Fig. 2 A and Fig. 2 B.Schematic diagram such as Fig. 3 of frequency division and a specific embodiments of circuit 14.Rest-set flip-flop 16 is specific embodiments with trigger of set/reset end, also can replace with other trigger with set/reset end, for example have the set/reset end d type flip flop, have the T trigger of set/reset end, and have JK flip-flop of set/reset end etc.The input signal S of delay circuit 10
HLMeet the set end S of rest-set flip-flop 16.The input signal S of delay circuit 10
HLReceive the input clr of frequency division and circuit 14 again.An input termination input signal S of 2 inputs or door 18
HL, the inverse output terminal Q of another input termination rest-set flip-flop 16.Or the output of door 18 is received the input ctrl of circular oscillator 12.The Ausgang of circular oscillator 12 is received the input clk of frequency division and circuit 14.Frequency division and the output out of circuit 14 receive the reset terminal R of rest-set flip-flop 16.The positive output end Q of rest-set flip-flop 16 meets the output signal S of delay circuit 10
Delay
When delay circuit 10 is started working among Fig. 1, the input signal S of trailing edge is arranged
HLBe high level 1, make rest-set flip-flop 16 put down 1 to positive output end Q set for high point, just the output signal S of delay circuit 10
DelayBe changed to high level 1.Simultaneously, input signal S
HLThe high level 1 input clr by frequency division and circuit 14 its output out zero clearing, just the reset terminal R of rest-set flip-flop 16 is a low level 0.Then, trailing edge input signal S
HLBecome low level 0, the square-wave signal f of circular oscillator 12 starting oscillations output some cycles.Signal f is through one of frequency division and the circuit 14 output input signal S with delay circuit 10
HLThe rising edge signal R that very big time-delay is arranged.The high level 1 of this signal R makes rest-set flip-flop 16 be reset to low level 0 to positive output end Q, just the output signal S of delay circuit 10
DelayBe reset to low level 0.Like this, signal S
HLOutput signal S after delay circuit 10 postpones a period of times just
Delay
Fig. 2 A is the schematic diagram that is used in a specific embodiments of the circular oscillator 12 among Fig. 1.In Fig. 2 A, circular oscillator 20A comprises: be made up of 2n reverser and 2n+1 electric capacity, n=1,2,3 ... adopt n=1 in the present embodiment, other is not described in detail at this promptly 2 input NOR gate 21, first reverser 23 and second reversers 25, and the first electric capacity 27a, the second electric capacity 27b and the 3rd electric capacity 27c.Wherein, the input ctrl of circular oscillator 20A connects an input of 2 input NOR gate 21.The output of 2 input NOR gate 21 is received the input of first reverser 23.The output of first reverser 23 is received the input of second reverser 25.The output of second reverser 25 is received another input of 2 input NOR gate 21.One of the first electric capacity 27a terminates to the output of 2 input NOR gate 21, and the other end receives ground.One of the second electric capacity 27b terminates to the output of first reverser 23, and the other end receives ground.One of the 3rd electric capacity 27c terminates to the output of second reverser 25, and the other end receives ground.The output out of the output T-Ring line oscillator 20A of second reverser 25.The embodiment that n equals other situation is not described in detail at this.
When input ctrl was high level 1 among Fig. 2 A, each node was a fixed level among the circular oscillator 20A.When ctrl is low level 0, circular oscillator 20A starting oscillation.In addition, the reverser number among the circular oscillator 20A also can be 4,6 or more a plurality of, but must be even number.Accordingly, the number of the capacitive load of these reverser outputs also can be 4,6 or more a plurality of, but must be even number.
Fig. 2 B is the schematic diagram that is used in another specific embodiments of the circular oscillator 12 among Fig. 1.In Fig. 2 B, circular oscillator 20B comprises: be made up of 2n reverser and 2n+1 electric capacity, n=1,2,3 ... adopt n=1 in the present embodiment, 2 input nand gate the 22, the 1st reverser the 24, the 2nd reversers 26 and input reverser 29 are promptly arranged, and the 1st electric capacity 28a, the 2nd electric capacity 28b and the 3rd electric capacity 28c.Wherein, the input ctrl of circular oscillator 20B connects the input of input reverser 29.An input of output termination 2 input nand gates 22 of input reverser 29.The output of NAND gate 22 is received the input of the 1st reverser 24.The output of the 1st reverser 24 is received the input of the 2nd reverser 26.The output of the 2nd reverser 26 is received another input of 2 input nand gates 22.One of the 1st electric capacity 28a terminates to the output of 2 input nand gates 22, and the other end receives ground.One of the 2nd electric capacity 28b terminates to the output of the 1st reverser 24, and the other end receives ground.One of electric capacity 28c terminates to the output of the 2nd reverser 26, and the other end receives ground.The output out of the output T-Ring line oscillator 20B of the 2nd reverser 26.The embodiment that n equals other situation is not described in detail at this.
When input ctrl was high level 1 among Fig. 2 B, each node was a fixed level among the circular oscillator 20B.When ctrl is low level 0, circular oscillator 20B starting oscillation.In addition, do not comprise among the circular oscillator 20B that reverser 29 outer reverser numbers also can be 4,6 or more a plurality of, but must be even number.Accordingly, the number of the capacitive load of these reverser outputs also can be 4,6 or more a plurality of, but must be even number.
In actual design, the number of reverser can be twenties or thirties among circular oscillator 20A or the circular oscillator 20B, but need be even number.The cycle of the square wave that circular oscillator 20A or circular oscillator 20B produce is driven the propagation delay decision of load capacitance and NOR gate inclusive NAND door driving load capacitance by reverser.By adopting suitable reverser number and selecting suitable capacitance to determine the cycle of the square wave that will produce.
Fig. 3 is the schematic diagram that is used in frequency division and a specific embodiments of circuit among Fig. 1.In Fig. 3, frequency division comprises with circuit 30: N+1 2 input and door, and N+1 the d type flip flop with reset terminal, N=1,2,3 ... adopt N=2 in the present embodiment, promptly present embodiment adopts: import and door for 32, and 3 d type flip flops with reset terminal.Wherein, frequency division and the input clr of circuit 30 receive the reset terminal CLR of first d type flip flop 32, second d type flip flop 34 and 3d flip-flop 36 respectively.The inverse output terminal Q of first d type flip flop 32, second d type flip flop 34 and 3d flip-flop 36 receives its input D respectively accordingly.Frequency division and the input clk of circuit 30 connect the input end of clock of first d type flip flop 32.The input clk of frequency division and circuit 30 receives an input of the one 2 input and door 31 again.The positive output end Q of first d type flip flop 32 (being q1) connects the input end of clock of second d type flip flop 34.The positive output end Q of first d type flip flop 32 receives another input of the one 2 input and door 31 again.The output of the one 2 input and door 31 is received an input of the 22 input and door 33.The positive output end Q of second d type flip flop 34 (being q2) connects the input end of clock of 3d flip-flop 36.The positive output end Q of second d type flip flop 34 receives another input of the 22 input and door 33 again.The output of the 22 input and door 33 is received an input of 2 inputs and door 35.The positive output end Q of 3d flip-flop 36 (being q3) receives another input of the 32 input and door 35.The 32 input and the output termination frequency division of door 35 and the output out of circuit 30.
Among Fig. 3, the number with d type flip flop of reset terminal also can be 1,2, also can be 4,5 or more a plurality of.Accordingly, 2 inputs also can be 1,2 with the number of door, also can be 4,5 or more a plurality of.
All d type flip flops shown in Figure 3 all have set end and reset terminal.But owing to do not use the set end in this embodiment, so also can adopt the d type flip flop structure that only has reset terminal.Be that function of the present invention is not subjected to the concrete structure of the d type flip flop that adopted and realizes the restriction of logic.In addition, the inverse output terminal Q of d type flip flop meets its input D among Fig. 3, and the functional equivalent of this connection connects high level 1 in the input T of T trigger.Therefore, can replace.
In the integrated circuit (IC) design based on standard CMOS process, the reverser among Fig. 2 A and Fig. 2 B is made up of a PMOS pipe and a NMOS pipe.NOR gate among Fig. 2 A is made up of two PMOS pipes and two NMOS pipes.NAND gate among Fig. 2 B is made up of two PMOS pipes and two NMOS pipes.Among Fig. 1 or Men Youyi NOR gate and a reverser form.Rest-set flip-flop among Fig. 1 can be made up of two NOR gate, also can be made up of two NAND gate and two reversers.Forming among Fig. 3 with Men Youyi NAND gate and a reverser.The d type flip flop of the band reset terminal among Fig. 3 can be made up of gate, also can be made up of transmission gate and gate, also can be made up of variable connector and gate.Transmission gate by a PMOS manage, NMOS pipe and a reverser form.Variable connector can be made up of gate, also can be made up of transmission gate, also can be directly with NMOS pipe and reverser or PMOS pipe and reverser realization.
Fig. 4 A is the sequential chart that adopts delay circuit among the Fig. 1 of the circular oscillator among Fig. 2 A.From Fig. 4 A as can be seen, signal S during beginning
HLBe high level 1, rest-set flip-flop 16 is set among Fig. 1, and output Q is a high level 1, and Q is a low level 0.Wherein, signal Q promptly is the signal S that is delayed
DelaySo, signal S
HLWith Q through or door 18 to make signal ctrl be high level 1.When signal ctrl was high level 1, the output signal f of ring oscillator 20A was a low level 0 among Fig. 2 A.Simultaneously, signal S
HLHigh level 1 positive output end q1, the q2 of d type flip flop among Fig. 3 32,34 and 36 and q3 zero clearing.Like this, signal f is low level 0 with signal q1 with making o1.Signal o1 is low level 0 with signal q2 with making o2.Signal o2 is low level 0 with signal q3 with the reset terminal R that makes rest-set flip-flop 16.Then, signal S
HLBecome low level 0, the set end S of rest-set flip-flop 16 is a low level 0 just also.Because this moment, the reset terminal R of rest-set flip-flop 16 still was 0, so the output end signal of rest-set flip-flop 16 remains unchanged Q (S
Delay) still be 1, Q still is 0.Like this, signal ctrl just becomes low level 0, ring oscillator 20A starting oscillation.When signal ctrl was 0, ring oscillator 20A produced the square-wave signal f of some cycles.Frequency division produces 2 fractional frequency signal q1,4 fractional frequency signal q2 and 8 fractional frequency signal q3 with circuit 30 among signal f input Fig. 3.Signal f and signal q1 and output o1.Signal o1 and signal q2 and output o2.Signal o2 and signal q3 and one of output and signal S
HLTrailing edge the high level pulse signal R of certain time-delay is arranged.This high level pulse R resets rest-set flip-flop 16.Q (S
Delay) end becomes low level 0, signal S
HLOutput signal S after Fig. 1 delay circuit 10 postpones a period of times just
DelaySimultaneously, the Q end becomes 1, makes the ctrl signal become 1, the ring oscillator 20A failure of oscillations.
The time of delay of being realized among Fig. 4 A can be by formula (2
m-0.5) * T
AProvide.Wherein, m be Fig. 3 frequency division with circuit 30 in realize the number of the d type flip flop of frequency division.T
AIt is the cycle of the square-wave signal of circular oscillator 20A output among Fig. 2 A.
Fig. 4 B is the sequential chart that adopts delay circuit among the Fig. 1 of the circular oscillator among Fig. 2 B.From Fig. 4 B as can be seen, signal S during beginning
HLBe high level 1, rest-set flip-flop 16 is set among Fig. 1, and output Q is a high level 1, and Q is a low level 0.Wherein, signal Q promptly is the signal S that is delayed
DelaySo, signal S
HLWith Q through or door 18 to make signal ctrl be high level 1.When signal ctrl was high level 1, the output signal f of ring oscillator 20B was a high level 1 among Fig. 2 B.Simultaneously, signal S
HLHigh level 1 positive output end q1, the q2 of d type flip flop among Fig. 3 32,34 and 36 and q3 zero clearing.Like this, signal f is low level 0 with signal q1 with making o1.Signal o1 is low level 0 with signal q2 with making o2.Signal o2 is low level 0 with signal q3 with the reset terminal R that makes rest-set flip-flop 16.Then, signal S
HLBecome low level 0, the set end S of rest-set flip-flop 16 is a low level 0 just also.Because this moment, the reset terminal R of rest-set flip-flop 16 still was 0, so the output end signal of rest-set flip-flop 16 remains unchanged Q (S
Delay) still be 1, Q still is 0.Like this, signal ctrl just becomes low level 0, ring oscillator 20B starting oscillation.When signal ctrl was 0, ring oscillator 20B produced the square-wave signal f of some cycles.Frequency division produces 2 fractional frequency signal q1,4 fractional frequency signal q2 and 8 fractional frequency signal q3 with circuit 30 among signal f input Fig. 3.Signal f and signal q1 and output o1.Signal o1 and signal q2 and output o2.Signal o2 and signal q3 and one of output and signal S
HLTrailing edge the rising edge signal R of certain time-delay is arranged.The high level 1 of this signal R resets rest-set flip-flop 16.Q (S
Delay) end becomes low level 0, signal S
HLOutput signal S after Fig. 1 delay circuit 10 postpones a period of times just
DelaySimultaneously, the Q end becomes 1, makes the ctrl signal become 1, the ring oscillator 20B failure of oscillations.
The time of delay of being realized among Fig. 4 B can be by formula (2
m-1) * T
BProvide.Wherein, m be Fig. 3 frequency division with circuit 30 in realize the number of the d type flip flop of frequency division.T
BIt is the cycle of the square-wave signal of circular oscillator 20B output among Fig. 2 B.
It among Fig. 5 a specific embodiments of the equivalent function unit that electric capacity can be replaced among Fig. 2 A and Fig. 2 B.Be to utilize the grid oxygen electric capacity of NMOS pipe 56 can replace general electric capacity 52 among Fig. 5.Wherein, source electrode, drain electrode and the substrate of NMOS pipe 56 connect together as an end of grid oxygen electric capacity, and grid is as the other end of grid oxygen electric capacity.Certainly, also can replace general electric capacity 52 with the grid oxygen electric capacity of PMOS pipe.Equally, also be that source electrode, drain electrode and the substrate of PMOS pipe connects together as an end of grid oxygen electric capacity, grid is as the other end of grid oxygen electric capacity.
The present invention is not subjected to the restriction of specific implementation method of circuit and the restriction of the logical form that circuit is adopted, and for example, all bottom circuit can be the CMOS technology of standard or other technology.
The above; only be the embodiment among the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with the people of this technology in the disclosed technical scope of the present invention; can understand conversion or the replacement expected; all should be encompassed in of the present invention comprising within the scope, therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (7)
1, a kind of signal time-delay integrated circuit is characterized in that, comprising: circular oscillator (12), frequency division and circuit (14), rest-set flip-flop (16) and logic sum gate (18), wherein:
Input signal (the S of delay circuit (10)
HL) receive set end (S), the frequency division and the clear terminal (clr) of circuit (14) and an input of logic sum gate (18) of rest-set flip-flop (16) respectively;
The inverse output terminal (Q) of another input termination (RS) trigger (16) of logic sum gate (18);
The output of logic sum gate (18) is received the input (ctrl) of circular oscillator (12);
The output (f) of circular oscillator (12) is received the input (clk) of frequency division and circuit (14);
Frequency division is received the reset terminal (R) of rest-set flip-flop (16) with the output (out) of circuit (14);
Output signal (the S of positive output end (Q) the output delay circuit (10) of rest-set flip-flop (16)
Delay).
2, signal time-delay integrated circuit according to claim 1 is characterized in that, described circular oscillator (12) adopts the circular oscillator with the control end whether control vibrate.
3, signal time-delay integrated circuit according to claim 1 is characterized in that, described circular oscillator (12) comprising: first circular oscillator (20A) or second circular oscillator (20B) are made up of 2n reverser and 2n+1 electric capacity respectively.
4, signal time-delay integrated circuit according to claim 3 is characterized in that, described first circular oscillator (20A) comprising:
2 input NOR gate, a 2n reverser, and 2n+1 electric capacity, wherein:
The control end whether control of first circular oscillator vibrates (ctrl) connects an input of 2 input NOR gate; The output of 2 input NOR gate is received the input of first reverser;
The output of first reverser is received the input of second reverser;
The output of 2n reverser is received another input of 2 input NOR gate;
One of first electric capacity terminates to the output of 2 input NOR gate, and the other end is received ground;
One of second electric capacity terminates to the output of first reverser, and the other end is received ground;
One of 2n+1 electric capacity terminates to the output of 2n reverser, and the other end is received ground;
The output of 2n reverser is the output of circular oscillator.
5, signal time-delay integrated circuit according to claim 3 is characterized in that, described second circular oscillator (20B) comprising:
2 input nand gates, input reverser, a 2n reverser, and 2n+1 electric capacity, wherein:
The control end whether control of second circular oscillator vibrates (ctrl) connects the input of input reverser;
An input of output termination 2 input nand gates of input reverser;
The output of 2 input nand gates is received the input of the 1st reverser;
The output of the 1st reverser is received the input of the 2nd reverser;
The output of 2n reverser is received another input of 2 input nand gates;
One of the 1st electric capacity terminates to the output of 2 input nand gates, and the other end is received ground;
One of the 2nd electric capacity terminates to the output of the 1st reverser, and the other end is received ground;
One of 2n+1 electric capacity terminates to the output of 2n reverser, and the other end is received ground;
The output of 2n reverser is the output of circular oscillator.
6, signal time-delay integrated circuit according to claim 1 is characterized in that, described frequency division comprising with circuit (30): N+1 2 input and door, and N+1 d type flip flop with reset terminal, wherein:
Frequency division and the input (clr) of circuit (30) are received the reset terminal (CLR) of N+1 d type flip flop;
The N+1 of a N+1 d type flip flop inverse output terminal (Q) is received its input (D) respectively accordingly;
Frequency division and the input (clk) of circuit connect the input end of clock of first d type flip flop;
Frequency division and the input (clk) of circuit are received an input of the one 2 input and door again;
Positive output termination the one 2 input of first d type flip flop and another input of door;
The positive output end of first d type flip flop is received the input end of clock of second d type flip flop again;
The output of the one 2 input and door is received an input of the 22 input and door;
Positive output termination the 22 input of second d type flip flop and another input of door;
The positive output end of second d type flip flop is received the input end of clock of 3d flip-flop again;
The output of the 22 input and door is received an input of the 32 input and door;
The positive output end of 3d flip-flop is received another input of the 32 input and door;
The input end of clock of the positive output termination N+1 d type flip flop of ND trigger;
The output of N2 input and door is received an input of N+1 2 inputs and door;
The positive output end of N+1 d type flip flop is received another input of N+1 2 inputs and door;
N+1 2 input with output be frequency division and the output of circuit.
7, according to claim 3 or 4 or 5 described signal time-delay integrated circuits, it is characterized in that, described electric capacity adopts the equivalent function unit to comprise: the grid oxygen electric capacity of NMOS pipe (56), wherein, source electrode, drain electrode and the substrate of NMOS pipe (56) connect together as an end of grid oxygen electric capacity, grid is as the other end of grid oxygen electric capacity, or with the grid oxygen electric capacity of PMOS pipe, or the source electrode of PMOS pipe, drain electrode and substrate connect together as an end of grid oxygen electric capacity, and grid is as the other end of grid oxygen electric capacity.
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| CN 200710117610 CN101330285B (en) | 2007-06-20 | 2007-06-20 | Signal time-delay integrated circuit |
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| CN 200710117610 CN101330285B (en) | 2007-06-20 | 2007-06-20 | Signal time-delay integrated circuit |
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| CN101286735B (en) * | 2008-05-29 | 2010-06-02 | 锐迪科微电子（上海）有限公司 | Delay device of reset signal |
| CN102195638A (en) * | 2011-03-28 | 2011-09-21 | 东南大学 | Low-delay digital clock frequency division method |
| CN102729887A (en) * | 2012-07-11 | 2012-10-17 | 重庆三信电子股份有限公司 | Special integrated circuit for vehicle flasher |
| CN104539272A (en) * | 2014-11-27 | 2015-04-22 | 英业达科技有限公司 | Computer system provided with wake-up circuit |
| CN105262462A (en) * | 2015-10-21 | 2016-01-20 | 圣邦微电子（北京）股份有限公司 | Digital delay implementation method for integrated circuit and circuit |
| CN107040246A (en) * | 2017-06-05 | 2017-08-11 | 深圳市国芯盟科技有限公司 | Bilateral delay circuit, chip with dynamic function of reset |
| CN108233905A (en) * | 2016-12-14 | 2018-06-29 | 电信科学技术研究院 | Electrification reset circuit and supply unit |
| WO2020024149A1 (en) * | 2018-08-01 | 2020-02-06 | Micron Technology, Inc. | Semiconductor device, delay circuit, and related method |
| CN112615589A (en) * | 2020-12-15 | 2021-04-06 | 海光信息技术股份有限公司 | Method and device for adjusting frequency of ring oscillator, storage medium and equipment |
| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
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| US5373535A (en) * | 1993-03-31 | 1994-12-13 | Intel Corporation | Method and apparatus for digitally compensating digital clock skew for high speed digital circuits |
| CN1155949A (en) * | 1995-05-31 | 1997-07-30 | 塞瑞斯逻辑公司 | Voltage controlled oscillator including voltage controlled delay circuit with power supply noise isolation |
| TW449976B (en) * | 1998-08-11 | 2001-08-11 | Toshiba Corp | Pulse width modulation waveform generation circuit |
| ATE311039T1 (en) * | 2000-06-28 | 2005-12-15 | Thomson Licensing | HIGH FREQUENCY OSCILLATOR |
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| CN105262462B (en) * | 2015-10-21 | 2018-03-20 | 圣邦微电子（北京）股份有限公司 | A kind of digital delay implementation method and circuit for integrated circuit |
| CN105262462A (en) * | 2015-10-21 | 2016-01-20 | 圣邦微电子（北京）股份有限公司 | Digital delay implementation method for integrated circuit and circuit |
| CN108233905A (en) * | 2016-12-14 | 2018-06-29 | 电信科学技术研究院 | Electrification reset circuit and supply unit |
| CN107040246A (en) * | 2017-06-05 | 2017-08-11 | 深圳市国芯盟科技有限公司 | Bilateral delay circuit, chip with dynamic function of reset |
| WO2020024149A1 (en) * | 2018-08-01 | 2020-02-06 | Micron Technology, Inc. | Semiconductor device, delay circuit, and related method |
| CN112438020A (en) * | 2018-08-01 | 2021-03-02 | 美光科技公司 | Semiconductor device, delay circuit and related method |
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| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
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| CN112615589A (en) * | 2020-12-15 | 2021-04-06 | 海光信息技术股份有限公司 | Method and device for adjusting frequency of ring oscillator, storage medium and equipment |
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Effective date of registration: 20210421 Address after: Room 705, 7 / F, building nw-01, Northwest District, nano City, No. 99, Jinjihu Avenue, Suzhou Industrial Park, Suzhou City, Jiangsu Province, 215028 Patentee after: EHIWAY MICROELECTRONIC TECHNOLOGY (SUZHOU) Co.,Ltd. Address before: 100080, No. 19 West Fourth Ring Road, Beijing, Haidian District Patentee before: Institute of Electronics, Chinese Academy of Sciences |