CN112825479A - Delay circuit and chip - Google Patents
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- CN112825479A CN112825479A CN201911142942.2A CN201911142942A CN112825479A CN 112825479 A CN112825479 A CN 112825479A CN 201911142942 A CN201911142942 A CN 201911142942A CN 112825479 A CN112825479 A CN 112825479A
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- 230000007306 turnover Effects 0.000 claims abstract description 10
- 230000000630 rising effect Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 18
- 230000003111 delayed effect Effects 0.000 description 13
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
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Abstract
The invention discloses a delay circuit and a chip. The delay circuit includes: delay means and control means; the first control input end of the control device is connected with the signal detection end of the delay device, the second control input end of the control device is connected with the input end of the delay device and then receives an input signal, and the control output end of the control device is connected with the signal control end of the delay device; the control device is used for adjusting a control signal output to the signal control end according to an input signal when a first voltage signal detected by the first control input end reaches a first overturning voltage of the control device, wherein the first overturning voltage is larger than a second overturning voltage of the output end of the delay device; the delay device is used for adjusting the first voltage signal based on the control signal and the input signal and delaying the output input signal based on the adjusted first voltage signal and the second turnover voltage. The delay circuit can delay the output time of the input signal, and the problem of large chip layout area caused by increasing the resistance value of the resistor and/or the capacitance value of the capacitor is avoided.
Description
Technical Field
The embodiment of the invention relates to the technical field of sequential circuits, in particular to a delay circuit and a chip.
Background
RC delay circuits are common blocks in integrated circuit design and are commonly used for the delay of timing signals. For example, RC delay circuits are often integrated in the chip to achieve the delay of the timing signals.
The delay time of the RC delay circuit is proportional to the product of the resistance and capacitance (R × C). If the delay time of the RC delay circuit is to be increased, the resistance of the resistor and/or the capacitance of the capacitor in the RC delay circuit are/is increased.
However, the resistor and the capacitor occupy a large volume on the chip layout, and if the delay time is increased by increasing the resistance value of the resistor and/or the capacitance value of the capacitor in the RC delay circuit, a large amount of chip layout area is inevitably consumed, thereby increasing the chip cost.
Disclosure of Invention
The embodiment of the invention provides a delay circuit and a chip, and aims to solve the technical problem that the area consumption of a chip layout is large when the delay time is increased by increasing the resistance value of a resistor and/or the capacitance value of a capacitor in an RC delay circuit.
In a first aspect, an embodiment of the present invention provides a delay circuit, including:
the first control input end of the control device is connected with the signal detection end of the delay device, the second control input end of the control device is connected with the input end of the delay device and then receives an input signal, and the control output end of the control device is connected with the signal control end of the delay device;
the control device is configured to adjust a control signal output to the signal control terminal according to the input signal when a first voltage signal detected by the first control input terminal reaches a first inversion voltage of the control device, where the first inversion voltage is greater than a second inversion voltage of the output terminal of the delay device;
the delay device is used for adjusting the first voltage signal based on the control signal and the input signal and delaying and outputting the input signal based on the adjusted first voltage signal and the second turnover voltage.
Optionally, the control device includes:
the first RS trigger is composed of a NAND gate;
the reset input end of the first RS trigger is connected with the signal detection end, the set input end receives the input signal, the Q non-output end is connected with the signal control end or the Q output end is connected with the signal control end through a first phase inverter.
Optionally, the control device further includes:
a second inverter and a third inverter;
the input end of the second phase inverter is connected with the signal detection end, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is connected with the reset input end.
Optionally, the control device includes:
a second RS trigger, a fourth inverter and a fifth inverter which are composed of NOR gates;
the input end of the fourth phase inverter is connected with the signal detection end, the output end of the fourth phase inverter is connected with the reset input end of the second RS trigger, the input end of the fifth phase inverter receives the input signal, the output end of the fifth phase inverter is connected with the set input end of the second RS trigger, and the output end of the second RS trigger is connected with the signal control end.
Optionally, the delay device is an RC delay device.
Optionally, the RC delay device includes: the input inverter, the output inverter, the resistor and the capacitor;
the input end of the input phase inverter is connected with the second control input end, the output end of the input phase inverter is connected with one end of the resistor, the other end of the resistor is respectively connected with one end of the capacitor, the first control input end and the input end of the output phase inverter, and the other end of the capacitor is connected with the control output end.
Optionally, the input inverter is configured to adjust a second voltage signal at one end of the resistor according to the input signal;
the resistor and the capacitor adjust the first voltage signal based on the second voltage signal and the control signal.
Optionally, the delay time of the rising edge of the delay circuit is adjusted by changing the first flip voltage and the voltage to which the first voltage signal is pushed.
Optionally, the delay time of the falling edge of the delay circuit is a time when the first voltage signal rises from a negative voltage to the second flip-flop voltage.
Optionally, the equivalent capacitance of the delay circuit is determined according to the first flipping voltage and the second flipping voltage.
In a second aspect, an embodiment of the present invention further provides a chip, including: such as the delay circuit provided by the embodiments of the present invention.
The embodiment of the invention provides a delay circuit and a chip, wherein the delay circuit comprises a delay device and a control device, and a first voltage signal of a signal detection end of the delay device is monitored by connecting a first control input end of the control device with the signal detection end of the delay device. And when the first voltage signal reaches the first turnover voltage of the control device, adjusting the control signal output to the signal control end according to the input signal. The voltage value of the first voltage signal at the signal detection end of the delay device can be adjusted by the input signal and the control signal. The delay means is capable of delaying the output input signal based on the adjusted first voltage signal and the second switching voltage. According to the technical scheme, when the first turnover voltage of the control device reaches, the control device adjusts the control signal output to the signal control end according to the input signal so as to adjust the voltage value of the first voltage signal used for controlling the output signal in the delay device, wherein the output signal can be regarded as the input signal of delay output, so that the time of the first voltage signal reaching the second turnover voltage is delayed, the output time of the input signal is further delayed, and the problem that the chip layout area is large due to the fact that the resistance value of a resistor and/or the capacitance value of a capacitor are/is increased is avoided. The first switching voltage is greater than the second switching voltage, so that the first voltage signal of the delay device is adjusted by the control device, and then the output of the input signal is controlled based on the first voltage signal.
Drawings
Fig. 1 is a schematic structural diagram of a delay circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a delay circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a delay circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a delay circuit according to another embodiment of the present invention;
FIG. 5 is an operational timing diagram corresponding to the connection diagram of the delay circuit of FIG. 4;
FIG. 6 is a schematic diagram of a prior art delay circuit connection;
FIG. 7 is a timing diagram corresponding to the delay circuit shown in FIG. 6;
fig. 8 is a schematic connection diagram of another delay circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Examples
Fig. 1 is a schematic structural diagram of a delay circuit according to an embodiment of the present invention, where the delay circuit is suitable for a situation where a timing signal is output in a delayed manner, and the timing circuit may be integrated on a chip for outputting a timing signal in a delayed manner, such as integrating the timing circuit on a timing control chip.
As shown in fig. 1, an embodiment of the present invention provides a delay circuit, including:
delay means 11 and control means 12;
a first control input end of the control device 12 is connected with the signal detection end of the delay device 11, a second control input end of the control device is connected with the input end of the delay device 11 and then receives an input signal, and a control output end of the control device is connected with the signal control end of the delay device 11;
a control device 12, configured to adjust a control signal output to the signal control terminal according to an input signal when a first voltage signal detected by the first control input terminal reaches a first inversion voltage of the control device 12, where the first inversion voltage is greater than a second inversion voltage of the output terminal of the delay device 11;
and a delay device 11 for adjusting the first voltage signal based on the control signal and the input signal, and delaying the output input signal based on the adjusted first voltage signal and the second inversion voltage.
In this embodiment, the operating principle of the delay circuit is: the delay device 11 adjusts a first voltage signal of the signal detection terminal according to the input signal received by the input terminal, and the first voltage signal can control the output terminal to delay the output input signal. A first control input of the control means 12 is connected to the signal detection terminal for monitoring a first voltage signal at the signal detection terminal of the delay means 11. When the first voltage signal reaches the first switching voltage of the control means 12, a control signal is output via the control output to the signal control terminal of the delay means 11. The voltage value of the first voltage signal at the signal detection terminal of the delay means 11 can be adjusted by the input signal and the control signal. The delay means 11 is capable of delaying the output input signal based on the adjusted first voltage signal and the second switching voltage. Thereby delaying the time when the first voltage signal reaches the second inversion voltage, and further delaying the output time of the output signal. The first switching voltage being larger than the second switching voltage ensures that the first voltage signal of the delay means 11 is first adjusted by the control means 12 and the output of the input signal is then controlled on the basis of the first voltage signal.
In the present embodiment, the delay device 11 can be understood as a device that delays an input signal to an output terminal. The delay device 11 includes an input end for inputting an input signal, a signal control end for receiving a control signal to adjust a first voltage signal of the delay device 11, a signal detection end for the control module to perform signal detection, and an output end for performing signal output based on the first voltage signal.
The control device 12 may be understood as a device that controls the delay device 11 to delay and output the input signal. The control means 12 comprises a first control input for receiving the first voltage signal of the signal detection terminal of the delay means 11 and a second control input for receiving the input signal, the control means 12 being capable of adjusting the control signal output to the signal control terminal in dependence on the input signal and the first voltage signal. Specifically, when the first voltage signal detected by the first control input terminal of the control device 12 reaches the first inversion voltage, the control signal output to the signal control terminal is adjusted according to the input signal.
The first switching voltage can be understood as a threshold value for determining whether the control device 12 switches the voltage signal. The inverted voltage signal is combined with the value of the input signal to determine whether to invert the control signal. The second switching voltage can be understood as a threshold value for determining whether the delay means 11 is switching the voltage signal.
The input signal in this embodiment is a pulse signal, and the pulse signal can be delayed and output by the delay device 11 in this embodiment. The first control input end of the control device 12 detects the value of the first voltage signal in real time, when the value of the first voltage signal reaches the first inversion voltage of the control device 12, the control signal output by the signal control end is adjusted according to the input signal, if the control signal can reach the first inversion voltage, a high-voltage signal is output to the signal control end, the value of the high-voltage signal is not limited, and a person skilled in the art can determine the value of the high-voltage signal according to the required delay time.
The delay device 11 adjusts the value of the first voltage signal based on the control signal and the input signal, so as to control the output end to output the input signal based on the adjusted first voltage signal. For example, the delay device 11, when receiving the high-level signal, increases the value of the first voltage signal in combination with the input signal to control the time when the output terminal outputs the input signal based on the adjusted first voltage signal. Since the first voltage signal is raised, the arrival time of the inverted voltage of the delay means 11 is delayed, thereby realizing the delayed output of the input signal.
In addition, when the input signal is a falling edge, the control device may adjust the control signal according to the input signal, so that the delay device delays and outputs the falling edge of the input signal based on the adjusted control signal.
The embodiment of the invention provides a delay circuit which comprises a delay device and a control device, wherein a first control input end of the control device is connected with a signal detection end of the delay device so as to monitor a first voltage signal of the signal detection end of the delay device. And when the first voltage signal reaches the first turnover voltage of the control device, adjusting the control signal output to the signal control end according to the input signal. The voltage value of the first voltage signal at the signal detection end of the delay device can be adjusted by the input signal and the control signal. The delay means is capable of delaying the output input signal based on the adjusted first voltage signal and the second switching voltage. According to the technical scheme, when the first turnover voltage of the control device reaches, the control device adjusts the control signal output to the signal control end according to the input signal so as to adjust the voltage value of the first voltage signal used for controlling the output signal in the delay device, wherein the output signal can be regarded as the input signal of delay output, so that the time of the first voltage signal reaching the second turnover voltage is delayed, the output time of the input signal is further delayed, and the problem that the chip layout area is large due to the fact that the resistance value of a resistor and/or the capacitance value of a capacitor are/is increased is avoided. The first switching voltage is greater than the second switching voltage, so that the first voltage signal of the delay device is adjusted by the control device, and then the output of the input signal is controlled based on the first voltage signal.
Optionally, in this embodiment, the optimization of the control device 12 includes:
the first RS trigger is composed of a NAND gate;
the reset input end of the first RS trigger is connected with the signal detection end, the set input end receives the input signal, the Q non-output end is connected with the signal control end or the Q output end is connected with the signal control end through a first phase inverter.
Specifically, fig. 2 is a schematic connection diagram of a delay circuit according to an embodiment of the present invention, and as shown in fig. 2, the control device 12 includes: a first RS flip-flop I1 formed by a nand gate;
reset input terminal of first RS flip-flop I1
Connected with the signal detection terminal, and set the input terminal
Receiving input signal IN, Q non-output end
And is connected with the signal control end. The control device 12 is connected via a reset input
Receiving a first voltage signal VM via a set input terminal
Receiving an input signal IN and then resetting the input terminal
When the first voltage signal VM reaches the first turnover voltage of the first RS flip-flop I1 formed by the NAND gate, the control signal VC output to the signal control end is adjusted according to the input signal IN, so that the signal control end adjusts the voltage value of the first voltage signal VM based on the control signal VC.
Fig. 3 is a schematic connection diagram of another delay circuit according to an embodiment of the present invention, and the connection relationship shown in fig. 3 is different from the connection relationship shown in fig. 2 in that the control device 12 is connected to the signal control terminal through the Q output terminal Q via the first inverter I2.
Optionally, the control device 12 further includes:
a second inverter and a third inverter;
the input end of the second phase inverter is connected with the signal detection end, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is connected with the reset input end.
The present embodiment can more conveniently adjust the switching voltage of the control device 12 by adding the second inverter and the third inverter to the control device 12. When the second inverter and the third inverter are not included in the control device 12, the first flip-flop voltage of the control device 12 is determined by the first RS flip-flop I1. When the second inverter and the third inverter are added to the control device 12, the first inversion voltage of the control device 12 is determined by the second inverter. In this embodiment, it is only necessary to ensure that the first inversion voltage of the second inverter is greater than the second inversion voltage at the output terminal of the delay device 11.
Fig. 4 is a schematic connection diagram of another delay circuit according to an embodiment of the present invention. In fig. 4, a second inverter I3 and a third inverter I4 are added to fig. 3. The input end of the second inverter I3 is connected with the signal detection end, the output end of the second inverter I3 is connected with the input end of the third inverter I4, and the output end of the third inverter I4 is connected with the reset input end
Are connected. The input end of the second inverter I3 is used for receiving the first voltage signal VM and outputting the control signal VC to the signal control end according to the input signal IN when the first voltage signal reaches the first inversion voltage of the second inverter I3.
For ease of understanding, the operating principle of the connection schematic of the delay circuit shown in fig. 4 is explained below:
fig. 5 shows an operation timing diagram corresponding to the connection diagram of the delay circuit in fig. 4. See fig. 4 and 5. The control device 12 includes a first RS flip-flop I1, a first inverter I2, a second inverter I3, and a third inverter I4. The switching voltage of the second inverter I3 is a first switching voltage that is higher than the second switching voltage of the delay device.
When the input signal IN is at a low level, the first fet P0 is turned on, VM is at a high level, and the control signal VC is at a low level because the reset input terminal of the first RS flip-flop I1 is at a high level and the set input terminal is at a low level.
When the input signal IN transits from low level to high level, since the inputs of the first RS flip-flop I1 are all 1, the control signal VC remains low level, and the first voltage signal VM on the upper plate of the capacitor C is discharged by the resistor R1 and the second fet N0. When the first voltage signal VM reaches the flip point of the second inverter I3, the second inverter I3 is flipped, the voltage of the control signal VC is changed from low to high, so that the first voltage signal VM is pushed up to the voltage of Vcp1 by couple, the first voltage signal VM starts to fall again from Vcp1, and when the first voltage signal VM reaches the flip point (second flip voltage) Vtg2 of the output stage inverter, the output OUT becomes high. From this process, it is known that the detection of the double-trip point is utilized, i.e., the detection of whether the first voltage signal VM reaches the first trip voltage of the second inverter I3 and the detection of whether the first voltage signal VM reaches the second trip voltage of the output stage inverter. The delay time Tdr of the rising edge of the input signal IN to the rising edge of the output OUT is increased compared to the adjustment of the first voltage signal VM without the control means 12 outputting the control signal VC, the increased time being adjustable by varying the first flipping voltage Vtg1 and the voltage Vcp1 to which the first voltage signal VM is pushed up, i.e. the delay time of the rising edge of the delay circuit is adjusted by varying the first flipping voltage and the voltage to which the first voltage signal is pushed up.
The delay for the falling edge of the input signal IN is as follows: when the input signal IN changes from high to low, the control signal VC will follow the input signal IN to low, and at the same time the couple pulls down the first voltage signal VM from VSS to a negative voltage-Vcp 2, and the power source charges the capacitor C through the first fet P0 and the resistor R1. When the voltage value of the first voltage signal VM reaches Vtg2, the output stage inverter flips and the output OUT is low. It can be seen that since the initial value of VM becomes-Vcp 2, the charging time is also increased to increase the delay of the falling edge compared to the case where the first voltage signal VM is raised from 0V to Vtg2 without the control device 12, since the first voltage signal VM is raised from-Vcp 2 to Vtg2 in this embodiment. Namely, the delay time of the falling edge of the delay circuit is the time when the first voltage signal rises from the negative voltage (-Vcp2) to the second flip-flop voltage.
It can be seen that the delay circuit is delayed on both rising and falling edges of the input signal by the inverter and the first RS flip-flop I1 in this embodiment. When the falling edge of the input signal arrives, the control means 12 adjusts the control signal VC based on the input signal, thereby pulling down the first voltage signal VM, delaying the time for the delay means 11 to flip. In this embodiment, when the input signal is delayed and outputted, the resistance of the resistor R1 and/or the capacitance of the capacitor C in the delay device 11 do not need to be increased. It should be noted that, compared with increasing the resistance of the resistor R1 and the capacitance of the capacitor C, the gate logic, such as the inverter and the first RS flip-flop I1, occupies a much smaller area on the chip layout, so the present invention can save the chip layout area and reduce the circuit cost.
The delay circuit in this embodiment utilizes the detection of the two-shift threshold voltage, that is, the detection of the first flipping voltage of the control device and the detection of the second flipping voltage of the delay device, to increase the equivalent capacitance, improve the utilization rate of the capacitance, and can realize the same delay time with a smaller layout area. That is, the equivalent capacitance of the delay circuit is determined according to the first and second flip voltages.
The voltage of the C plate of the capacitor is controlled by the first RS trigger I1, and sudden change is carried out on the voltage of the lower plate so as to adjust the first voltage signal.
It should be noted that the connection in fig. 2 may not consider the delay of the falling edge of the input signal, but only consider the delay of the rising edge of the input signal.
Fig. 6 is a connection diagram of a prior art delay circuit. Fig. 7 is a timing diagram corresponding to the delay circuit shown in fig. 6. Referring to fig. 6 and 7, the first fet P00 and the second fet N00 constitute an inverter of the input stage. The third fet P11 and the fourth fet N11 form an inverter of the output stage.
When the input signal IN changes from low level to high level, the voltage of the capacitor C is discharged from VDD via the resistor R1 and the second field effect transistor (NMOS transistor) N00. When the flip point (flip voltage) Vtg of the output stage inverter is reached, the output OUT goes high, the delay time of which is determined by the values of the resistor and capacitor and the flip point of the output stage inverter. If a large delay is to be realized, the resistance value of the resistor needs to be increased and/or the capacitance value of the capacitor needs to be increased, which means that the chip layout area needs to be increased.
From the above analysis, it can be seen that the delay time of the present invention is longer than that of the delay circuit shown in fig. 6 regardless of the rising edge and the falling edge.
IN the embodiment, when the falling edge of the input signal IN arrives, the substrate may charge the first voltage signal VM through the forward PN junction due to the fact that the voltage of the capacitor C IN the delay device 11 is coupled to a negative voltage, and the increased delay time is limited. However, the delay time of the rising edge is precisely controllable, so in order to improve the controllability of the delay time, the present embodiment may apply the delay circuit to a single-edge delay.
Optionally, the control device 12 includes:
a second RS trigger, a fourth inverter and a fifth inverter which are composed of NOR gates;
the input end of the fourth phase inverter is connected with the signal detection end, the output end of the fourth phase inverter is connected with the reset input end of the second RS trigger, the input end of the fifth phase inverter receives an input signal, the output end of the fifth phase inverter is connected with the set input end of the second RS trigger, and the output end of the second RS trigger is connected with the signal control end.
It is understood that, in the present embodiment, the specific connection mode of the control device 12 may be adjusted based on the configuration of the RS flip-flop included in the control device 12.
The RS flip-flop can be formed by cross-connecting the input and output of two nand gates or two nor gates.
Fig. 8 is a schematic connection diagram of another delay circuit according to an embodiment of the present invention. As shown in fig. 8, when the control means 12 includes the second RS flip-flop I5 formed of a nor gate, the present embodiment may set the first flip-flop voltage of the fourth inverter I6 to be greater than the second flip-flop voltage of the delay means 11. Thus, when the first voltage signal reaches the first inversion voltage, the control signal VC output to the signal control terminal is adjusted according to the input signal IN, so that the delay device 11 delays outputting the input signal IN according to the adjusted first voltage signal VM and the second inversion voltage.
The first RS flip-flop I1 and the second RS flip-flop I5 differ in that the trigger levels of the respective reset input and set input are opposite, and the Q output and the set input are opposite
The position of the output end is opposite. Based on the technical effect that the technical personnel in the field can modify the existing connection mode to obtain the corresponding technical effect.
The embodiment is not limited to the specific type of RS flip-flop (which may be implemented by NOR gate or NAND gate or other forms), NOR the type of detection unit (unit that detects the first threshold voltage, e.g., the second inverter I3), and the magnitudes of the first and second flip-flops.
Optionally, the delay device 11 is an RC delay device.
In this embodiment, the delay device 11 may be optimized as an RC delay device, and correspondingly, the control device 12 may further adjust the first voltage signal by outputting a control signal to a capacitor in the RC delay device by using a principle that the capacitor cannot change abruptly, so as to ensure that the delay circuit delays the output input signal.
Optionally, the RC delay device includes: the input inverter, the output inverter, the resistor and the capacitor;
the input end of the input inverter is connected with the second control input end, the output end of the input inverter is connected with one end of a resistor, the other end of the resistor is respectively connected with one end of a capacitor, the first control input end and the input end of the output inverter, and the other end of the capacitor is connected with the control output end;
the input inverter is used for adjusting a second voltage signal at one end of the resistor according to the input signal;
the resistor and the capacitor adjust the first voltage signal based on the second voltage signal and the control signal, so that the output inverter delays outputting the input signal based on the first voltage signal and the second inversion voltage.
Referring to fig. 8, the input inverter includes a first fet P0 and a second fet N0, and the output inverter includes a third fet P1 and a fourth fet N1.
The first fet P0 is turned on when the input signal IN is low, charging the capacitor C. The second fet N0 is turned on when the input signal IN is high, discharging the capacitor C. The third fet P1 is turned on at a low level to output a high level VDD. The fourth fet N1 is turned on at high capacitance to output a low level VSS. The delay device 11 adjusts the voltage value of the first voltage signal according to the principle that the capacitor voltage cannot change suddenly, so that the inversion time of the output inverter is delayed, and the input signal is delayed and output.
In addition, an embodiment of the present invention further provides a chip, including: such as the delay circuit provided by the embodiments of the present invention.
The chip in the embodiment has the same technical effect as the delay circuit by integrating the delay circuit provided by the embodiment of the invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. A delay circuit, comprising: delay means and control means;
the first control input end of the control device is connected with the signal detection end of the delay device, the second control input end of the control device is connected with the input end of the delay device and then receives an input signal, and the control output end of the control device is connected with the signal control end of the delay device;
the control device is configured to adjust a control signal output to the signal control terminal according to the input signal when a first voltage signal detected by the first control input terminal reaches a first inversion voltage of the control device, where the first inversion voltage is greater than a second inversion voltage of the output terminal of the delay device;
the delay device is used for adjusting the first voltage signal based on the control signal and the input signal and delaying and outputting the input signal based on the adjusted first voltage signal and the second turnover voltage.
2. The delay circuit of claim 1, wherein the control means comprises:
the first RS trigger is composed of a NAND gate;
the reset input end of the first RS trigger is connected with the signal detection end, the set input end receives the input signal, the Q non-output end is connected with the signal control end or the Q output end is connected with the signal control end through a first phase inverter.
3. The delay circuit of claim 2, wherein the control means further comprises:
a second inverter and a third inverter;
the input end of the second phase inverter is connected with the signal detection end, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is connected with the reset input end.
4. The delay circuit of claim 1, wherein the control means comprises:
a second RS trigger, a fourth inverter and a fifth inverter which are composed of NOR gates;
the input end of the fourth phase inverter is connected with the signal detection end, the output end of the fourth phase inverter is connected with the reset input end of the second RS trigger, the input end of the fifth phase inverter receives the input signal, the output end of the fifth phase inverter is connected with the set input end of the second RS trigger, and the output end of the second RS trigger is connected with the signal control end.
5. The delay circuit of any one of claims 1 to 4, wherein the delay means is an RC delay means.
6. The delay circuit of claim 5, wherein the RC delay means comprises: the input inverter, the output inverter, the resistor and the capacitor;
the input end of the input phase inverter is connected with the second control input end, the output end of the input phase inverter is connected with one end of the resistor, the other end of the resistor is respectively connected with one end of the capacitor, the first control input end and the input end of the output phase inverter, and the other end of the capacitor is connected with the control output end.
7. The delay circuit of claim 6, wherein the input inverter is configured to adjust a second voltage signal at one end of the resistor according to the input signal;
the resistor and the capacitor adjust the first voltage signal based on the second voltage signal and the control signal.
8. The delay circuit of claim 1, wherein the delay time of the rising edge of the delay circuit is adjusted by changing the first flipping voltage and the voltage to which the first voltage signal is pushed up.
9. The delay circuit of claim 1, wherein the delay time of the falling edge of the delay circuit is a time when the first voltage signal rises from a negative voltage to the second flipping voltage.
10. The delay circuit of claim 1, wherein an equivalent capacitance of the delay circuit is determined according to the first and second flipping voltages.
11. A chip, comprising: a delay circuit as claimed in any one of claims 1 to 10.
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|---|---|---|---|
| CN201911142942.2A CN112825479A (en) | 2019-11-20 | 2019-11-20 | Delay circuit and chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911142942.2A CN112825479A (en) | 2019-11-20 | 2019-11-20 | Delay circuit and chip |
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| CN112825479A true CN112825479A (en) | 2021-05-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023065583A1 (en) * | 2021-10-19 | 2023-04-27 | 深圳飞骧科技股份有限公司 | Radio frequency switch bias voltage feedback control circuit |
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Address after: 230601 No.368 Qinghua Road, Hefei Economic and Technological Development Zone, Anhui Province Applicant after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Applicant after: Zhaoyi Innovation Technology Group Co.,Ltd. Applicant after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Address before: 230601 No.368 Qinghua Road, Hefei Economic and Technological Development Zone, Anhui Province Applicant before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Applicant before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Applicant before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. |