WO2023065583A1

WO2023065583A1 - Radio frequency switch bias voltage feedback control circuit

Info

Publication number: WO2023065583A1
Application number: PCT/CN2022/078368
Authority: WO
Inventors: 苏俊华; 郭嘉帅
Original assignee: 深圳飞骧科技股份有限公司
Priority date: 2021-10-19
Filing date: 2022-02-28
Publication date: 2023-04-27
Also published as: CN215932482U

Abstract

A radio frequency switch bias voltage feedback control circuit (100), comprising a frequency-adjustable oscillator (1), a charge pump (2), a level detection circuit (3) and a decoding circuit (4) connected in sequence. The decoding circuit (4) is further connected to the frequency-adjustable oscillator (1); the frequency-adjustable oscillator (1) is used to generate, according to a received frequency control signal, a clock signal the frequency of which corresponds to the frequency control signal and to output same; the charge pump (2) is used to generate, according to the clock signal, N multiples of a switch bias level from an externally inputted reference level and to output same, wherein N>1; the level detection circuit (3) is used to compare the received switch bias level with a preset reference level and to generate and output a bias level state indication signal; and the decoding circuit (4) is used to sequentially set a frequency, perform decoding according to the received bias level state indication signal, and generate and output a frequency control signal. The switch bias level outputted by the radio frequency switch bias voltage feedback control circuit (100) has good stability.

Description

RF Switch Bias Voltage Feedback Control Circuit

technical field

The utility model relates to the technical field of radio frequency switches, in particular to a bias voltage feedback control circuit of a radio frequency switch.

Background technique

At present, radio frequency switches are widely used in wireless communication equipment, and are used in occasions where radio frequency signals need to be turned on or off, such as transmitting and receiving switches, channel selection switches, tuning switches, and reversing switches. According to the comprehensive cost and performance considerations of radio frequency switches, silicon substrate-buried oxide layer-outer edge silicon (SOI) technology is usually used in wireless communication equipment, and metal oxide field effect transistor (MOS transistor) devices are grown on outer edge silicon. Make a radio frequency switch circuit. Generally, in order to improve the turn-on and cut-off characteristics of MOS tubes, it is necessary to use a level higher than the power supply voltage or lower than the reference ground as the bias level of the RF switch. In the RF switch circuit, a charge pump is generally used to generate a voltage higher than the power supply voltage or lower than the reference ground. The level of the reference ground, and the load capacity of the charge pump is linearly positively related to the clock frequency.

The RF switch bias voltage circuit of the related art comprises a timer and a logic inversion detection circuit connected in sequence, a frequency adjustable oscillator and a charge pump; the logic inversion detection circuit detects and generates a frequency control signal according to an externally input RF switch control signal, to Flip to adjust the frequency form of the oscillator; the frequency adjustable oscillator outputs the clock signal to the charge pump according to the frequency control signal; the charge pump generates a certain multiple of the input reference level according to the clock signal to generate the bias level required by the RF switch; timing The registers are respectively connected to the output terminal of the frequency adjustable oscillator and the clock input terminal detected by the logic flip detection circuit, and are used to extend the duration of the fast clock signal.

However, when the state of the load connected to the RF switch bias voltage circuit in the related art changes, for example, when the path of the RF switch is switched, that is, the capacitive load of the bias voltage circuit will undergo a large mutation, which is limited by the bias voltage. The response speed and driving capability of the charge pump in the circuit lead to the loss of charge stored in the voltage stabilizing capacitor at the output end of the charge pump, causing the voltage amplitude of the bias level of the bias voltage circuit to drop instantaneously. If the voltage amplitude of the bias level does not return to normal within the specified switching time, it will affect the performance of the RF switch. In this case, the RF switch bias voltage circuit in the related art cannot meet the switching time requirement. The unavoidable nonlinearity of the RF switch determines that the AC-DC conversion (AC-DC) phenomenon will occur when the RF signal passes through the device, so that the load of the charge pump is no longer just a capacitor, but a combination of capacitor and DC current. And, while the DC current will greatly weaken the magnitude of the bias level, at this time the RF switch conduction and cut-off performance will deteriorate sharply, as the RF signal power of the RF switch contacts increases, the AC-DC conversion phenomenon will become more Obviously, the output level of the charge pump cannot maintain the state of the radio frequency switch in the end, resulting in the breakdown and burning of the radio frequency switch.

Therefore, it is necessary to provide a new RF switch bias voltage circuit to solve the above problems.

Utility model content

Aiming at the above deficiencies in the prior art, the utility model proposes a radio frequency switch bias voltage feedback control circuit with good output switch bias level stability.

In order to solve the above technical problems, the embodiment of the utility model provides a radio frequency switch bias voltage feedback control circuit, which includes a frequency adjustable oscillator and a charge pump connected in sequence; the frequency adjustable oscillator is used to generate a clock signal and output; the charge pump is used to generate N times the switch bias level and output the externally input reference level according to the clock signal; wherein, N>1; the radio frequency switch bias voltage feedback control circuit It also includes a level detection circuit and a decoding circuit connected in sequence; the level detection circuit is also connected to the charge pump, and the level detection circuit is used to compare the received switch bias level with the preset The reference level is compared and the bias level status indication signal is generated and output; the decoding circuit is also connected to the frequency adjustable oscillator, and the decoding circuit is used for sequentially setting the frequency and according to the received Decode the bias level state indication signal to generate and output a frequency control signal; the frequency adjustable oscillator is also used to generate the frequency corresponding to the frequency control signal according to the frequency control signal to be received the clock signal.

Preferably, the level detection circuit detects and receives the switch bias level output by the charge pump in real time; the level detection circuit includes a comparator, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS, and a voltage-dividing impedance Z2, wherein, the voltage dividing impedance ZS is a variable impedance; the first end of the voltage dividing impedance Z1 is connected to the power supply voltage; the second end of the voltage dividing impedance Z1 is respectively connected to the negative input of the comparator terminal, the first end of the voltage dividing impedance ZS; the positive input terminal of the comparator is used as the reference level input terminal of the level detection circuit; the output terminal of the comparator is used as the reference level input terminal of the level detection circuit The bias level state indicates the signal output terminal, and the output terminal of the comparator is connected to the adjustment terminal of the voltage dividing impedance ZS; the second end of the voltage dividing impedance ZS is connected to the first terminal of the voltage dividing impedance Z2 Two terminals; the first terminal of the voltage dividing impedance Z2 is used as the input terminal of the level detection circuit.

Preferably, the bias level state indication signal is a set of digital signals or analog signals.

Preferably, the reference level is a fixed voltage input by an external circuit or a preset threshold voltage internally generated by the level detection circuit.

Preferably, the decoding circuit performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.

Preferably, the decoding circuit is configured to perform the frequency setting according to the received bias level state indication signal;

The decoding circuit includes an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, three input AND gate ANDB and 8421 decoder; the positive end of the inverter INV1 is used as the input end of the decoding circuit, and the positive end of the inverter INV1 is respectively connected to the gate of the transistor PM1, the The first input end of the three-input AND gate ANDB and the first input end of the 8421 decoder; the negative end of the inverter INV1 is connected to the first end of the resistor R1; the first end of the resistor R2 The two terminals are respectively connected to the positive terminal of the capacitor C1, the input terminal of the Schmitt trigger ST1 and the drain of the transistor PM1; the negative terminal of the capacitor C1 is connected to ground; the source of the transistor PM1 The pole is connected to the power supply voltage; the output terminal of the Schmitt trigger ST1 is respectively connected to the positive terminal of the inverter INV2, the gate of the transistor NM1 and the third input terminal of the three-input AND gate ANDB ; The negative terminal of the inverter INV2 is connected to the first terminal of the resistor R2; the second terminal of the resistor R2 is respectively connected to the negative terminal of the capacitor C2 and the input of the Schmitt trigger ST2 terminal and the drain of the transistor NM1; the positive terminal of the capacitor C2 is connected to the power supply voltage; the source of the transistor NM1 is connected to ground; the output terminal of the Schmitt trigger ST2 is connected to the three inputs The second input end of the AND gate ANDB; the output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder; the third input end of the 8421 decoder is used as the decoding circuit The frequency setting input terminal; the output terminal of the 8421 decoder is used as the output terminal of the decoding circuit.

Preferably, the frequency control signal is a set of digital signals or analog signals.

Preferably, the decoding circuit includes a delay processing module, and the delay processing module is used for delay processing the external input signal of the decoding circuit or the intermediate signal inside the decoding circuit.

Preferably, the frequency control signal can control the frequency of the clock signal in real time.

Preferably, the charge pump includes a voltage stabilizing capacitor, the positive end of the voltage stabilizing capacitor is connected to the output end of the charge pump that outputs the switch bias level, and the negative end of the voltage stabilizing capacitor is connected to ground .

Compared with related technologies, the radio frequency switch bias voltage feedback control circuit of the utility model is provided with a level detection circuit, a decoding circuit and the frequency adjustable oscillator, and the level detection circuit outputs the output voltage of the charge pump. The switch bias level is compared with a preset reference level to generate and output a bias level state indication signal; the bias level state indication signal is decoded by a decoding circuit to generate and output a frequency control signal, and then generate the clock signal corresponding to the frequency of the frequency control signal from the frequency control signal through the frequency adjustable oscillator, so that the charge pump generates and inputs the corresponding clock signal according to the clock signal Switching bias levels, the charge pump periodically transfers positive charges to accumulate above the reference level to generate a level higher than the reference level, and if negative charges are transferred, it generates a level higher than the reference level The level is lower, so the switch bias level generated by the charge pump is the bias level required by the radio frequency switch. The circuit simultaneously makes the frequency adjustable oscillator, the charge pump, the level detection circuit and the decoding circuit jointly form a feedback system, thereby making the output switch bias level of the radio frequency switch bias voltage feedback control circuit of the utility model stable Good sex.

Description of drawings

Below in conjunction with accompanying drawing, describe the utility model in detail. Through the detailed description in conjunction with the following drawings, the content of the above or other aspects of the present invention will become clearer and easier to understand. In the attached picture,

Fig. 1 is the circuit structural diagram of the RF switch bias voltage feedback control circuit of related art;

2 is a circuit structure diagram of a radio frequency switch bias voltage feedback control circuit in Embodiment 1 of the present invention;

FIG. 3 is a schematic circuit diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 2 of the present invention.

Detailed ways

The specific embodiment of the utility model will be described in detail below in conjunction with the accompanying drawings.

The specific implementations/embodiments described here are specific specific implementations of the present utility model, and are used to illustrate the concept of the present utility model. Limitations on the scope of utility models. In addition to the embodiments described here, those skilled in the art can also adopt other obvious technical solutions based on the claims of the application and the contents disclosed in the description, and these technical solutions include adopting any obvious changes made to the embodiments described here. The replacement and modified technical solutions are all within the protection scope of the present utility model.

(Embodiment 1)

The utility model provides a radio frequency switch bias voltage feedback control circuit 100 . Please refer to FIG. 2 , which is a circuit structure diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 1 of the present invention.

The RF switch bias voltage feedback control circuit 100 includes a frequency adjustable oscillator 1 , a charge pump 2 , a level detection circuit 3 and a decoding circuit 4 connected in sequence. Wherein, the decoding circuit 1 is also connected to the frequency adjustable oscillator 4 . The frequency adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 together form a circuit closed loop.

The frequency adjustable oscillator 1 is used to generate and output a clock signal.

The charge pump 2 is used for generating and outputting a switch bias level of N multiples from an externally input reference level according to the clock signal. Among them, N>1. The voltage value of the switch bias level is positively related to the frequency of the clock signal generated by the adjustable frequency oscillator 1 .

In the first embodiment, the charge pump 2 includes a voltage stabilizing capacitor. The positive end of the voltage stabilizing capacitor is connected to the output end of the charge pump 2 for outputting the switch bias level. The negative end of the voltage stabilizing capacitor is connected to ground. The charge pump 2 transfers charges from the external input reference level to the output voltage stabilizing capacitor at the frequency of the current clock signal, so as to provide the switch bias level required by the radio frequency switch.

The level detection circuit 3 is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indication signal.

In the first embodiment, the reference level is a fixed voltage input by an external circuit. Of course, it is not limited thereto, the preset threshold voltage generated inside the level detection circuit 3 . For example, a fixed threshold voltage can be generated by resistive voltage division, and the level detection circuit 3 can generate the Bias level status indication signal.

In the first embodiment, the bias level state indication signal is a set of digital signals. Of course, in another embodiment, the bias level state indicating signal may also be an analog signal.

More preferably, the level detection circuit 3 detects and receives the switch bias level output by the charge pump 2 in real time, and this setting can make the switch bias level output by the charge pump 2 last Adjust and keep the voltage value stable.

The decoding circuit 4 is used to sequentially perform frequency setting and decode according to the received bias level status indication signal to generate and output a frequency control signal. The frequency adjustable oscillator 1 is also used for generating the clock signal with a frequency corresponding to the frequency control signal according to the frequency control signal to be received.

In the first embodiment, the decoding circuit 4 is configured to perform the frequency setting according to the received bias level state indication signal. Of course, it is not limited thereto, and the decoding circuit 4 also performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.

In the first embodiment, the frequency control signal is a set of digital signals. Of course, it is also possible that the frequency control signal is an analog signal in another embodiment.

In the first embodiment, the decoding circuit 4 includes a delay processing module (not shown in the figure), and the delay processing module is used to convert the external input signal of the decoding circuit 4 or the intermediate signal inside the decoding circuit 4 The signal is delayed. In this way, the delay processing module can reduce the output glitch of the charge pump 2 caused by the excessive frequency change of the clock signal of the charge pump 2, and at the same time, it will not make an error when the level detection circuit 3 misjudges The frequency tunable oscillator 1 is used to generate the frequency of the clock signal.

In the first embodiment, the frequency control signal can control the frequency of the clock signal in real time. This setting can make the switch bias level output by the charge pump 2 continuously adjustable and keep the voltage value stable.

The RF switch bias voltage feedback control circuit 100 periodically transports positive charges above the reference level through the charge pump 2 to generate a level higher than the reference level, such as transporting negative charges , then a level lower than the reference level is generated, so that the switch bias level generated by the charge pump 2 is the bias level required by the radio frequency switch. At the same time, the level detection circuit 3 continuously detects the switch bias level output by the charge pump 2, and the level detection circuit 3 compares the switch bias level with the reference level Comparing and generating the bias level state indication signal for continuously adjusting the decoding circuit 4 . Therefore, the frequency adjustable oscillator 1 , the charge pump 2 , the level detection circuit 3 and the decoding circuit 4 together form a feedback system.

In this feedback system, when the on/off state of the radio frequency switch changes, the magnitude of the bias level of the switch will decrease instantaneously. At this time, the level detection circuit 3 detects the state change, and outputs the bias level The status indication signal indicates that the frequency of the clock signal of the adjustable frequency oscillator 1 needs to be adjusted at this time to improve the driving capability of the charge pump 2, so as to quickly return to the normal RF switch working state.

When the RF power input by the RF switch becomes larger, due to non-linear reasons, the load of the charge pump 2 changes from a capacitive load to a capacitive superimposed DC current load, and the switch bias level amplitude at this time will be reduced and maintained, so The level detection circuit 3 detects a state change, and indicates that the frequency of the clock signal of the frequency adjustable oscillator 1 needs to be adjusted at this time by outputting the bias level state indication signal to enable the charge pump 2 to drive Increased ability to maintain adequate switch bias levels until RF power is reduced. Therefore, the stability of the switch bias level of the output of the RF switch bias voltage feedback control circuit 100 is good.

It should be pointed out that the frequency adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 used in the present invention are all commonly used circuits in the field, and the specific circuit results and performance indicators are determined according to actual applications. The adjustment is not described in detail here.

(Example 2)

Embodiment 2 of the utility model provides a radio frequency switch bias voltage feedback control circuit with a specific circuit structure. Please refer to FIG. 3 , which is a schematic circuit diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 2 of the present invention.

In the second embodiment, the level detection circuit 3 includes a comparator COMP, a voltage dividing impedance Z1, a voltage dividing impedance ZS, and a voltage dividing impedance Z2, wherein the voltage dividing impedance ZS is a variable impedance.

The concrete circuit structure of described level detection circuit 3 is:

A first end of the voltage dividing impedance Z1 is connected to a power supply voltage.

The second terminal of the voltage dividing impedance Z1 is respectively connected to the negative input terminal of the comparator COMP and the first terminal of the voltage dividing impedance ZS.

The positive input terminal of the comparator COMP is used as the reference level input terminal of the level detection circuit 3 .

The output terminal of the comparator COMP is used as the output terminal of the bias level state indication signal of the level detection circuit 3 , and the output terminal of the comparator COMP is connected to the adjusting terminal of the voltage dividing impedance ZS.

The second end of the voltage dividing impedance ZS is connected to the second end of the voltage dividing impedance Z2.

The first end of the voltage dividing impedance Z2 is used as the input end of the level detection circuit 3 .

Wherein, the connection point between the negative input terminal of the comparator COMP and the voltage dividing impedance Z1 and the voltage dividing impedance ZS is VS.

When the bias level state indicating signal is high, the voltage dividing impedance ZS is close to 0 ohm, and when the bias level state indicating signal is low, the voltage dividing impedance ZS is much larger than 0 ohm. The potential of VS at any moment is:

When the reference level VREF does not reach the required level, the bias level state indication signal is low, the voltage division impedance ZS is much greater than 0 ohms, and the VS voltage value is greater than the reference level VREF. As the voltage amplitude of the reference level VNEG increases, the VS voltage value approaches the reference level VREF, until the VS voltage value is slightly greater than the reference level VREF, at this time the bias level status indication signal is turned high, and at this time:

When the bias level state indication signal is high, the voltage divider impedance ZS is close to 0 ohms, so the level of VS changes suddenly as follows:

The above process can complete the hysteresis process, so as to avoid output oscillation caused by noise and interference, and at the same time, the output of the level detection circuit 3 will not be completely locked, so that it maintains the detection function.

The decoding circuit 4 includes an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, three Input AND gate ANDB and 8421 decoder.

The circuit structure of described decoding circuit 4 is:

The positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is connected to the gate of the transistor PM1 and the first gate of the three-input AND gate ANDB respectively. input and the first input of the 8421 decoder.

The negative end of the inverter INV1 is connected to the first end of the resistor R1.

The second terminal of the resistor R2 is respectively connected to the positive terminal of the capacitor C1 , the input terminal of the Schmitt trigger ST1 and the drain of the transistor PM1 . The negative terminal of the capacitor C1 is connected to ground. The source of the transistor PM1 is connected to a power supply voltage.

The output terminal of the Schmitt trigger ST1 is respectively connected to the positive terminal of the inverter INV2 , the gate of the transistor NM1 and the third input terminal of the three-input AND gate ANDB.

The negative end of the inverter INV2 is connected to the first end of the resistor R2.

The second terminal of the resistor R2 is respectively connected to the negative terminal of the capacitor C2, the input terminal of the Schmitt trigger ST2 and the drain of the transistor NM1. The positive end of the capacitor C2 is connected to the power supply voltage; the source of the transistor NM1 is connected to the ground.

The output end of the Schmitt trigger ST2 is connected to the second input end of the three-input AND gate ANDB.

The output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder.

The third input terminal of the 8421 decoder is used as the frequency setting input terminal of the decoding circuit 4;

The output terminal of the 8421 decoder is used as the output terminal of the decoding circuit 4 .

In the second embodiment, the inverter INV1, the resistor R1, the capacitor C1, the transistor PM1 and the Schmitt trigger ST1 in the decoding circuit 4 form a first-stage single-edge delayer, and the decoding circuit 4 Inverter INV2, resistor R2, capacitor C2, transistor NM1 and Schmitt trigger ST2 form the second-stage single-edge delayer. The three-input AND gate ANDB and 8421 decoder realize the decoding function. Among them, the frequency setting input terminal VCH is used to control the frequency setting of the 8421 decoder.

The function of the first-stage single-edge delayer is to output a high level immediately when the input signal is turned from a high level to a low level, and to delay the generation of a low level when the input signal is turned from a low level to a high level, and the delay time is Determined by the product of resistor R1 and capacitor C1. The function of the second-stage single-edge delayer is to output low level immediately when the input signal is turned from low level to high level, and to delay the generation of high level when the input signal is turned from high level to low level. The delay time is Determined by the product of resistor R2 and capacitor C2.

In the second embodiment, the frequency adjustable oscillator 1 is a ring oscillator, which is composed of the inverter INV3 of the frequency adjustable oscillator 1 and an even-order inverter chain, and the frequency is determined by the frequency adjustable The controlled current source CS of oscillator 1 and the load capacitance C3 determine that when the controlled current source CS is set to a small current, the clock signal period is very long; when the controlled current source CS is set to a medium current, the clock signal period Short; when the controlled current source CS is set to a large current, the clock signal period is extremely short.

In the second embodiment, the charge pump 2 is composed of a non-overlapping clock generator and a mutually biased symmetric charge pump, and the two phases of the clock can be fully used to charge the voltage stabilizing capacitor C4 of the charge pump 2, and the switch The bias level VNEG is the output terminal of the charge pump 2 .

The decoding circuit 4 and the frequency adjustable oscillator 1 jointly form a variable frequency oscillator with a delay function. specific,

When the bias level state indication signal is high, the frequency adjustable oscillator 1 outputs a clock signal with a very low frequency, so as to reduce the power consumption of the whole system.

When the bias level state indication signal changes from high to low, the frequency adjustable oscillator 1 immediately outputs a clock signal with a high frequency to strengthen the driving of the charge pump 2 .

When the bias level state indication signal changes from low to high, the frequency adjustable oscillator 1 will first output a medium frequency clock signal for a period of time, so that the drive of the charge pump 2 is reduced, and then the frequency is adjustable The oscillator 1 outputs a clock signal with a very low frequency, and the charge pump 2 returns to normal operation.

If the switch bias level amplitude will decrease due to the increase of the RF power input by the RF switch, the level detection circuit 3 will continuously output a low level so that the frequency adjustable oscillator 1 always maintains The high-frequency clock signal maintains the level of the switch bias level VNEG by consuming more power, thereby ensuring the working state of the radio frequency switch.

It should be pointed out that the relevant circuits, modules and components used in this utility model are all circuits, modules and components commonly used in the field, and the corresponding specific indicators and parameters are adjusted according to actual applications, and will not be described in detail here.

It should be noted that the various embodiments described above with reference to the accompanying drawings are only used to illustrate the utility model rather than limit the scope of the utility model, those of ordinary skill in the art should understand that without departing from the spirit and scope of the utility model Any modifications or equivalent replacements made to the present utility model under the premise of the present utility model shall be covered within the scope of the present utility model. Further, words appearing in the singular include the plural and vice versa unless the context otherwise requires. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.

Claims

A radio frequency switch bias voltage feedback control circuit, which includes an adjustable frequency oscillator and a charge pump connected in sequence; the adjustable frequency oscillator is used to generate and output a clock signal; the charge pump is used to generate and output a clock signal according to the clock The signal generates a switch bias level of N multiples from the externally input reference level and outputs it; wherein, N>1; it is characterized in that the RF switch bias voltage feedback control circuit also includes a sequentially connected level detection circuit and decoding circuit;

The level detection circuit is also connected to the charge pump, and the level detection circuit is used to compare the received switch bias level with a preset reference level and generate and output a bias level state indication signal;

The decoding circuit is also connected to the frequency adjustable oscillator, and the decoding circuit is used to sequentially set the frequency and decode according to the received bias level state indication signal to generate and output the frequency control Signal;

The frequency adjustable oscillator is also used to generate the clock signal with a frequency corresponding to the frequency control signal according to the frequency control signal to be received.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the level detection circuit detects and receives the switch bias level output by the charge pump in real time;

The level detection circuit includes a comparator, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS, and a voltage-dividing impedance Z2, wherein the voltage-dividing impedance ZS is a variable impedance;

The first end of the voltage dividing impedance Z1 is connected to the power supply voltage;

The second end of the voltage dividing impedance Z1 is respectively connected to the negative input end of the comparator and the first end of the voltage dividing impedance ZS;

The positive input terminal of the comparator is used as the reference level input terminal of the level detection circuit;

The output terminal of the comparator is used as the output terminal of the bias level state indication signal of the level detection circuit, and the output terminal of the comparator is connected to the adjustment terminal of the voltage dividing impedance ZS;

The second end of the voltage dividing impedance ZS is connected to the second end of the voltage dividing impedance Z2;

The first end of the voltage dividing impedance Z2 is used as the input end of the level detection circuit.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the bias level state indication signal is a set of digital signals or analog signals.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the reference level is a fixed voltage input from an external circuit or a preset threshold voltage generated inside the level detection circuit.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the decoding circuit performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the decoding circuit is used to perform the frequency setting according to the received bias level state indication signal;

The decoding circuit includes an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, three input AND gate ANDB and 8421 decoder;

The positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is connected to the gate of the transistor PM1 and the first gate of the three-input AND gate ANDB respectively. input terminal and the first input terminal of the 8421 decoder;

The negative end of the inverter INV1 is connected to the first end of the resistor R1;

The second terminal of the resistor R2 is respectively connected to the positive terminal of the capacitor C1, the input terminal of the Schmitt trigger ST1 and the drain of the transistor PM1; the negative terminal of the capacitor C1 is connected to ground; The source of the transistor PM1 is connected to a power supply voltage;

The output terminal of the Schmitt trigger ST1 is respectively connected to the positive terminal of the inverter INV2, the gate of the transistor NM1 and the third input terminal of the three-input AND gate ANDB;

The negative end of the inverter INV2 is connected to the first end of the resistor R2;

The second terminal of the resistor R2 is respectively connected to the negative terminal of the capacitor C2, the input terminal of the Schmitt trigger ST2 and the drain of the transistor NM1; the positive terminal of the capacitor C2 is connected to the power supply voltage ; The source of the transistor NM1 is connected to ground;

The output terminal of the Schmitt trigger ST2 is connected to the second input terminal of the three-input AND gate ANDB;

The output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder;

The third input terminal of the 8421 decoder is used as the frequency setting input terminal of the decoding circuit;

The output terminal of the 8421 decoder is used as the output terminal of the decoding circuit.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the frequency control signal is a set of digital signals or analog signals.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the decoding circuit includes a delay processing module, and the delay processing module is used to convert the external input signal of the decoding circuit or the The intermediate signal inside the decoding circuit is delayed.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the frequency control signal can control the frequency of the clock signal in real time.
The RF switch bias voltage feedback control circuit according to claim 1, wherein the charge pump includes a voltage stabilizing capacitor, and the positive end of the voltage stabilizing capacitor is connected to the charge pump to connect the switch bias voltage The output terminal of the flat output, and the negative terminal of the voltage stabilizing capacitor is connected to the ground.