CN215932482U - Bias voltage feedback control circuit of radio frequency switch - Google Patents
Bias voltage feedback control circuit of radio frequency switch Download PDFInfo
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- CN215932482U CN215932482U CN202122519735.3U CN202122519735U CN215932482U CN 215932482 U CN215932482 U CN 215932482U CN 202122519735 U CN202122519735 U CN 202122519735U CN 215932482 U CN215932482 U CN 215932482U
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
Abstract
The utility model provides a radio frequency switch bias voltage feedback control circuit, which comprises a frequency-adjustable oscillator, a charge pump, a level detection circuit and a decoding circuit which are connected in sequence, wherein the decoding circuit is also connected with the frequency-adjustable oscillator; the frequency adjustable oscillator is used for generating and outputting a clock signal with a frequency corresponding to the frequency control signal according to the received frequency control signal; the charge pump is used for generating and outputting N times of switch bias level from an externally input reference level according to a clock signal; wherein N > 1; the level detection circuit is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indicating signal; the decoding circuit is used for sequentially carrying out frequency setting and decoding according to the received bias level state indicating signal and generating and outputting a frequency control signal. The switch bias level output by the radio frequency switch bias voltage feedback control circuit has good stability.
Description
Technical Field
The utility model relates to the technical field of radio frequency switches, in particular to a bias voltage feedback control circuit of a radio frequency switch.
Background
Currently, radio frequency switches are widely used in wireless communication devices, and are used in occasions where radio frequency signals need to be turned on or off, such as transmitting and receiving switches, channel selection switches, tuning switches, reversing switches, and the like. In consideration of the overall cost and performance of the rf switch, the rf switch circuit is usually fabricated in wireless communication devices by using a silicon substrate-buried oxide layer-Silicon On Insulator (SOI) technology, and growing metal oxide field effect transistor (MOS) devices on the silicon on the outer edge. Generally, in order to improve the on and off characteristics of the MOS transistor, a level higher than a supply voltage or lower than a reference ground is required to be used as a bias level of the radio frequency switch, a charge pump is generally adopted in a radio frequency switch circuit to generate a level higher than the supply voltage or lower than the reference ground, and the load capacity of the charge pump is in positive linear correlation with a clock frequency.
The radio frequency switch bias voltage circuit in the related art comprises a timer, and a logic turnover detection circuit, a frequency adjustable oscillator and a charge pump which are connected in sequence; the logic turnover detection circuit detects and generates a frequency control signal according to an externally input radio frequency switch control signal so as to turn over and adjust the frequency form of the oscillator; the frequency adjustable oscillator outputs a clock signal to the charge pump according to the frequency control signal; the charge pump generates a certain multiple of an input reference level according to a clock signal to generate a bias level required by the radio frequency switch; the timer is respectively connected to the output end of the frequency-adjustable oscillator and the clock input end detected by the logic turnover detection circuit and is used for prolonging the duration time of the fast clock signal.
However, when the load state of the rf switch bias voltage circuit is changed, for example, when the path of the rf switch is switched, the capacitive load of the bias voltage circuit may have a large sudden change, which is limited by the response speed and the driving capability of the charge pump in the bias voltage circuit, and the charge stored in the voltage stabilizing capacitor at the output terminal of the charge pump is lost, resulting in a momentary drop of the voltage amplitude of the bias level of the bias voltage circuit. If the voltage amplitude of the bias level does not return to normal within the specified switching time, the performance of the rf switch may be affected. In this case, the related art rf switch bias voltage circuit cannot meet the switching time requirement. The unavoidable nonlinearity of the radio frequency switch determines that an alternating current-direct current (AC-DC) conversion phenomenon can be generated when a radio frequency signal passes through a device, so that the load of the charge pump is not only a capacitor but also the sum of the capacitor and direct current, the direct current can greatly weaken the amplitude of a bias level, the on-off performance of the radio frequency switch is rapidly deteriorated, the alternating current-direct current conversion phenomenon is more obvious along with the increase of the power of the radio frequency signal contacted by the radio frequency switch, and finally the output level of the charge pump cannot keep the state of the radio frequency switch, so that the breakdown and the burning of the radio frequency switch are caused.
Therefore, there is a need to provide a new rf switch bias voltage circuit to solve the above problems.
SUMMERY OF THE UTILITY MODEL
In view of the above deficiencies of the prior art, the present invention provides a feedback control circuit for rf switch bias voltage with good stability of the output switch bias level.
In order to solve the above technical problem, an embodiment of the present invention provides a bias voltage feedback control circuit for a radio frequency switch, which includes a frequency-adjustable oscillator and a charge pump connected in sequence; the frequency adjustable oscillator is used for generating and outputting a clock signal; the charge pump is used for generating and outputting N times of switch bias level of an externally input reference level according to the clock signal; wherein N > 1; the radio frequency switch bias voltage feedback control circuit further comprises a level detection circuit and a decoding circuit which are connected in sequence; the level detection circuit is also connected with the charge pump and is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indication signal; the decoding circuit is also connected with the frequency-adjustable oscillator and is used for sequentially carrying out frequency setting, decoding according to the received bias level state indicating signal and generating and outputting a frequency control signal; the frequency adjustable oscillator is further used for generating the clock signal with the frequency corresponding to the frequency control signal according to the frequency control signal to be received.
Preferably, the level detection circuit detects and receives the switch bias level output by the charge pump in real time; the level detection circuit comprises a comparator, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS and a voltage-dividing impedance Z2, wherein the voltage-dividing impedance ZS is variable impedance; a first end of the voltage-dividing impedance Z1 is connected to a power supply voltage; the second end of the voltage-dividing impedance Z1 is respectively connected to the negative input end of the comparator and the first end of the voltage-dividing impedance ZS; a positive input end of the comparator is used as a reference level input end of the level detection circuit; the output end of the comparator is used as the bias level state indicating signal output end of the level detection circuit, and the output end of the comparator is connected to the adjusting end of the voltage-dividing impedance ZS; the second end of the partial pressure impedance ZS is connected to the second end of the partial pressure impedance Z2; a first terminal of the voltage-dividing impedance Z2 serves as an input terminal of the level detection circuit.
Preferably, the bias level status indicator signal is a set of digital signals or analog signals.
Preferably, the reference level is a fixed voltage input by an external circuit or a preset threshold voltage generated inside the level detection circuit.
Preferably, the decoding circuit performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.
Preferably, the decoding circuit is configured to perform the frequency setting according to the bias level status indication signal to be received;
the decoding circuit comprises an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, a three-input AND gate ANDB and a 8421 decoder; the positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is respectively connected to the gate of the transistor PM1, the first input terminal of the three-input and gate ANDB and the first input terminal of the 8421 decoder; a negative electrode terminal of the inverter INV1 is connected to the first terminal of the resistor R1; a second end of the resistor R2 is connected to a positive terminal of the capacitor C1, an input terminal of the schmitt trigger ST1, and a drain of the transistor PM1, respectively; the negative terminal of the capacitor C1 is connected to the ground; the source of the transistor PM1 is connected to a supply voltage; an output end of the schmitt trigger ST1 is respectively connected to a positive electrode end of the inverter INV2, a gate of the transistor NM1, and a third input end of the three-input and gate ANDB; a negative electrode terminal of the inverter INV2 is connected to the first terminal of the resistor R2; a second end of the resistor R2 is connected to the negative terminal of the capacitor C2, the input terminal of the schmitt trigger ST2, and the drain of the transistor NM1, respectively; the positive end of the capacitor C2 is connected to a power supply voltage; the source of the transistor NM1 is connected to ground; the output end of the Schmitt trigger ST2 is connected to the second input end of the three-input AND gate ANDB; the output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder; a third input end of the 8421 decoder is used as a frequency setting input end of the decoding circuit; the output end of the 8421 decoder serves as the output end of the decoding circuit.
Preferably, the frequency control signal is a set of digital signals or analog signals.
Preferably, the decoding circuit includes a delay processing module, and the delay processing module is configured to delay an external input signal of the decoding circuit or an intermediate signal inside the decoding circuit.
Preferably, the frequency control signal may control the frequency of the clock signal in real time.
Preferably, the charge pump includes a voltage stabilizing capacitor, a positive terminal of the voltage stabilizing capacitor is connected to an output terminal of the charge pump, which outputs the switch bias level, and a negative terminal of the voltage stabilizing capacitor is connected to ground.
Compared with the prior art, the radio frequency switch bias voltage feedback control circuit is provided with the level detection circuit, the decoding circuit and the frequency-adjustable oscillator, wherein the level detection circuit compares the switch bias level output by the charge pump with a preset reference level and generates and outputs a bias level state indication signal; the bias level state indicating signal is decoded by a decoding circuit to generate and output a frequency control signal, and then the frequency control signal is used by the frequency adjustable oscillator to generate the clock signal with the frequency corresponding to the frequency control signal, so that the charge pump generates and inputs a corresponding switch bias level according to the clock signal, the charge pump periodically carries positive charges to be accumulated above the reference level to generate a level higher than the reference level, if carries negative charges, a level lower than the reference level is generated, and the switch bias level generated by the charge pump is the bias level required by the radio frequency switch. The circuit simultaneously enables the frequency-adjustable oscillator, the charge pump, the level detection circuit and the decoding circuit to jointly form a feedback system, so that the stability of the switch bias level of the output of the radio frequency switch bias voltage feedback control circuit is good.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the utility model will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, there is shown in the drawings,
fig. 1 is a circuit configuration diagram of a bias voltage feedback control circuit of a related art rf switch;
fig. 2 is a circuit diagram of a bias voltage feedback control circuit of a radio frequency switch according to a first embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a bias voltage feedback control circuit of an rf switch according to a second embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the utility model refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the utility model. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
(embodiment one)
The utility model provides a bias voltage feedback control circuit 100 of a radio frequency switch. Referring to fig. 2, fig. 2 is a circuit structure diagram of a bias voltage feedback control circuit of an rf switch according to a first embodiment of the utility model.
The radio frequency switch bias voltage feedback control circuit 100 comprises a frequency-adjustable oscillator 1, a charge pump 2, a level detection circuit 3 and a decoding circuit 4 which are connected in sequence. Wherein, the decoding circuit 1 is further connected to the frequency-tunable oscillator 4. The frequency-adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 together form a closed circuit loop.
The frequency-adjustable oscillator 1 is used for generating and outputting a clock signal.
The charge pump 2 is used for generating and outputting N times of switch bias level of an externally input reference level according to the clock signal. Wherein N > 1. The voltage value of the switching bias level is positively correlated with the frequency of the clock signal generated by the frequency tunable oscillator 1.
In the first embodiment, the charge pump 2 includes a voltage stabilizing capacitor. And the positive end of the voltage-stabilizing capacitor is connected to the output end of the charge pump 2 for outputting the switch bias level. And the negative end of the voltage stabilizing capacitor is connected to the ground. The charge pump 2 transfers charges from the reference level input from the outside to the output voltage stabilizing capacitor at the current frequency of the clock signal, so as to provide the switch bias level required by the radio frequency switch.
The level detection circuit 3 is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indication signal.
In this embodiment, the reference level is a fixed voltage input by an external circuit. Of course, without being limited thereto, the level detection circuit 3 internally generates a preset threshold voltage. For example, a fixed threshold voltage may be generated by using a resistor voltage division, and the level detection circuit 3 generates the bias level status indication signal by detecting whether the switch bias level output by the charge pump 2 exceeds or is less than the preset threshold voltage.
In this embodiment, the bias level status indicator is a set of digital signals. Of course, in another embodiment it is also possible that the bias level status indicator signal is an analog signal.
Preferably, the level detection circuit 3 detects and receives the switch bias level output by the charge pump 2 in real time, and this setting can make the switch bias level output by the charge pump 2 continuously adjustable and keep the voltage value stable.
The decoding circuit 4 is used for sequentially performing frequency setting and decoding according to the bias level state indicating signal to be received, and generating and outputting a frequency control signal. The frequency tunable oscillator 1 is further configured to generate the clock signal with a frequency corresponding to the frequency control signal according to the frequency control signal to be received.
In the first embodiment, the decoding circuit 4 is configured to perform the frequency setting according to the bias level status indication signal to be received. Of course, without being limited thereto, the decoding circuit 4 also performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.
In this embodiment, the frequency control signal is a set of digital signals. Of course, in another embodiment, the frequency control signal may be an analog signal.
In this embodiment, the decoding circuit 4 includes a delay processing module (not shown), and the delay processing module is configured to delay an external input signal of the decoding circuit 4 or an intermediate signal inside the decoding circuit 4. The delay processing module can reduce the output glitch of the charge pump 2 caused by the overlarge frequency change of the clock signal of the charge pump 2, and meanwhile, the frequency adjustable oscillator 1 which is not wrong when the level detection circuit 3 judges by mistake is used for generating the frequency of the clock signal.
In this embodiment, the frequency control signal can control the frequency of the clock signal in real time. This arrangement allows the switch bias level output by the charge pump 2 to be continuously adjusted and to keep the voltage level stable.
The rf switch bias voltage feedback control circuit 100 generates a higher level than the reference level by the charge pump 2 periodically carrying positive charges accumulated above the reference level, and generates a lower level than the reference level if carrying negative charges, so that the switch bias level generated by the charge pump 2 is the bias level required by the rf switch. Meanwhile, the level detection circuit 3 continuously detects the switch bias level output by the charge pump 2, and the level detection circuit 3 compares the switch bias level with the reference level and generates the bias level state indicating signal to continuously adjust the decoding circuit 4. Therefore, the frequency-adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 jointly form a feedback system.
When the on/off state of the radio frequency switch is changed, the amplitude of the switch bias level is instantly reduced, the level detection circuit 3 detects the state change at the moment, and the bias level state indication signal is output to indicate that the frequency of the clock signal of the frequency-adjustable oscillator 1 needs to be adjusted at the moment so as to improve the driving capability of the charge pump 2, so that the radio frequency switch quickly returns to the normal working state.
When the rf power input by the rf switch becomes larger, due to a non-linear reason, the load of the charge pump 2 is changed from a capacitive load to a capacitive superimposed dc load, the amplitude of the switch bias level at this time is reduced and maintained, the level detection circuit 3 detects a state change, and outputs the bias level state indication signal to indicate that the frequency of the clock signal of the frequency-tunable oscillator 1 needs to be adjusted at this time to improve the driving capability of the charge pump 2, so as to maintain a sufficient switch bias level until the rf power becomes smaller. Therefore, the stability of the switch bias level of the output of the rf switch bias voltage feedback control circuit 100 is good.
It should be noted that the frequency-tunable oscillator 1, the charge pump 2, the level detection circuit 3, and the decoding circuit 4 adopted in the present invention are all circuits commonly used in the art, and the specific circuit result and performance index are adjusted according to the actual application, which is not described in detail herein.
(second embodiment)
The second embodiment of the utility model provides a radio frequency switch bias voltage feedback control circuit with a specific circuit structure. Referring to fig. 3, fig. 3 is a schematic circuit diagram of a bias voltage feedback control circuit of an rf switch according to a second embodiment of the utility model.
In the second embodiment, the level detection circuit 3 includes a comparator COMP, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS, and a voltage-dividing impedance Z2, where the voltage-dividing impedance ZS is a variable impedance.
The specific circuit structure of the level detection circuit 3 is as follows:
a first terminal of the voltage-dividing impedance Z1 is connected to a supply voltage.
The second end of the voltage-dividing impedance Z1 is respectively connected to the negative input end of the comparator COMP and the first end of the voltage-dividing impedance ZS.
A positive input terminal of the comparator COMP serves as a reference level input terminal of the level detection circuit 3.
An output end of the comparator COMP serves as a bias level state indicating signal output end of the level detection circuit 3, and the output end of the comparator COMP is connected to an adjusting end of the voltage-dividing impedance ZS.
The second end of the partial pressure impedance ZS is connected to the second end of the partial pressure impedance Z2.
A first terminal of the voltage-dividing impedance Z2 serves as an input terminal of the level detection circuit 3.
And the connecting points of the negative input end of the comparator COMP and the voltage-dividing impedance Z1 and the voltage-dividing impedance ZS are VS respectively.
When the bias level state indicating signal is high, the voltage-dividing impedance ZS is close to 0 ohm, and when the bias level state indicating signal is low, the voltage-dividing impedance ZS is far larger than 0 ohm. The potential at VS at any time is:
when the reference level VREF does not reach the required level, the bias level state indicating signal is low, the voltage dividing impedance ZS is far larger than 0 ohm, and the VS voltage value is larger than the reference level VREF. As the voltage amplitude of the reference level VNEG becomes larger, the VS voltage value approaches the reference level VREF until the VS voltage value is slightly larger than the reference level VREF, at which point the bias level status indicator signal flips high, at which point:
when the bias level state indicating signal is high, the voltage-dividing impedance ZS is close to 0 ohm, so that the level of VS is suddenly changed to:
the above process can complete the hysteresis process, thereby avoiding output oscillation caused by noise and interference, and at the same time, the output of the level detection circuit 3 will not be completely locked, so that the detection function is maintained.
The decoding circuit 4 comprises an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a schmitt trigger ST1, a schmitt trigger ST2, a three-input and gate ANDB and a 8421 decoder.
The circuit structure of the decoding circuit 4 is:
the positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is respectively connected to the gate of the transistor PM1, the first input terminal of the three-input and gate ANDB, and the first input terminal of the 8421 decoder.
A negative terminal of the inverter INV1 is connected to the first terminal of the resistor R1.
A second terminal of the resistor R2 is connected to the positive terminal of the capacitor C1, the input terminal of the schmitt trigger ST1, and the drain of the transistor PM1, respectively. The negative terminal of the capacitor C1 is connected to ground. The source of the transistor PM1 is connected to a supply voltage.
An output end of the schmitt trigger ST1 is connected to a positive electrode end of the inverter INV2, a gate of the transistor NM1, and a third input end of the three-input and gate ANDB, respectively.
A negative terminal of the inverter INV2 is connected to the first terminal of the resistor R2.
A second terminal of the resistor R2 is connected to the negative terminal of the capacitor C2, the input terminal of the schmitt trigger ST2, and the drain of the transistor NM1, respectively. The positive end of the capacitor C2 is connected to a power supply voltage; the source of the transistor NM1 is connected to ground.
The output of the schmitt trigger ST2 is connected to a second input of the three-input and gate ANDB.
The output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder.
A third input terminal of the 8421 decoder serves as a frequency setting input terminal of the decoding circuit 4;
the output end of the 8421 decoder serves as the output end of the decoding circuit 4.
In the second embodiment, the inverter INV1, the resistor R1, the capacitor C1, the transistor PM1 and the schmitt trigger ST1 in the decoding circuit 4 constitute a first-stage single-edge delay, and the inverter INV2, the resistor R2, the capacitor C2, the transistor NM1 and the schmitt trigger ST2 in the decoding circuit 4 constitute a second-stage single-edge delay. The three-input and gate ANDB and 8421 decoder implements the decoding function. Wherein the frequency setting input VCH is used to control the frequency setting of the 8421 decoder.
The first stage single-edge delayer is used for outputting a high level immediately when the input signal is inverted from a high level to a low level, and delaying to generate a low level when the input signal is inverted from a low level to a high level, wherein the delay time is determined by the product of a resistor R1 and a capacitor C1. The second stage single-edge delayer is used for outputting a low level immediately when the input signal is inverted from a low level to a high level, and delaying to generate a high level when the input signal is inverted from a high level to a low level, wherein the delay time is determined by the product of a resistor R2 and a capacitor C2.
In the second embodiment, the frequency tunable oscillator 1 is a ring oscillator, and is composed of the inverter INV3 of the frequency tunable oscillator 1 and an even-order inverter chain, the frequency is determined by the controlled current source CS of the frequency tunable oscillator 1 and the load capacitor C3, and when the controlled current source CS is set to be a small current, the clock signal period is long; when the controlled current source CS is set to a medium current, the clock signal period is short; when the controlled current source CS is set to a large current, the clock signal period is extremely short.
In the second embodiment, the charge pump 2 is composed of a non-overlapping clock generator and a mutually-biased symmetrical charge pump, two phases of a clock can be fully utilized to charge a voltage stabilizing capacitor C4 of the charge pump 2, and a switch bias level VNEG is an output end of the charge pump 2.
The decoding circuit 4 and the frequency-adjustable oscillator 1 together form a frequency-variable oscillator with a delay function. In particular, the method comprises the following steps of,
when the bias level state indicating signal is high, the frequency tunable oscillator 1 outputs a clock signal having a very low frequency to reduce power consumption of the entire system.
When the bias level state indicating signal changes from high to low, the frequency tunable oscillator 1 immediately outputs a clock signal with a very high frequency to enhance the driving of the charge pump 2.
When the bias level state indicating signal changes from low to high, the frequency-adjustable oscillator 1 outputs a clock signal with a medium frequency for a period of time, so that the charge pump 2 is driven to be reduced, then the frequency-adjustable oscillator 1 outputs a clock signal with a very low frequency, and the charge pump 2 returns to normal operation.
If the amplitude of the switch bias level is reduced due to the fact that the radio-frequency power input by the radio-frequency switch is increased, the level detection circuit 3 can continuously output a low level to enable the frequency-adjustable oscillator 1 to always maintain a high-frequency clock signal, and the level of the switch bias level VNEG is maintained by consuming larger power, so that the working state of the radio-frequency switch is guaranteed.
It should be noted that the related circuits, modules and components adopted in the present invention are all circuits, modules and components commonly used in the art, and the corresponding specific indexes and parameters are adjusted according to the actual application, which is not described in detail herein.
Compared with the prior art, the radio frequency switch bias voltage feedback control circuit is provided with the level detection circuit, the decoding circuit and the frequency-adjustable oscillator, wherein the level detection circuit compares the switch bias level output by the charge pump with a preset reference level and generates and outputs a bias level state indication signal; the bias level state indicating signal is decoded by a decoding circuit to generate and output a frequency control signal, and then the frequency control signal is used by the frequency adjustable oscillator to generate the clock signal with the frequency corresponding to the frequency control signal, so that the charge pump generates and inputs a corresponding switch bias level according to the clock signal, the charge pump periodically carries positive charges to be accumulated above the reference level to generate a level higher than the reference level, if carries negative charges, a level lower than the reference level is generated, and the switch bias level generated by the charge pump is the bias level required by the radio frequency switch. The circuit simultaneously enables the frequency-adjustable oscillator, the charge pump, the level detection circuit and the decoding circuit to jointly form a feedback system, so that the stability of the switch bias level of the output of the radio frequency switch bias voltage feedback control circuit is good.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (10)
1. A radio frequency switch bias voltage feedback control circuit comprises a frequency-adjustable oscillator and a charge pump which are sequentially connected; the frequency adjustable oscillator is used for generating and outputting a clock signal; the charge pump is used for generating and outputting N times of switch bias level of an externally input reference level according to the clock signal; wherein N > 1; the radio frequency switch bias voltage feedback control circuit is characterized by further comprising a level detection circuit and a decoding circuit which are sequentially connected;
the level detection circuit is also connected with the charge pump and is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indication signal;
the decoding circuit is also connected with the frequency-adjustable oscillator and is used for sequentially carrying out frequency setting, decoding according to the received bias level state indicating signal and generating and outputting a frequency control signal;
the frequency adjustable oscillator is further used for generating the clock signal with the frequency corresponding to the frequency control signal according to the frequency control signal to be received.
2. The rf switch bias voltage feedback control circuit of claim 1, wherein the level detection circuit detects and receives the switch bias level of the charge pump output in real time;
the level detection circuit comprises a comparator, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS and a voltage-dividing impedance Z2, wherein the voltage-dividing impedance ZS is variable impedance;
a first end of the voltage-dividing impedance Z1 is connected to a power supply voltage;
the second end of the voltage-dividing impedance Z1 is respectively connected to the negative input end of the comparator and the first end of the voltage-dividing impedance ZS;
a positive input end of the comparator is used as a reference level input end of the level detection circuit;
the output end of the comparator is used as the bias level state indicating signal output end of the level detection circuit, and the output end of the comparator is connected to the adjusting end of the voltage-dividing impedance ZS;
the second end of the partial pressure impedance ZS is connected to the second end of the partial pressure impedance Z2;
a first terminal of the voltage-dividing impedance Z2 serves as an input terminal of the level detection circuit.
3. The rf switch bias voltage feedback control circuit of claim 1, wherein the bias level status indicator signal is a set of digital or analog signals.
4. The rf switch bias voltage feedback control circuit of claim 1, wherein the reference level is a fixed voltage inputted by an external circuit or a preset threshold voltage generated inside the level detection circuit.
5. The rf switch bias voltage feedback control circuit of claim 1, wherein the decoding circuit performs the frequency setting according to an externally input frequency control signal or performs the frequency setting according to a preset condition.
6. The rf switch bias voltage feedback control circuit of claim 1, wherein the decoding circuit is configured to perform the frequency setting according to the bias level status indication signal to be received;
the decoding circuit comprises an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, a three-input AND gate ANDB and a 8421 decoder;
the positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is respectively connected to the gate of the transistor PM1, the first input terminal of the three-input and gate ANDB and the first input terminal of the 8421 decoder;
a negative electrode terminal of the inverter INV1 is connected to the first terminal of the resistor R1;
a second end of the resistor R2 is connected to a positive terminal of the capacitor C1, an input terminal of the schmitt trigger ST1, and a drain of the transistor PM1, respectively; the negative terminal of the capacitor C1 is connected to the ground; the source of the transistor PM1 is connected to a supply voltage;
an output end of the schmitt trigger ST1 is respectively connected to a positive electrode end of the inverter INV2, a gate of the transistor NM1, and a third input end of the three-input and gate ANDB;
a negative electrode terminal of the inverter INV2 is connected to the first terminal of the resistor R2;
a second end of the resistor R2 is connected to the negative terminal of the capacitor C2, the input terminal of the schmitt trigger ST2, and the drain of the transistor NM1, respectively; the positive end of the capacitor C2 is connected to a power supply voltage; the source of the transistor NM1 is connected to ground;
the output end of the Schmitt trigger ST2 is connected to the second input end of the three-input AND gate ANDB;
the output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder;
a third input end of the 8421 decoder is used as a frequency setting input end of the decoding circuit;
the output end of the 8421 decoder serves as the output end of the decoding circuit.
7. The rf switch bias voltage feedback control circuit of claim 1, wherein the frequency control signal is a set of digital or analog signals.
8. The rf switch bias voltage feedback control circuit of claim 1, wherein the decoding circuit comprises a delay processing module, and the delay processing module is configured to delay an external input signal of the decoding circuit or an intermediate signal inside the decoding circuit.
9. The rf switch bias voltage feedback control circuit of claim 1, wherein the frequency control signal controls the frequency of the clock signal in real time.
10. The rf switch bias voltage feedback control circuit according to claim 1, wherein the charge pump includes a voltage stabilizing capacitor, a positive terminal of the voltage stabilizing capacitor is connected to an output terminal of the charge pump for outputting the switch bias level, and a negative terminal of the voltage stabilizing capacitor is connected to ground.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122519735.3U CN215932482U (en) | 2021-10-19 | 2021-10-19 | Bias voltage feedback control circuit of radio frequency switch |
| PCT/CN2022/078368 WO2023065583A1 (en) | 2021-10-19 | 2022-02-28 | Radio frequency switch bias voltage feedback control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202122519735.3U CN215932482U (en) | 2021-10-19 | 2021-10-19 | Bias voltage feedback control circuit of radio frequency switch |
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| CN215932482U true CN215932482U (en) | 2022-03-01 |
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| CN202122519735.3U Active CN215932482U (en) | 2021-10-19 | 2021-10-19 | Bias voltage feedback control circuit of radio frequency switch |
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| CN (1) | CN215932482U (en) |
| WO (1) | WO2023065583A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115378459A (en) * | 2022-09-01 | 2022-11-22 | 江苏卓胜微电子股份有限公司 | Radio frequency switch control link, system and control method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667774B (en) * | 2008-09-02 | 2012-05-16 | 北京兆易创新科技有限公司 | Closed-loop control charge pump circuit |
| TWI505617B (en) * | 2011-09-21 | 2015-10-21 | United Microelectronics Corp | Charge pump system capable of stablizing an output voltage |
| US8917126B1 (en) * | 2013-12-23 | 2014-12-23 | International Business Machines Corporation | Charge pump operating voltage range control using dynamic biasing |
| CN108718195B (en) * | 2018-04-17 | 2022-05-13 | 北京时代民芯科技有限公司 | Charge pump phase-locked loop adopting configurable starting circuit |
| US20190326915A1 (en) * | 2018-04-19 | 2019-10-24 | Qualcomm Incorporated | Sampling Phase-Locked Loop (PLL) |
| CN110113039A (en) * | 2019-05-16 | 2019-08-09 | 上海猎芯半导体科技有限公司 | A kind of biasing circuit and frequency communication devices for RF switch |
| CN209692726U (en) * | 2019-05-16 | 2019-11-26 | 上海猎芯半导体科技有限公司 | A kind of biasing circuit and frequency communication devices for RF switch |
| CN111030661A (en) * | 2019-05-16 | 2020-04-17 | 上海猎芯半导体科技有限公司 | Biasing circuit and radio frequency communication device |
| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
| CN213426126U (en) * | 2020-11-30 | 2021-06-11 | 开元通信技术（厦门）有限公司 | Radio frequency switch negative voltage bias circuit and radio frequency switch system |
-
2021
- 2021-10-19 CN CN202122519735.3U patent/CN215932482U/en active Active
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115378459A (en) * | 2022-09-01 | 2022-11-22 | 江苏卓胜微电子股份有限公司 | Radio frequency switch control link, system and control method thereof |
| CN115378459B (en) * | 2022-09-01 | 2023-06-23 | 江苏卓胜微电子股份有限公司 | Radio frequency switch control link, system and control method thereof |
| WO2024046104A1 (en) * | 2022-09-01 | 2024-03-07 | 江苏卓胜微电子股份有限公司 | Radio-frequency switch control link and system and control method for radio-frequency switch control link |
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| WO2023065583A1 (en) | 2023-04-27 |
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