CN110113039A - A kind of biasing circuit and frequency communication devices for RF switch - Google Patents
A kind of biasing circuit and frequency communication devices for RF switch Download PDFInfo
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- CN110113039A CN110113039A CN201910411459.3A CN201910411459A CN110113039A CN 110113039 A CN110113039 A CN 110113039A CN 201910411459 A CN201910411459 A CN 201910411459A CN 110113039 A CN110113039 A CN 110113039A
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- type flip
- logic control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0081—Power supply means, e.g. to the switch driver
Abstract
The invention discloses a kind of biasing circuit and frequency communication devices for RF switch, which includes control circuit, oscillator and charge pump；Oscillator is arranged to export clock signal to charge pump；Charge pump is arranged to export bias voltage according to clock signal, works for RF switch；Control circuit is arranged to when the switch state for detecting RF switch changes, and control oscillator increases the frequency of clock signal within the set duration, to increase the voltage amplitude of bias voltage.
Description
Technical field
The present invention relates to technical field of circuit design, more particularly, to a kind of biasing circuit for RF switch and
Frequency communication devices.
Background technique
RF switch is widely used in the radio-frequency front-end design of wireless communication device, can be applied to various need to radio frequency
The occasion that the on or off state of transmission signal control effectively, for example radio-frequency transmissions switch, reception switch, channel choosing
Select switch, antenna tuning switch etc..The considerations of for cost and integrated level and manufacturing process technology are horizontal gradually to be mentioned
It rises, mobile communications device field mainly uses and introduces one layer of buries oxide layer (SOI) between top layer silicon and backing bottom at present, raw
RF switch chip is made at the technique of complementary metal oxide semiconductor (CMOS).Such cake core generally will use negative voltage
Biasing circuit, to improve switch cutoff performance.But biasing circuit typically contains the parts such as oscillator and charge pump.
The existing negative voltage bias circuit for RF switch can be as shown in Figure 1, generally including oscillator and electricity
Lotus pump.Oscillator is generally started to work after RF switch starting, provides clock CK to charge pump.Charge pump by clock and
Fly capacitor (flying capacitor) coupling path and the charge in output capacitance periodically move, realizes the defeated of bias voltage
Out.Assuming that RF switch includes two paths: access 1 and access 2.By the logic level change of logic control signal DIN, make
RF switch by the conducting of access 1, the state ended of access 2, can be with when being switched to the cut-off of access 1, the state that access 2 is connected
Think that suddenly change occurs for the load condition of biasing circuit connection.
When suddenly change occurs for the load condition of biasing circuit connection, when for example the access of RF switch switches over,
Due to loading the charge and discharge of itself and releasing for other circuits, i.e. biggish mutation can occur for the capacitive load of biasing circuit,
It is limited to the response speed and driving capability of charge pump in biasing circuit, causes the energy of bias voltage that can generate certain damage
It loses, the voltage amplitude moment of bias voltage is caused to decline.If the voltage amplitude of bias voltage does not have within defined switching time
There is recovery normal, it is likely that influence the performance of RF switch.
Summary of the invention
One purpose of the embodiment of the present invention, which is to provide one kind, to be mentioned when the switch state of RF switch changes
The technical solution of the driving capability of high bias voltage.
According to the first aspect of the invention, a kind of biasing circuit for RF switch, including control circuit, vibration are provided
Swing device and charge pump；
The oscillator is arranged to export clock signal to the charge pump；The charge pump is arranged to according to
Clock signal exports bias voltage, works for the RF switch；
The control circuit is arranged to when detecting that the switch state of the RF switch changes, described in control
Oscillator increases the frequency of the clock signal within the set duration, to increase the voltage amplitude of the bias voltage.
Optionally, the biasing circuit further include: the logic control of the switch state for RF switch described in input control
The input terminal of signal processed；
The control circuit is arranged to when detecting that the logic state of the logic control signal changes, and determines
Detect that the switch state of the RF switch changes.
Optionally, the control circuit is arranged to output regulation signal to the oscillator；The oscillator is set
For output frequency clock signal corresponding with the level state of the adjustment signal, for the charge pump output voltage amplitude with
The corresponding bias voltage of the level state of the adjustment signal；
The control circuit is arranged to when detecting that the logic state of the logic control signal changes, in institute
State the level state of the overturning adjustment signal in setting duration.
Optionally, the level state after the adjustment signal is reversed is high level；The control circuit is prolonged including first
Slow circuit and the first XOR gate；
First delay circuit is arranged to carry out postponing the processing of the setting duration to the logic control signal,
The logic control signal postponed；
First XOR gate is arranged to carry out the logic control signal of the logic control signal and the delay
XOR logic processing, obtains the adjustment signal.
Optionally, the control circuit includes the second delay circuit, the second XOR gate and timer,
Second delay circuit is arranged to carry out postponing the processing of another setting duration to the logic control signal,
Obtain the logic control signal of another delay；Another setting duration is less than the setting duration；
Second XOR gate is arranged to the logic control signal to the logic control signal and another delay
XOR logic processing is carried out, timing signal is obtained and is exported to the timer；
The timer is arranged to export the adjustment signal, and when receiving the rising edge of the timing signal,
The level state of the adjustment signal is overturn in the setting duration.
Optionally, the setting duration is equal to the period of N number of clock signal, wherein N is positive integer；
The timer includes phase inverter, Fractional-N frequency circuit and the first d type flip flop；
The Fractional-N frequency circuit is arranged to carry out Fractional-N frequency processing to the clock signal, obtains N sub-frequency clock signal,
And it is input to the clock end of first d type flip flop；
The phase inverter is arranged to export after carrying out reverse phase processing to the timing signal to first d type flip flop
Clear terminal；
The first d type flip flop input terminal is connect with the reversed-phase output of itself, the output end quilt of first d type flip flop
It is set as exporting the adjustment signal.
Optionally, the M power that N is 2, wherein M is positive integer；
The Fractional-N frequency circuit includes M cascade second d type flip flops；
The input terminal of each second d type flip flop is connect with the reversed-phase output of itself, the second d type flip flop of previous stage
Output end is connected with the clock end of corresponding the second d type flip flop of next stage, and the clock end of first the second d type flip flop is arranged to
The clock signal is inputted, the output end of the second d type flip flop of m-th is connect with the clock end of first d type flip flop.
Optionally, the biasing circuit can also include clock processing module, and the clock processing module be arranged to pair
The clock signal carries out frequency dividing or process of frequency multiplication, and will treated clock signal transmission to the charge pump, for the electricity
Treated described in lotus pump basis, and clock signal exports the bias voltage.
Optionally, the oscillator is relaxor.
According to the second aspect of the invention, a kind of frequency communication devices are improved, including RF switch and according to the present invention
Biasing circuit described in first aspect, the biasing circuit is arranged to provide bias voltage to the RF switch, for described
RF switch work.
In an embodiment of the present invention, control circuit exports the frequency of clock signal by control oscillator increase, so that
The voltage amplitude of the bias voltage of charge pump output increases, and then the driving capability of bias voltage can be improved.In this way, can reach
To maintenance or the purpose of fast quick-recovery negative voltage amplitude, and then the performance of RF switch can be kept.
By referring to the drawings to the detailed description of exemplary embodiment of the present invention, other feature of the invention and its
Advantage will become apparent.
Detailed description of the invention
It is combined in the description and the attached drawing for constituting part of specification shows the embodiment of the present invention, and even
With its explanation together principle for explaining the present invention.
Fig. 1 is the structural schematic diagram of existing biasing circuit；
Fig. 2 is the diagrammatic view in principle block diagram according to first example of the biasing circuit of the embodiment of the present invention；
Fig. 3 is the schematic circuit diagram figure according to second example of the biasing circuit of the embodiment of the present invention；
Fig. 4 is the schematic circuit diagram figure according to the third example of the biasing circuit of the embodiment of the present invention.
Specific embodiment
Carry out the various exemplary embodiments of detailed description of the present invention now with reference to attached drawing.It should also be noted that unless in addition having
Body explanation, the unlimited system of component and the positioned opposite of step, numerical expression and the numerical value otherwise illustrated in these embodiments is originally
The range of invention.
Be to the description only actually of at least one exemplary embodiment below it is illustrative, never as to the present invention
And its application or any restrictions used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of, the technology, method and apparatus should be considered as part of specification.
It is shown here and discuss all examples in, any occurrence should be construed as merely illustratively, without
It is as limitation.Therefore, other examples of exemplary embodiment can have different values.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, then in subsequent attached drawing does not need that it is further discussed.
<biasing circuit>
Fig. 2 is the diagrammatic view in principle block diagram according to the biasing circuit for RF switch of the embodiment of the present invention.
According to Fig.2, which includes control circuit U1, oscillator U2 and charge pump U3.
Oscillator U2 is arranged to export clock signal CK to charge pump U3, and charge pump U3 is arranged to be believed according to the clock
Number CK exports bias voltage VNG.In one example, biasing circuit can be output bias voltage VNG to RF switch, for
RF switch work.
Control circuit U1 is arranged to when the switch state for detecting RF switch changes, and control oscillator U2 exists
The frequency for increasing clock signal in duration is set, to increase the voltage amplitude of bias voltage.
When the switch state of RF switch changes, the load condition of bias voltage is driven to change.Control electricity
Road U1 exports the frequency of clock signal by control oscillator U2 increase, so that the voltage amplitude of the bias voltage of charge pump U3 output
Degree increases, and then the driving capability of bias voltage can be improved.In this way, can achieve maintenance or fast quick-recovery negative voltage amplitude
Purpose, and then the performance of RF switch can be kept.
In one embodiment, for the RF switch being arranged in frequency communication devices, usually there are multiple channels.?
In frequency communication devices, logic control circuit is also typically included, logic control circuit is arranged to export at least one logic control
Signal processed, to control the switch state of RF switch according to the logic state of the logic control signal, namely control radio frequency is opened
The corresponding channel conductive in the Central Shanxi Plain.
Therefore, as shown in figure 3, the biasing circuit can also include patrolling for the switch state for input control RF switch
Collect the input terminal DIN of control signal.So, control circuit U1 can be set in the logic shape for detecting logic control signal
When state changes, the switch state for confirmly detecting RF switch changes.
Specifically, control circuit U1 can be the output end output regulation signal TRIG to oscillator U2 by itself, supply
Oscillator U2 output frequency clock signal corresponding with the level state of adjustment signal TRIG, for charge pump U3 output voltage
Amplitude bias voltage corresponding with the level state of adjustment signal TRIG.
Oscillator U2 can be the clock that output can be arbitrarily adjusted according to the voltage or logic level state of input signal
The oscillator of the frequency of signal.For example, oscillator U2 can be voltage controlled oscillator, it is also possible to relaxor.
In one embodiment, oscillator U2 can be relaxor.As shown in Fig. 3~Fig. 4, which can
To include adjustable current source IB, first capacitor C1, the first phase inverter Inv1, the second phase inverter Inv2 and third phase inverter Inv3.
Wherein, the input terminal of the first phase inverter Inv1 is connect with the output end of third phase inverter Inv3, the output of the first phase inverter Inv1
End is connect with the input terminal of the second phase inverter Inv2, the input of the output end and third phase inverter Inv3 of the second phase inverter Inv2
End connection.Adjustable current source IB can be the input terminal VREG2 for being connected to the supply voltage of oscillator and the first phase inverter Inv1
Operating voltage input terminal between, the bias current control terminal of adjustable current source IB is connect with the output end of control circuit U1.
First capacitor C1 is connected between the output end and ground terminal GND of the first phase inverter Inv1.The output end of third phase inverter Inv3
Output end as clock signal CK.
Oscillator U2 is arranged to the signal inputted according to the bias current control terminal of adjustable current source IB, adjusts adjustable electric
The bias current of stream source IB output, with output frequency and the matched clock signal of adjustment signal TRIG.
In such as Fig. 3~embodiment shown in Fig. 4, charge pump U3 may include the first buffer cell Buf1, the second electricity
Hold C2, third capacitor C3, first diode Diode1 and the second diode Diode2.The input terminal of first buffer cell U31 with
The output end of the clock signal CK of oscillator U2 connects, and the second capacitor C2 is connected to the output end and the of the first buffer cell U31
Between the cathode of two diode Diode2, the anode of the second diode Diode2 is connect with the output end of bias voltage VNG.The
The anode of one diode Diode1 is connect with the cathode of the second diode Diode2, the cathode of first diode Diode1 and ground connection
GND connection is held, third capacitor C3 is connected between the output and ground GND of bias voltage VNG.
Wherein, first diode Diode1 and the second diode Diode2 can be substituted by metal-oxide-semiconductor.
In the present embodiment, control circuit U1 may be also configured in the logic state hair for detecting logic control signal
When raw change, the level state of adjustment signal TRIG is overturn within the set duration.For example, in the logic state of logic control signal
Before changing, when the level state of adjustment signal TRIG is low level, if control circuit U1 is detecting logic control
The logic state of signal changes, then can be within the set duration high electricity by the level state overturning of adjustment signal TRIG
It is flat, and overturning is low level again after setting duration.For another example the logic state in logic control signal changes it
Before, when the level state of adjustment signal TRIG is high level, if control circuit U1 is in the logic for detecting logic control signal
State changes, then can within the set duration overturn the level state of adjustment signal TRIG for low level, and setting
Overturning is high level again after duration.
Before the logic state of logic control signal changes, the level state of adjustment signal TRIG is low level
In embodiment, as shown in figure 3, control circuit U1 may include the first delay circuit U11 and the first XOR gate XOR1.Wherein,
One delay circuit U11 is arranged to carry out logic control signal the processing of delay setting duration, the logic control postponed
Signal.First XOR gate XOR1 is arranged to carry out at XOR logic the logic control signal of logic control signal and delay
Reason, obtains adjustment signal TRIG.
Before the logic state of logic control signal changes, the logic control signal of logic control signal and delay
Level state it is identical, therefore the first XOR gate XOR1 output adjustment signal TRIG be low level.Due to the first delay circuit
U11 carries out the processing of delay setting duration to logic control signal, then, it changes in the logic state of logic control signal
In setting duration afterwards, logic control signal is different with the level state of the logic control signal of delay, therefore the first XOR gate
The adjustment signal TRIG that XOR1 is exported within the set duration is reversed as high level.Occur in the logic state of logic control signal
After the setting duration of change, logic control signal is identical with the level state of the logic control signal of delay, therefore the first exclusive or
The adjustment signal TRIG of door XOR1 output is reversed again as low level.
Before the logic state of logic control signal changes, the level state of adjustment signal TRIG is low level
In another embodiment, as shown in figure 4, control circuit U1 may include the second delay circuit U12, the second XOR gate XOR2 and meter
When device U13.Second delay circuit U12 is arranged to carry out postponing the processing of another setting duration to logic control signal, obtains
The logic control signal of another delay, wherein another setting duration is less than setting duration above-mentioned.Second XOR gate XOR2 is set
It is set to and XOR logic processing is carried out to the logic control signal of logic control signal and another delay, obtain timing signal and export
To timer U13.Timer U13 is arranged to output regulation signal TRIG, and in the rising edge for receiving timing signal,
Setting duration varus turns the level state of adjustment signal TRIG.
Specifically, before the logic state of logic control signal changes, the logic of logic control signal and delay
The level state for controlling signal is identical, therefore the timing signal of the second XOR gate XOR2 output is low level.Due to the second delay
Circuit U 12 postpone to logic control signal the processing of another setting duration, then, in the logic state of logic control signal
In another setting duration after changing, the level state of the logic control signal of logic control signal and another delay is not
Together, therefore the second XOR gate XOR2 is reversed in another timing signal exported in duration that sets as high level.In logic control
After another setting duration that the logic state of signal changes, the logic control signal of logic control signal and another delay
Level state is identical, therefore the timing signal of the second XOR gate XOR2 output is reversed again as low level.
Before the logic state of logic control signal changes, the second XOR gate XOR2 exports low level timing letter
Number, timer U13 also exports low level adjustment signal TRIG.The second XOR gate XOR2 logic control signal logic shape
The timing signal exported when state changes is reversed by low level as high level, and timer U13 can receive timing signal
Rising edge, and receiving in the setting duration after the rising edge export high level adjustment signal TRIG.In logic control
After the logic state of signal changes setting duration, timer U13 exports low level adjustment signal TRIG again.
In the present embodiment, setting duration can be the period equal to N number of clock signal, wherein N is positive integer.That
, timer U13 may include phase inverter NOT1, Fractional-N frequency circuit U 131 and the first d type flip flop DFF1.Fractional-N frequency circuit
U131 is arranged to carry out Fractional-N frequency processing to clock signal, obtains Fractional-N frequency clock signal and is input to the first d type flip flop DFF1
Clock end CK1.Phase inverter NOT1 is arranged to export after carrying out reverse phase processing to timing signal to the first d type flip flop DFF1
Clear terminal R1.The input terminal D1 of first d type flip flop DFF1 is connect with the reversed-phase output QN1 of itself, the first d type flip flop
The output end Q1 of DFF1 is arranged to output regulation signal TRIG, the bias current control with adjustable current source IB in oscillator U2
End connection.
On this basis, N can be 2 M power, wherein M is positive integer, then, N frequency dividing circuit U131 may include
M cascade second d type flip flops.The input terminal of each second d type flip flop is connect with the reversed-phase output of itself, and the of previous stage
The output end of two triggers is connected with the clock end of corresponding the second d type flip flop of next stage, the clock end of first the second d type flip flop
It is arranged to input clock signal, the output end of the second d type flip flop of m-th is connect with the clock end of the first d type flip flop.Each
The clear terminal of 2-D trigger is connect with the output end of phase inverter NOT1.
In the embodiment as shown in fig.4, M can be 2, then, N can be 22 powers, i.e. N is 4, then, Fractional-N frequency
Circuit U 131 includes 2 cascade second d type flip flop DFF21 and DFF22.The input terminal D21 of second d type flip flop DFF21 with from
The reversed-phase output QN21 connection of body, the input terminal D22 of the second d type flip flop DFF12 and the reversed-phase output QN22 of itself connect
It connects.The clear terminal R22 of the clear terminal R21 of second d type flip flop DFF21 and the second d type flip flop DFF22 are with phase inverter NOT1's
Output end connection.The output end of the clock signal CK of the clock end CK21 and oscillator U2 of second d type flip flop DFF21 are connect, the
The output end Q21 of 2-D trigger DFF21 is connect with the clock end CK22 of the second d type flip flop DFF22, the second d type flip flop DFF12
Output end Q22 connect with the clock end CK1 of the first d type flip flop DFF1.The input terminal D1 of first d type flip flop DFF1 and itself
Reversed-phase output QN1 connection, the output end Q1 of the first d type flip flop DFF1 as adjustment signal TRIG output end, with oscillation
The bias current control terminal connection of adjustable current source IB in device U2.
Before the logic state of logic control signal changes, the level state of adjustment signal TRIG is high level
In embodiment, control circuit U1 may include third delay circuit and with or door, wherein third delay circuit is arranged to patrolling
Collect the processing that control signal carries out delay setting duration, the logic control signal postponed.Same or door is arranged to logic
The logic control signal for controlling signal and delay carries out same or logical process, obtains adjustment signal TRIG.
Before the logic state of logic control signal changes, the logic control signal of logic control signal and delay
Level state it is identical, therefore with or door output adjustment signal TRIG be high level.Since third delay circuit is to logic control
Signal processed carries out the processing of delay setting duration, then, in the setting after the logic state of logic control signal changes
In length, logic control signal is different with the level state of the logic control signal of delay, what same or door exported within the set duration
Adjustment signal TRIG is reversed as low level.After the setting duration that the logic state of logic control signal changes, logic
Control signal is identical with the level state of the logic control signal of delay, and the adjustment signal TRIG of same or door output is reversed again
For high level.
Before the logic state of logic control signal changes, the level state of adjustment signal TRIG is high level
In another embodiment, control circuit U1 be can be including the second delay circuit U12, the second XOR gate in previous embodiment
It further include phase inverter on the basis of XOR2 and timer U13, which is arranged to the adjusting letter exported to timer U13
Number TRIG carry out reverse phase processing after, the bias current control terminal of output to adjustable current source IB in oscillator U2.Physical circuit knot
Structure is referred to embodiment above-mentioned, and details are not described herein.
In one embodiment, which can also include clock processing module, which is set
Clock signal to export to oscillator U2 carries out frequency dividing or process of frequency multiplication, and will treated clock signal transmission to charge pump
U3, so that clock signal exports bias voltage to charge pump U3 according to treated.
<frequency communication devices>
The present invention also provides a kind of frequency communication devices, which may include RF switch and aforementioned
Biasing circuit in embodiment, wherein biasing circuit is arranged to provide bias voltage to RF switch, for RF switch work
Make.
In one embodiment, which can be negative, to improve the cutoff performance of RF switch.
Various embodiments of the present invention are described above, above description is exemplary, and non-exclusive, and
It is not limited to disclosed each embodiment.Without departing from the scope and spirit of illustrated each embodiment, for this skill
Many modifications and changes are obvious for the those of ordinary skill in art field.The selection of term used herein, purport
In principle, the practical application or to the technological improvement in market for best explaining each embodiment, or make the art its
Its those of ordinary skill can understand each embodiment disclosed herein.The scope of the present invention is defined by the appended claims.
Claims (10)
1. a kind of biasing circuit for RF switch, which is characterized in that including control circuit, oscillator and charge pump；
The oscillator is arranged to export clock signal to the charge pump；The charge pump is arranged to according to the clock
Signal exports bias voltage, works for the RF switch；
The control circuit is arranged to control the oscillation when detecting that the switch state of the RF switch changes
Device increases the frequency of the clock signal within the set duration, to increase the voltage amplitude of the bias voltage.
2. biasing circuit according to claim 1, which is characterized in that
The biasing circuit further include: the input of the logic control signal of the switch state for RF switch described in input control
End；
The control circuit is arranged to when detecting that the logic state of the logic control signal changes, and determines detection
Switch state to the RF switch changes.
3. biasing circuit according to claim 2, which is characterized in that
The control circuit is arranged to output regulation signal to the oscillator；The oscillator be arranged to output frequency with
The corresponding clock signal of the level state of the adjustment signal, for the charge pump output voltage amplitude and the adjustment signal
The corresponding bias voltage of level state；
The control circuit is arranged to set when detecting that the logic state of the logic control signal changes described
The level state of the overturning adjustment signal in timing is long.
4. biasing circuit according to claim 3, which is characterized in that the level state after the adjustment signal is reversed is
High level；The control circuit includes the first delay circuit and the first XOR gate；
First delay circuit is arranged to carry out postponing the processing of the setting duration to the logic control signal, obtains
The logic control signal of delay；
First XOR gate is arranged to carry out exclusive or to the logic control signal of the logic control signal and the delay
Logical process obtains the adjustment signal.
5. biasing circuit according to claim 3, which is characterized in that
The control circuit includes the second delay circuit, the second XOR gate and timer,
Second delay circuit is arranged to carry out postponing the processing of another setting duration to the logic control signal, obtains
The logic control signal of another delay；Another setting duration is less than the setting duration；
Second XOR gate is arranged to carry out the logic control signal of the logic control signal and another delay
XOR logic processing obtains timing signal and exports to the timer；
The timer is arranged to export the adjustment signal, and when receiving the rising edge of the timing signal, in institute
State the level state of the overturning adjustment signal in setting duration.
6. biasing circuit according to claim 5, which is characterized in that the setting duration is equal to N number of clock signal
Period, wherein N is positive integer；
The timer includes phase inverter, Fractional-N frequency circuit and the first d type flip flop；
The Fractional-N frequency circuit is arranged to carry out Fractional-N frequency processing to the clock signal, obtains Fractional-N frequency clock signal, and input
To the clock end of first d type flip flop；
The phase inverter is arranged to export after carrying out the timing signal reverse phase processing to the clearing of first d type flip flop
End；
The first d type flip flop input terminal is connect with the reversed-phase output of itself, and the output end of first d type flip flop is set
To export the adjustment signal.
7. biasing circuit according to claim 6, which is characterized in that the M power that N is 2, wherein M is positive integer；
The Fractional-N frequency circuit includes M cascade second d type flip flops；
The input terminal of each second d type flip flop is connect with the reversed-phase output of itself, the output end of the second d type flip flop of previous stage
It is connected with the clock end of corresponding the second d type flip flop of next stage, the clock end of first the second d type flip flop is arranged to described in input
Clock signal, the output end of the second d type flip flop of m-th are connect with the clock end of first d type flip flop.
8. biasing circuit according to claim 1, which is characterized in that the biasing circuit can also include that clock handles mould
Block, the clock processing module are arranged to carry out the clock signal frequency dividing or process of frequency multiplication, and will treated clock
Signal is transmitted to the charge pump, and for the charge pump, treated that clock signal exports the bias voltage according to described.
9. biasing circuit according to any one of claim 1 to 8, which is characterized in that the oscillator is relaxation oscillation
Device.
10. a kind of frequency communication devices, which is characterized in that including RF switch and according to claim 1 to any one of 9 institutes
The biasing circuit stated, the biasing circuit is arranged to provide bias voltage to the RF switch, for the RF switch work
Make.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910411459.3A CN110113039A (en) | 2019-05-16 | 2019-05-16 | A kind of biasing circuit and frequency communication devices for RF switch |
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| CN201910411459.3A CN110113039A (en) | 2019-05-16 | 2019-05-16 | A kind of biasing circuit and frequency communication devices for RF switch |
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| CN115378459A (en) * | 2022-09-01 | 2022-11-22 | 江苏卓胜微电子股份有限公司 | Radio frequency switch control link, system and control method thereof |
| WO2022247843A1 (en) * | 2021-05-27 | 2022-12-01 | 广东工业大学 | Low-power-consumption negative pressure generator for radio frequency switch |
| WO2023065583A1 (en) * | 2021-10-19 | 2023-04-27 | 深圳飞骧科技股份有限公司 | Radio frequency switch bias voltage feedback control circuit |
| CN117294286A (en) * | 2023-11-27 | 2023-12-26 | 深圳新声半导体有限公司 | Radio frequency switch control circuit |
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2019
- 2019-05-16 CN CN201910411459.3A patent/CN110113039A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022247843A1 (en) * | 2021-05-27 | 2022-12-01 | 广东工业大学 | Low-power-consumption negative pressure generator for radio frequency switch |
| US11711075B2 (en) | 2021-05-27 | 2023-07-25 | Guangdong University Of Technology | Low-power consumption negative voltage generator for radio frequency switches |
| WO2023065583A1 (en) * | 2021-10-19 | 2023-04-27 | 深圳飞骧科技股份有限公司 | Radio frequency switch bias voltage feedback control circuit |
| CN115378459A (en) * | 2022-09-01 | 2022-11-22 | 江苏卓胜微电子股份有限公司 | Radio frequency switch control link, system and control method thereof |
| WO2024046104A1 (en) * | 2022-09-01 | 2024-03-07 | 江苏卓胜微电子股份有限公司 | Radio-frequency switch control link and system and control method for radio-frequency switch control link |
| CN117294286A (en) * | 2023-11-27 | 2023-12-26 | 深圳新声半导体有限公司 | Radio frequency switch control circuit |
| CN117294286B (en) * | 2023-11-27 | 2024-04-02 | 深圳新声半导体有限公司 | Radio frequency switch control circuit |
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