WO2023065583A1 - Circuit de commande de rétroaction de tension de polarisation de commutateur radiofréquence - Google Patents

Circuit de commande de rétroaction de tension de polarisation de commutateur radiofréquence Download PDF

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Publication number
WO2023065583A1
WO2023065583A1 PCT/CN2022/078368 CN2022078368W WO2023065583A1 WO 2023065583 A1 WO2023065583 A1 WO 2023065583A1 CN 2022078368 W CN2022078368 W CN 2022078368W WO 2023065583 A1 WO2023065583 A1 WO 2023065583A1
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frequency
level
terminal
input
voltage
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PCT/CN2022/078368
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English (en)
Chinese (zh)
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苏俊华
郭嘉帅
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深圳飞骧科技股份有限公司
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Publication of WO2023065583A1 publication Critical patent/WO2023065583A1/fr

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated

Definitions

  • the utility model relates to the technical field of radio frequency switches, in particular to a bias voltage feedback control circuit of a radio frequency switch.
  • radio frequency switches are widely used in wireless communication equipment, and are used in occasions where radio frequency signals need to be turned on or off, such as transmitting and receiving switches, channel selection switches, tuning switches, and reversing switches.
  • silicon substrate-buried oxide layer-outer edge silicon (SOI) technology is usually used in wireless communication equipment, and metal oxide field effect transistor (MOS transistor) devices are grown on outer edge silicon.
  • SOI silicon substrate-buried oxide layer-outer edge silicon
  • MOS transistor metal oxide field effect transistor
  • make a radio frequency switch circuit Generally, in order to improve the turn-on and cut-off characteristics of MOS tubes, it is necessary to use a level higher than the power supply voltage or lower than the reference ground as the bias level of the RF switch.
  • a charge pump is generally used to generate a voltage higher than the power supply voltage or lower than the reference ground. The level of the reference ground, and the load capacity of the charge pump is linearly positively related to the clock frequency.
  • the RF switch bias voltage circuit of the related art comprises a timer and a logic inversion detection circuit connected in sequence, a frequency adjustable oscillator and a charge pump; the logic inversion detection circuit detects and generates a frequency control signal according to an externally input RF switch control signal, to Flip to adjust the frequency form of the oscillator; the frequency adjustable oscillator outputs the clock signal to the charge pump according to the frequency control signal; the charge pump generates a certain multiple of the input reference level according to the clock signal to generate the bias level required by the RF switch; timing The registers are respectively connected to the output terminal of the frequency adjustable oscillator and the clock input terminal detected by the logic flip detection circuit, and are used to extend the duration of the fast clock signal.
  • the state of the load connected to the RF switch bias voltage circuit in the related art changes, for example, when the path of the RF switch is switched, that is, the capacitive load of the bias voltage circuit will undergo a large mutation, which is limited by the bias voltage.
  • the response speed and driving capability of the charge pump in the circuit lead to the loss of charge stored in the voltage stabilizing capacitor at the output end of the charge pump, causing the voltage amplitude of the bias level of the bias voltage circuit to drop instantaneously. If the voltage amplitude of the bias level does not return to normal within the specified switching time, it will affect the performance of the RF switch. In this case, the RF switch bias voltage circuit in the related art cannot meet the switching time requirement.
  • the unavoidable nonlinearity of the RF switch determines that the AC-DC conversion (AC-DC) phenomenon will occur when the RF signal passes through the device, so that the load of the charge pump is no longer just a capacitor, but a combination of capacitor and DC current. And, while the DC current will greatly weaken the magnitude of the bias level, at this time the RF switch conduction and cut-off performance will deteriorate sharply, as the RF signal power of the RF switch contacts increases, the AC-DC conversion phenomenon will become more Obviously, the output level of the charge pump cannot maintain the state of the radio frequency switch in the end, resulting in the breakdown and burning of the radio frequency switch.
  • AC-DC AC-DC conversion
  • the utility model proposes a radio frequency switch bias voltage feedback control circuit with good output switch bias level stability.
  • the embodiment of the utility model provides a radio frequency switch bias voltage feedback control circuit, which includes a frequency adjustable oscillator and a charge pump connected in sequence; the frequency adjustable oscillator is used to generate a clock signal and output; the charge pump is used to generate N times the switch bias level and output the externally input reference level according to the clock signal; wherein, N>1; the radio frequency switch bias voltage feedback control circuit It also includes a level detection circuit and a decoding circuit connected in sequence; the level detection circuit is also connected to the charge pump, and the level detection circuit is used to compare the received switch bias level with the preset The reference level is compared and the bias level status indication signal is generated and output; the decoding circuit is also connected to the frequency adjustable oscillator, and the decoding circuit is used for sequentially setting the frequency and according to the received Decode the bias level state indication signal to generate and output a frequency control signal; the frequency adjustable oscillator is also used to generate the frequency corresponding to the frequency control signal according to the frequency control signal to be received the clock signal.
  • the level detection circuit detects and receives the switch bias level output by the charge pump in real time;
  • the level detection circuit includes a comparator, a voltage-dividing impedance Z1, a voltage-dividing impedance ZS, and a voltage-dividing impedance Z2, wherein, the voltage dividing impedance ZS is a variable impedance; the first end of the voltage dividing impedance Z1 is connected to the power supply voltage; the second end of the voltage dividing impedance Z1 is respectively connected to the negative input of the comparator terminal, the first end of the voltage dividing impedance ZS; the positive input terminal of the comparator is used as the reference level input terminal of the level detection circuit; the output terminal of the comparator is used as the reference level input terminal of the level detection circuit
  • the bias level state indicates the signal output terminal, and the output terminal of the comparator is connected to the adjustment terminal of the voltage dividing impedance ZS; the second end of the voltage dividing impedance ZS is connected to the first terminal of the voltage dividing impedance Z
  • the bias level state indication signal is a set of digital signals or analog signals.
  • the reference level is a fixed voltage input by an external circuit or a preset threshold voltage internally generated by the level detection circuit.
  • the decoding circuit performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.
  • the decoding circuit is configured to perform the frequency setting according to the received bias level state indication signal
  • the decoding circuit includes an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, three input AND gate ANDB and 8421 decoder; the positive end of the inverter INV1 is used as the input end of the decoding circuit, and the positive end of the inverter INV1 is respectively connected to the gate of the transistor PM1, the The first input end of the three-input AND gate ANDB and the first input end of the 8421 decoder; the negative end of the inverter INV1 is connected to the first end of the resistor R1; the first end of the resistor R2 The two terminals are respectively connected to the positive terminal of the capacitor C1, the input terminal of the Schmitt trigger ST1 and the drain of the transistor PM1; the negative terminal of the capacitor C1 is connected to ground; the source of the transistor PM1 The pole is connected to the power supply
  • the frequency control signal is a set of digital signals or analog signals.
  • the decoding circuit includes a delay processing module, and the delay processing module is used for delay processing the external input signal of the decoding circuit or the intermediate signal inside the decoding circuit.
  • the frequency control signal can control the frequency of the clock signal in real time.
  • the charge pump includes a voltage stabilizing capacitor, the positive end of the voltage stabilizing capacitor is connected to the output end of the charge pump that outputs the switch bias level, and the negative end of the voltage stabilizing capacitor is connected to ground .
  • the radio frequency switch bias voltage feedback control circuit of the utility model is provided with a level detection circuit, a decoding circuit and the frequency adjustable oscillator, and the level detection circuit outputs the output voltage of the charge pump.
  • the switch bias level is compared with a preset reference level to generate and output a bias level state indication signal; the bias level state indication signal is decoded by a decoding circuit to generate and output a frequency control signal, and then generate the clock signal corresponding to the frequency of the frequency control signal from the frequency control signal through the frequency adjustable oscillator, so that the charge pump generates and inputs the corresponding clock signal according to the clock signal
  • the charge pump periodically transfers positive charges to accumulate above the reference level to generate a level higher than the reference level, and if negative charges are transferred, it generates a level higher than the reference level The level is lower, so the switch bias level generated by the charge pump is the bias level required by the radio frequency switch.
  • the circuit simultaneously makes the frequency adjustable oscillator, the charge pump, the level detection circuit and the decoding circuit
  • Fig. 1 is the circuit structural diagram of the RF switch bias voltage feedback control circuit of related art
  • FIG. 2 is a circuit structure diagram of a radio frequency switch bias voltage feedback control circuit in Embodiment 1 of the present invention
  • FIG. 3 is a schematic circuit diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 2 of the present invention.
  • the utility model provides a radio frequency switch bias voltage feedback control circuit 100 .
  • FIG. 2 is a circuit structure diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 1 of the present invention.
  • the RF switch bias voltage feedback control circuit 100 includes a frequency adjustable oscillator 1 , a charge pump 2 , a level detection circuit 3 and a decoding circuit 4 connected in sequence. Wherein, the decoding circuit 1 is also connected to the frequency adjustable oscillator 4 .
  • the frequency adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 together form a circuit closed loop.
  • the frequency adjustable oscillator 1 is used to generate and output a clock signal.
  • the charge pump 2 is used for generating and outputting a switch bias level of N multiples from an externally input reference level according to the clock signal. Among them, N>1.
  • the voltage value of the switch bias level is positively related to the frequency of the clock signal generated by the adjustable frequency oscillator 1 .
  • the charge pump 2 includes a voltage stabilizing capacitor.
  • the positive end of the voltage stabilizing capacitor is connected to the output end of the charge pump 2 for outputting the switch bias level.
  • the negative end of the voltage stabilizing capacitor is connected to ground.
  • the charge pump 2 transfers charges from the external input reference level to the output voltage stabilizing capacitor at the frequency of the current clock signal, so as to provide the switch bias level required by the radio frequency switch.
  • the level detection circuit 3 is used for comparing the received switch bias level with a preset reference level and generating and outputting a bias level state indication signal.
  • the reference level is a fixed voltage input by an external circuit.
  • the preset threshold voltage generated inside the level detection circuit 3 can be generated by resistive voltage division, and the level detection circuit 3 can generate the Bias level status indication signal.
  • the bias level state indication signal is a set of digital signals.
  • the bias level state indicating signal may also be an analog signal.
  • the level detection circuit 3 detects and receives the switch bias level output by the charge pump 2 in real time, and this setting can make the switch bias level output by the charge pump 2 last Adjust and keep the voltage value stable.
  • the decoding circuit 4 is used to sequentially perform frequency setting and decode according to the received bias level status indication signal to generate and output a frequency control signal.
  • the frequency adjustable oscillator 1 is also used for generating the clock signal with a frequency corresponding to the frequency control signal according to the frequency control signal to be received.
  • the decoding circuit 4 is configured to perform the frequency setting according to the received bias level state indication signal. Of course, it is not limited thereto, and the decoding circuit 4 also performs the frequency setting according to an externally input frequency control signal, or performs the frequency setting according to a preset condition.
  • the frequency control signal is a set of digital signals.
  • the frequency control signal is an analog signal in another embodiment.
  • the decoding circuit 4 includes a delay processing module (not shown in the figure), and the delay processing module is used to convert the external input signal of the decoding circuit 4 or the intermediate signal inside the decoding circuit 4 The signal is delayed.
  • the delay processing module can reduce the output glitch of the charge pump 2 caused by the excessive frequency change of the clock signal of the charge pump 2, and at the same time, it will not make an error when the level detection circuit 3 misjudges
  • the frequency tunable oscillator 1 is used to generate the frequency of the clock signal.
  • the frequency control signal can control the frequency of the clock signal in real time.
  • This setting can make the switch bias level output by the charge pump 2 continuously adjustable and keep the voltage value stable.
  • the RF switch bias voltage feedback control circuit 100 periodically transports positive charges above the reference level through the charge pump 2 to generate a level higher than the reference level, such as transporting negative charges , then a level lower than the reference level is generated, so that the switch bias level generated by the charge pump 2 is the bias level required by the radio frequency switch.
  • the level detection circuit 3 continuously detects the switch bias level output by the charge pump 2, and the level detection circuit 3 compares the switch bias level with the reference level Comparing and generating the bias level state indication signal for continuously adjusting the decoding circuit 4 . Therefore, the frequency adjustable oscillator 1 , the charge pump 2 , the level detection circuit 3 and the decoding circuit 4 together form a feedback system.
  • the level detection circuit 3 detects the state change, and outputs the bias level
  • the status indication signal indicates that the frequency of the clock signal of the adjustable frequency oscillator 1 needs to be adjusted at this time to improve the driving capability of the charge pump 2, so as to quickly return to the normal RF switch working state.
  • the level detection circuit 3 detects a state change, and indicates that the frequency of the clock signal of the frequency adjustable oscillator 1 needs to be adjusted at this time by outputting the bias level state indication signal to enable the charge pump 2 to drive Increased ability to maintain adequate switch bias levels until RF power is reduced. Therefore, the stability of the switch bias level of the output of the RF switch bias voltage feedback control circuit 100 is good.
  • the frequency adjustable oscillator 1, the charge pump 2, the level detection circuit 3 and the decoding circuit 4 used in the present invention are all commonly used circuits in the field, and the specific circuit results and performance indicators are determined according to actual applications. The adjustment is not described in detail here.
  • Embodiment 2 of the utility model provides a radio frequency switch bias voltage feedback control circuit with a specific circuit structure.
  • FIG. 3 is a schematic circuit diagram of a radio frequency switch bias voltage feedback control circuit according to Embodiment 2 of the present invention.
  • the level detection circuit 3 includes a comparator COMP, a voltage dividing impedance Z1, a voltage dividing impedance ZS, and a voltage dividing impedance Z2, wherein the voltage dividing impedance ZS is a variable impedance.
  • the concrete circuit structure of described level detection circuit 3 is:
  • a first end of the voltage dividing impedance Z1 is connected to a power supply voltage.
  • the second terminal of the voltage dividing impedance Z1 is respectively connected to the negative input terminal of the comparator COMP and the first terminal of the voltage dividing impedance ZS.
  • the positive input terminal of the comparator COMP is used as the reference level input terminal of the level detection circuit 3 .
  • the output terminal of the comparator COMP is used as the output terminal of the bias level state indication signal of the level detection circuit 3 , and the output terminal of the comparator COMP is connected to the adjusting terminal of the voltage dividing impedance ZS.
  • the second end of the voltage dividing impedance ZS is connected to the second end of the voltage dividing impedance Z2.
  • the first end of the voltage dividing impedance Z2 is used as the input end of the level detection circuit 3 .
  • connection point between the negative input terminal of the comparator COMP and the voltage dividing impedance Z1 and the voltage dividing impedance ZS is VS.
  • the voltage dividing impedance ZS When the bias level state indicating signal is high, the voltage dividing impedance ZS is close to 0 ohm, and when the bias level state indicating signal is low, the voltage dividing impedance ZS is much larger than 0 ohm.
  • the potential of VS at any moment is:
  • the bias level state indication signal When the reference level VREF does not reach the required level, the bias level state indication signal is low, the voltage division impedance ZS is much greater than 0 ohms, and the VS voltage value is greater than the reference level VREF.
  • the voltage amplitude of the reference level VNEG increases, the VS voltage value approaches the reference level VREF, until the VS voltage value is slightly greater than the reference level VREF, at this time the bias level status indication signal is turned high, and at this time:
  • the above process can complete the hysteresis process, so as to avoid output oscillation caused by noise and interference, and at the same time, the output of the level detection circuit 3 will not be completely locked, so that it maintains the detection function.
  • the decoding circuit 4 includes an inverter INV1, an inverter INV2, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a transistor PM1, a transistor NM1, a Schmitt trigger ST1, a Schmitt trigger ST2, three Input AND gate ANDB and 8421 decoder.
  • the circuit structure of described decoding circuit 4 is:
  • the positive terminal of the inverter INV1 is used as the input terminal of the decoding circuit, and the positive terminal of the inverter INV1 is connected to the gate of the transistor PM1 and the first gate of the three-input AND gate ANDB respectively. input and the first input of the 8421 decoder.
  • the negative end of the inverter INV1 is connected to the first end of the resistor R1.
  • the second terminal of the resistor R2 is respectively connected to the positive terminal of the capacitor C1 , the input terminal of the Schmitt trigger ST1 and the drain of the transistor PM1 .
  • the negative terminal of the capacitor C1 is connected to ground.
  • the source of the transistor PM1 is connected to a power supply voltage.
  • the output terminal of the Schmitt trigger ST1 is respectively connected to the positive terminal of the inverter INV2 , the gate of the transistor NM1 and the third input terminal of the three-input AND gate ANDB.
  • the negative end of the inverter INV2 is connected to the first end of the resistor R2.
  • the second terminal of the resistor R2 is respectively connected to the negative terminal of the capacitor C2, the input terminal of the Schmitt trigger ST2 and the drain of the transistor NM1.
  • the positive end of the capacitor C2 is connected to the power supply voltage; the source of the transistor NM1 is connected to the ground.
  • the output end of the Schmitt trigger ST2 is connected to the second input end of the three-input AND gate ANDB.
  • the output end of the three-input AND gate ANDB is connected to the second input end of the 8421 decoder.
  • the third input terminal of the 8421 decoder is used as the frequency setting input terminal of the decoding circuit 4;
  • the output terminal of the 8421 decoder is used as the output terminal of the decoding circuit 4 .
  • the inverter INV1, the resistor R1, the capacitor C1, the transistor PM1 and the Schmitt trigger ST1 in the decoding circuit 4 form a first-stage single-edge delayer
  • the decoding circuit 4 Inverter INV2, resistor R2, capacitor C2, transistor NM1 and Schmitt trigger ST2 form the second-stage single-edge delayer.
  • the three-input AND gate ANDB and 8421 decoder realize the decoding function. Among them, the frequency setting input terminal VCH is used to control the frequency setting of the 8421 decoder.
  • the function of the first-stage single-edge delayer is to output a high level immediately when the input signal is turned from a high level to a low level, and to delay the generation of a low level when the input signal is turned from a low level to a high level, and the delay time is Determined by the product of resistor R1 and capacitor C1.
  • the function of the second-stage single-edge delayer is to output low level immediately when the input signal is turned from low level to high level, and to delay the generation of high level when the input signal is turned from high level to low level. The delay time is Determined by the product of resistor R2 and capacitor C2.
  • the frequency adjustable oscillator 1 is a ring oscillator, which is composed of the inverter INV3 of the frequency adjustable oscillator 1 and an even-order inverter chain, and the frequency is determined by the frequency adjustable
  • the controlled current source CS of oscillator 1 and the load capacitance C3 determine that when the controlled current source CS is set to a small current, the clock signal period is very long; when the controlled current source CS is set to a medium current, the clock signal period Short; when the controlled current source CS is set to a large current, the clock signal period is extremely short.
  • the charge pump 2 is composed of a non-overlapping clock generator and a mutually biased symmetric charge pump, and the two phases of the clock can be fully used to charge the voltage stabilizing capacitor C4 of the charge pump 2, and the switch
  • the bias level VNEG is the output terminal of the charge pump 2 .
  • the decoding circuit 4 and the frequency adjustable oscillator 1 jointly form a variable frequency oscillator with a delay function. specific,
  • the frequency adjustable oscillator 1 When the bias level state indication signal is high, the frequency adjustable oscillator 1 outputs a clock signal with a very low frequency, so as to reduce the power consumption of the whole system.
  • the frequency adjustable oscillator 1 When the bias level state indication signal changes from high to low, the frequency adjustable oscillator 1 immediately outputs a clock signal with a high frequency to strengthen the driving of the charge pump 2 .
  • the frequency adjustable oscillator 1 When the bias level state indication signal changes from low to high, the frequency adjustable oscillator 1 will first output a medium frequency clock signal for a period of time, so that the drive of the charge pump 2 is reduced, and then the frequency is adjustable The oscillator 1 outputs a clock signal with a very low frequency, and the charge pump 2 returns to normal operation.
  • the level detection circuit 3 will continuously output a low level so that the frequency adjustable oscillator 1 always maintains
  • the high-frequency clock signal maintains the level of the switch bias level VNEG by consuming more power, thereby ensuring the working state of the radio frequency switch.
  • the radio frequency switch bias voltage feedback control circuit of the utility model is provided with a level detection circuit, a decoding circuit and the frequency adjustable oscillator, and the level detection circuit outputs the output voltage of the charge pump.
  • the switch bias level is compared with a preset reference level to generate and output a bias level state indication signal; the bias level state indication signal is decoded by a decoding circuit to generate and output a frequency control signal, and then generate the clock signal corresponding to the frequency of the frequency control signal from the frequency control signal through the frequency adjustable oscillator, so that the charge pump generates and inputs the corresponding clock signal according to the clock signal
  • the charge pump periodically transfers positive charges to accumulate above the reference level to generate a level higher than the reference level, and if negative charges are transferred, it generates a level higher than the reference level The level is lower, so the switch bias level generated by the charge pump is the bias level required by the radio frequency switch.
  • the circuit simultaneously makes the frequency adjustable oscillator, the charge pump, the level detection circuit and the decoding circuit

Abstract

La présente divulgation concerne un circuit de commande de rétroaction de tension de polarisation de commutateur radiofréquence (100), comprenant un oscillateur réglable en fréquence (1), une pompe de charge (2), un circuit de détection de niveau (3) et un circuit de décodage (4) connectés en séquence. Le circuit de décodage (4) est en outre connecté à l'oscillateur réglable en fréquence (1) ; l'oscillateur réglable en fréquence (1) est utilisé pour générer, selon un signal de commande de fréquence reçu, un signal d'horloge dont la fréquence correspond au signal de commande de fréquence et pour le délivrer ; la pompe de charge (2) est utilisée pour générer, en fonction du signal d'horloge, N multiples d'un niveau de polarisation de commutateur à partir d'un niveau de référence entré de manière externe et pour les délivrer, N > 1 ; le circuit de détection de niveau (3) est utilisé pour comparer le niveau de polarisation de commutateur reçu à un niveau de référence prédéfini et pour générer et délivrer en sortie un signal d'indication d'état de niveau de polarisation ; et le circuit de décodage (4) est utilisé pour régler séquentiellement une fréquence, effectuer un décodage selon le signal d'indication d'état de niveau de polarisation reçu, et générer et émettre un signal de commande de fréquence. Le niveau de polarisation de commutateur émis par le circuit de commande de rétroaction de tension de polarisation de commutateur radiofréquence (100) a une bonne stabilité.
PCT/CN2022/078368 2021-10-19 2022-02-28 Circuit de commande de rétroaction de tension de polarisation de commutateur radiofréquence WO2023065583A1 (fr)

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CN202122519735.3U CN215932482U (zh) 2021-10-19 2021-10-19 射频开关偏置电压反馈控制电路
CN202122519735.3 2021-10-19

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CN209692726U (zh) * 2019-05-16 2019-11-26 上海猎芯半导体科技有限公司 一种用于射频开关的偏置电路、及射频通信装置
CN111030661A (zh) * 2019-05-16 2020-04-17 上海猎芯半导体科技有限公司 一种偏置电路、及射频通信装置
CN112825479A (zh) * 2019-11-20 2021-05-21 合肥格易集成电路有限公司 一种延迟电路及芯片
CN213426126U (zh) * 2020-11-30 2021-06-11 开元通信技术（厦门）有限公司 一种射频开关负压偏置电路及射频开关系统

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