CN103595378A - Power-on reset circuit with low power consumption and high performance - Google Patents
Power-on reset circuit with low power consumption and high performance Download PDFInfo
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- CN103595378A CN103595378A CN201310564390.0A CN201310564390A CN103595378A CN 103595378 A CN103595378 A CN 103595378A CN 201310564390 A CN201310564390 A CN 201310564390A CN 103595378 A CN103595378 A CN 103595378A
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Abstract
The invention discloses a novel power-on reset circuit which mainly comprises a counter reset signal generating circuit, an annular oscillating circuit, a counter circuit, a combination logic circuit and a reset terminal circuit. The counter reset signal generating circuit is in electric connection with the counter circuit, the counter circuit is respectively in electric connection with the annular oscillating circuit and the combination logic circuit, the annular oscillating circuit is in electric connection with the combination logic circuit, and the annular oscillating circuit and the combination logic circuit are respectively in electric connection with the reset terminal circuit. According to the novel power-on reset circuit, the power-on reset function is achieved by adopting a digital circuit structure, level high and low information of a CTRL end is displayed through counting of a counter, and work of an oscillator is controlled through the level magnitude of the CTRL end of the signal output end of the oscillator. Two buffers I24 and I26 are finally added, a pulse signal of the CTRL is received, a stable reset signal is output, and a reset function is achieved. Layout area is saved while the reset function of high performance and low power consumption is achieved.
Description
Technical field
The present invention relates to a kind of electrify restoration circuit, relate in particular to the high performance electrify restoration circuit of a kind of super low-power consumption for hand-held electronic very product.
Background technology
Electrify restoration circuit exists in the circuit of electronic product, and its performance generally affects the performance of integrated circuit directly or indirectly.And the electrify restoration circuit of extensive use in the market generally all adopts simulation circuit structure, be mainly to discharge and recharge by RC the broadband of deciding reset pulse; When using and powering on slowly, conventionally adopt the form of electric resistance partial pressure to decide the voltage of electrification reset.Its circuit structure as shown in Figure 1, mainly comprises input voltage Vdd, earth terminal GND, reset terminal RESET, circuit R0, resistance R 1, resistance R 2, resistance R 3, capacitor C 0, counter I1, counter I12, oscillator I7, transistor NM0 and transistor NM1; Input voltage Vdd is electrically connected to one end of resistance R 0, R1, R3 respectively; The other end of resistance R 0 is electrically connected to the positive pole of capacitor C 0, the drain D of 1 port of counter I1, transistor NM0 respectively; 2 ports of counter I1 are electrically connected to 2 ports of oscillator I7; The other end of resistance R 1 is electrically connected to one end of resistance R 2, the grid G of transistor NM1 respectively; Resistance R 3 is electrically connected to 1 port of oscillator I7, the grid G of the drain D of transistor NM1, transistor NM0 respectively; 3 ports of oscillator I7 are electrically connected to 1 port of counter I12; 2 ports of counter I12 connect reset terminal RESET; The source S of the other end of the source S of the negative pole of capacitor C O, transistor NM0, resistance R 2, transistor NM1 is electrically connected to earth terminal GND respectively; Although foregoing circuit structure can realize electrification reset function, there is following defect: the first, this circuit is if while realizing wider electrification reset pulse, RC get will be enough large, need to take enough chip areas, cause chip area to increase; The second, in circuit, there are a plurality of current branch, size and the resistance of quiescent current are inversely proportional to, and conventionally will increase the resistance of resistance in the situation that meeting power consumption demand, certainly will cause like this increase of the power consumption of integrated circuit; Due to the increase of resistance, also increased to a certain extent the demand to chip area simultaneously.
For solving electrify restoration circuit, adopt simulation circuit structure cannot meet low-power consumption and little these two requirements of domain area occupied simultaneously; In order to solve this this problem, the present invention adopts the electrify restoration circuit of numeric structure, realizes the reset of Low Power High Performance and controls.
Summary of the invention
The object of the present invention is to provide a kind of simple in structure, domain area occupied is little, can effectively realize the reset circuit that low power consumption high-precision is controlled.
The present invention includes counter reset signal and produce circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; Described counter signals produces circuit and is electrically connected to counter circuit; Described counter circuit is electrically connected to annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected to combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected to reset terminal circuit respectively.
Described counter reset signal produces circuit and comprises transistor M0, transistor M1, transistor M2, transistor M4, capacitor C 0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected to the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected to the positive pole of capacitor C 0, the grid G of the source S of transistor M2, transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described capacitor C 0; The drain D ground connection of described transistor M1; The drain D of described transistor M1 is electrically connected to the drain D of transistor M3; The drain D of described transistor M3 is electrically connected to the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET.
Described counter circuit is comprised of 6 counters, i.e. counter I0, I41, I43, I42, I47, I46; On described counter I0, I41, I43, I42, I47, I46, be equipped with five connectivity ports, these five connectivity ports, are respectively RESET port, D port, QB port, CLK port, Q port; The RESET end of described counter I0, I41, I43, I42, I47, I46 is electrically connected to the reset exit RESET of counter reset signal generation circuit respectively; The D port of described counter I0, I41, I43, I42, I47, I46 is all electrically connected to the QB port of himself; The Q port of described counter I0 is electrically connected to the CLK port of counter I41, and at terminals, is provided with signal and draws interface CLK2; The Q port of described counter I41 is electrically connected to the CLK port of counter I43, and at terminals, is provided with signal and draws interface CLK4; The Q port of described counter I43 is electrically connected to the CLK port of counter I42, and at terminals, is provided with signal and draws interface CLK8; The Q port of described counter I42 is electrically connected to the CLK port of counter I47, and at terminals, is provided with signal and draws interface CLK16; The Q port of described counter I47 is electrically connected to the CLK port of counter I46, and at terminals, is provided with signal and draws interface CLK32; The Q end of described counter I46 is provided with signal and draws interface CLK64.
Described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; 2 ports of described oscillator I29 are electrically connected to 1 port of inverter I23; 1 port of described oscillator I29 is electrically connected to the CLK port of counter I0,2 ports of inverter I22 respectively; 1 port of described inverter I22 is electrically connected to 2 ports of inverter I27; State 1 port of inverter I27 and 2 ports of inverter I21 are electrically connected to; State 1 port of inverter I21 and 2 ports of inverter I23 are electrically connected to.
Described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; 2 ports and the signal of described oscillator I18 drawn interface CLK2 and is electrically connected to; 3 ports and the signal of described oscillator I18 drawn interface CLK4 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK8 and is electrically connected to; 1 port of described oscillator I18 is electrically connected to 2 ports of inverter I17; 1 port of described inverter I17 is electrically connected to 2 ports of oscillator I19; 1 port of described oscillator I19 is electrically connected to 3 ports of oscillator I29, and is provided with signal exit CTRL; 2 ports of described oscillator I19 are electrically connected to 1 port of inverter I15; 2 ports of described inverter I15 are electrically connected to 1 port of oscillator I16; 2 ports and the signal of described oscillator I16 drawn interface CLK16 and is electrically connected to; 3 ports and the signal of described oscillator I16 drawn interface CLK32 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK64 and is electrically connected to.
Described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected to 1 port of buffer I24; 2 ports of described buffer I24 are electrically connected to 1 port of buffer I26; 2 ports of described buffer I26 are electrically connected to signal exit CTRL.
Described transistor M0, transistor M1, transistor M2 are PMOS pipe; Described transistor M4 is NMOS pipe.
Described counter is that high level triggers, and the maximum count value of counter is 64.
The number of the inverter in described ring oscillator circuit is N; This circuit selects 6.
The present invention adopts digital circuit structure to realize electrification reset function; By rolling counters forward, show CTRL end level height information, the level of the CTRL end of the signal output part by oscillator is just controlled the work of oscillator; And in the end increased by two buffer I24, I26, receive the pulse signal of CTRL, and the reset signal of stable output, realize reset function; When meet saving chip area, realized the reset function of high-performance, low-power consumption.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of prior art;
Fig. 2 is schematic block diagram of the present invention;
Fig. 3 is count resets signal generating circuit schematic diagram;
Fig. 4 is ring oscillator circuit schematic diagram;
Fig. 5 is counter circuit schematic diagram;
Fig. 6 is Combinational Logic Control circuit theory diagrams;
Fig. 7 is the integrally-built circuit theory diagrams of the present invention.
Embodiment
The invention will be further described for the embodiment providing below in conjunction with accompanying drawing:
As described in Figure 2, the present invention includes counter reset signal and produce circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; Described counter signals produces circuit and is electrically connected to counter circuit; Described counter circuit is electrically connected to annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected to combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected to reset terminal circuit respectively.
As described in Figure 3, described counter reset signal generation circuit comprises transistor M0, transistor M1, transistor M2, transistor M4, capacitor C 0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected to the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected to the positive pole of capacitor C 0, the grid G of the source S of transistor M2, transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described capacitor C 0; The drain D ground connection of described transistor M1; The drain D of described transistor M1 is electrically connected to the drain D of transistor M3; The drain D of described transistor M3 is electrically connected to the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET;
The effect of this part circuit is when power supply electrifying, to counter circuit, provides an of short duration reset pulse, and counter is resetted, and the initial count value of counter is 0;
In this circuit, described transistor M0, transistor M1, transistor M2 all select PMOS pipe, and the cut-in voltage of transistor M0 is greater than transistor M1, and the cut-in voltage of transistor M1 equates with the cut-in voltage of transistor M2; Described transistor M4 selects NMOS pipe, and selects the width of pipe of crystal than large the falling than managing of length, contributes to like this electric current that flows through when pipe conducting less;
The voltage Vdd that switches on power, makes power on circuitry; When voltage does not reach the cut-in voltage of transistor M1, M2, because the cut-in voltage of M0 is also greater than M1, so M0 and M1 end, the current branch at their places does not have electric current, M2 is because grid end directly accesses power supply, for the ceiling voltage of circuit, under normal condition, its source and grid terminal voltage are poor may arrive cut-in voltage value never, so it also ends.Transistor M0, M1, M2, M3 that now whole counter reset signal produces in circuit all, in by state, do not have current loss in circuit, output voltage is also extremely low, supply voltage Vdd continues to rise, when supply voltage Vdd is greater than transistor M1, the cut-in voltage of M2, but while being only less than the cut-in voltage of transistor M0, now transistor M0 cut-off, in the current branch at its place, there is no electric current, so A point in circuit, namely the upper end of capacitor C 0 is not because there is no charging current, so voltage is 0V, and now the voltage difference of the upper source electrode of transistor M1 and grid G end has been more than or equal to the cut-in voltage of transistor M0, transistor M1 starts conducting work, start to have electric current to pass through the drain D end of transistor M1, the voltage that Y in circuit is ordered starts to rise, because NMOS M3 is below down than pipe, equivalent resistance is very large, so charging current is obviously greater than discharging current, make Y point voltage constantly raise and progressively approach supply voltage Vdd, after this, supply voltage Vdd continues to rise, until the magnitude of voltage that Y is ordered reaches the cut-in voltage value of transistor M0, and now transistor M0 conducting, electric current, through transistor M0, gives capacitor C 0 charging, along with the positive pole of capacitor C 0 constantly charges, the voltage that A is ordered starts to rise, and progressively approaches supply voltage, along with the rising of A point voltage, transistor M1 is progressively in closing, until cut-off work, now the voltage of the grid G of transistor M1 is zero, and transistor M3 is in discharge condition, the lower voltage that Y order, and progressively close to zero, this state is maintained to supply voltage Vdd and keeps stable,
In the circuit of this part, the voltage that Y is ordered has experienced the process that rises and decline again, is reduced to again low level state after reaching supply voltage, and this state has produced the reset signal of counter, and flow to the trigger in counter circuit.
As described in Figure 5, described counter circuit is comprised of 6 counters, i.e. counter I41, I42, I43, I44, I45, I46; On described counter I41, I42, I43, I44, I45, I46, be equipped with five connectivity ports, these five connectivity ports, are respectively RESET port, D port, QB port, CLK port, Q port; The RESET end of described counter I0, I41, I43, I42, I47, I46 is electrically connected to the reset exit RESET of counter reset signal generation circuit respectively; The D port of described counter I0, I41, I43, I42, I47, I46 is all electrically connected to the QB port of himself; The Q port of described meter counter I0 is electrically connected to the CLK port of counter I41, and at terminals, is provided with signal and draws interface CLK2; The Q port of described counter I41 is electrically connected to the CLK port of counter I43, and at terminals, is provided with signal and draws interface CLK4; The Q port of described counter I43 is electrically connected to the CLK port of counter I42, and at terminals, is provided with signal and draws interface CLK8; The Q port of described counter I42 is electrically connected to the CLK port of counter I47, and at terminals, is provided with signal and draws interface CLK16; The Q port of described counter I47 is electrically connected to the CLK port of counter I46, and at terminals, is provided with signal and draws interface CLK32; The Q end of described counter I46 is provided with signal and draws interface CLK64;
The quantity of the trigger that preferably, this part circuit is connected is N; This circuit selects 6;
Preferably, the trigger in the circuit of this part is all to adopt high level to trigger, and when the level that CLK end detected changes from high to low, the value of output Q is with different variation of value of input D;
Preferably, QB port is connected with D port, forms 2 frequency dividing circuits; The function of its realization is that the frequency of input signal is reduced to original half, the cycle has been expanded to one times;
Preferably, the Q port of counter I0 and the CLK port of counter I41 are connected; Counter I0 and counter I41 form a two-stage trigger structure; After QB port is connected with D port, at the Q of counter I0 port, form 2 frequency divisions, the frequency division forming at the Q of counter I41 port is 4 frequency divisions; The like, partial circuit, connects six triggers altogether, and the output signal cycle that in the end the output Q of one-level counter I46 produces is exactly 64 times of input signal; It is coded representation that signal in intention is drawn interface, is CLK64=64CLK.
As described in Figure 4, described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; 2 ports of described oscillator I29 are electrically connected to 1 port of inverter I23; 1 port of described oscillator I29 is electrically connected to the CLK port of counter I0,2 ports of inverter I22 respectively; 1 port of described inverter I22 is electrically connected to 2 ports of inverter I27; 1 port of described inverter I27 is electrically connected to 2 ports of inverter I21; State 1 port of inverter I21 and 2 ports of inverter I23 are electrically connected to;
Preferably, this part circuit is for generation of the clock pulse signal of counting use;
Preferably, described signal exit CTRL is the Enable Pin of this part circuit; When CTRL is high level, the NAND gate signal of oscillator is not subject to the interference of this level signal, works on, and whole annular oscillation circuit produces the pulse signal of one fixed width; When CTRL is that low level is, the output CLK of NAND gate is high level, makes the level of each node in pierce circuit maintain a fixed value, and now whole annular oscillation circuit no longer produces pulse signal;
Preferably, ring oscillator is normally by the raw cyclic pulse signal of inverter stage coproduction of odd level; And this part circuit can carry out according to the width of actual reset pulse the adjustment of every grade of time delay of sum of series; Suppose that N represents the number of the inverter that cascade is used, Tdelay represents the time delay of every grade of inverter, be T=2*N*Tdelay the cycle of oscillation of this ring oscillator, in order to obtain a wider reset pulse, we can adopt counter circuit to count this cyclic pulse signal, by counter and logic control, we can obtain the reset pulsewidth that we are scheduled to.Suppose that the value that we identify counting is the width Treset that M controls final reset pulse, Treset=2*M* N*Tdelay; For example: finally to expect the reseting pulse signal of 1us width, select N=7, M=64,7 grades of inverter cascades, are counted as 64, and the time delay of every grade is Tdelay=1us/2*64*7=2.23ns.
As described in Figure 6, described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; 2 ports and the signal of described oscillator I18 drawn interface CLK2 and is electrically connected to; 3 ports and the signal of described oscillator I18 drawn interface CLK4 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK8 and is electrically connected to; 1 port of described oscillator I18 is electrically connected to 2 ports of inverter I17; 1 port of described inverter I17 is electrically connected to 2 ports of oscillator I19; 1 port of described oscillator I19 is electrically connected to 3 ports of oscillator I29, and is provided with signal exit CTRL; 2 ports of described oscillator I19 are electrically connected to 1 port of inverter I15; 2 ports of described inverter I15 are electrically connected to 1 port of oscillator I16; 2 ports and the signal of described oscillator I16 drawn interface CLK16 and is electrically connected to; 3 ports and the signal of described oscillator I16 drawn interface CLK32 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK64 and is electrically connected to;
Preferably, the input of oscillator I18, oscillator I16 is 3 NAND gate;
In counter circuit, it is CLK2, CLK4, CLK8, CLK16, CLK32, CLK64 that the Q of every grade of trigger holds signal to draw interface, a signal of each port output, put them into 2 groups, every group of 3 signals, CLK2, CLK4, CLK8 are connected with 2,3,4 ports of oscillator I18 respectively; CLK16, CLK32, CLK64 are connected with 2,3,4 ports of oscillator I16 respectively; The function that whole combinational logic circuit is realized is exactly, when CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=H(H is high level) time, with the CTRL of logic output terminal be low level, if while having any one signal not for high level in CLK2, CLK4, CLK8, CLK16, these six signals of CLK32, CLK64, CTRL is just high level;
Further, when counter circuit counting CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=111111, CTRL is just low level;
Preferably, the output level of described CTRL is used for controlling ring oscillator; When CTRL is low level, ring oscillator quits work.
As described in Figure 7, described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected to 1 port of buffer I24; 2 ports of described buffer I24 are electrically connected to 1 port of buffer I26; 2 ports of described buffer I26 are electrically connected to signal exit CTRL;
Preferably, described buffer I26 connects with buffer I24; For receiving the pulse signal of CTRL, and the power-on reset signal of stable output.
The course of work: power on to circuit, voltage Vdd switches on power, supply voltage Vdd rising, when supply voltage Vdd is greater than transistor M1, the cut-in voltage of M2, but while being only less than the cut-in voltage of transistor M0, counter reset signal produces circuit and starts working, electric current is through M1, the voltage of RESET end starts to rise to and approaches supply voltage, RESET end in counter reset signal generation circuit is connected with the RESET port of triggers all in counter, making signal draw interface is CLK2, CLK4, CLK8, CLK16, CLK32, the signal of CLK64 is low level, and signal to draw interface be that CLK2, CLK4, CLK8, CLK16, CLK32, CLK64 are divided into two groups and are connected with 2,3,4 ports of oscillator I18 in combinational logic circuit, 2,3,4 ports of oscillator I16 respectively, after the NAND gate and gate action of oscillator I18, oscillator I16 in combinational logic circuit, the level of CTRL is high level, and now, ring oscillator is started working, and produces cyclic pulse signal, the pulse signal of oscillator output provides clock signal for counter circuit, counter in counter circuit starts counting, when CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=111111, NAND gate and gate action through oscillator I18, oscillator I16 in combinational logic circuit, the level of CTRL becomes low level, now oscillator quits work, output pulse signal no longer, counter also maintains 111111 count value always, no longer changes, until whole down circuitry or power down, repeatedly repeat afterwards above-mentioned steps,
In whole power up, the value of CTRL is along with high level appearred one time in power supply electrifying, and the time that maintains high level is 64 cycles, the i.e. width of reset pulse; This signal meets the requirement of electrification reset, has also increased by two buffer I24, I26 in circuit, receives the pulse signal of CTRL, and the reset signal of stable output; Power on stable after, the signal of CTRL becomes low level, ring oscillator, whole circuit is in a static state, the electric current consuming in combinational logic circuit is zero; , after having powered on, whole circuit completes reset function.
Claims (7)
1. the high performance electrify restoration circuit of super low-power consumption, comprises that counter reset signal produces circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; It is characterized in that: described counter signals produces circuit and is electrically connected to counter circuit; Described counter circuit is electrically connected to annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected to combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected to reset terminal circuit respectively;
Described counter reset signal produces circuit and comprises transistor M0, transistor M1, transistor M2, transistor M4, capacitor C 0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected to the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected to the positive pole of capacitor C 0, the grid G of the source S of transistor M2, transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described capacitor C 0; The drain D ground connection of described transistor M1; The drain D of described transistor M1 is electrically connected to the drain D of transistor M3; The drain D of described transistor M3 is electrically connected to the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET;
Described counter circuit is comprised of 6 counters, i.e. counter I0, I41, I43, I42, I47, I46; On described counter I0, I41, I43, I42, I47, I46, be equipped with five connectivity ports, these five connectivity ports, are respectively RESET port, D port, QB port, CLK port, Q port; The RESET end of described counter I0, I41, I43, I42, I47, I46 is electrically connected to the reset exit RESET of counter reset signal generation circuit respectively; The D port of described counter I0, I41, I43, I42, I47, I46 is all electrically connected to the QB port of himself; The Q port of described counter I0 is electrically connected to the CLK port of counter I41, and at terminals, is provided with signal and draws interface CLK2; The Q port of described counter I41 is electrically connected to the CLK port of counter I43, and at terminals, is provided with signal and draws interface CLK4; The Q port of described counter I43 is electrically connected to the CLK port of counter I42, and at terminals, is provided with signal and draws interface CLK8; The Q port of described counter I42 is electrically connected to the CLK port of counter I47, and at terminals, is provided with signal and draws interface CLK16; The Q port of described counter I47 is electrically connected to the CLK port of counter I46, and at terminals, is provided with signal and draws interface CLK32; The Q end of described counter I46 is provided with signal and draws interface CLK64;
Described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; 2 ports of described oscillator I29 are electrically connected to 1 port of inverter I23; 1 port of described oscillator I29 is electrically connected to the CLK port of counter I0,2 ports of inverter I22 respectively; 1 port of described inverter I22 is electrically connected to 2 ports of inverter I27; State 1 port of inverter I27 and 2 ports of inverter I21 are electrically connected to; State 1 port of inverter I21 and 2 ports of inverter I23 are electrically connected to;
Described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; 2 ports and the signal of described oscillator I18 drawn interface CLK2 and is electrically connected to; 3 ports and the signal of described oscillator I18 drawn interface CLK4 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK8 and is electrically connected to; 1 port of described oscillator I18 is electrically connected to 2 ports of inverter I17; 1 port of described inverter I17 is electrically connected to 2 ports of oscillator I19; 1 port of described oscillator I19 is electrically connected to 3 ports of oscillator I29, and is provided with signal exit CTRL; 2 ports of described oscillator I19 are electrically connected to 1 port of inverter I15; 2 ports of described inverter I15 are electrically connected to 1 port of oscillator I16; 2 ports and the signal of described oscillator I16 drawn interface CLK16 and is electrically connected to; 3 ports and the signal of described oscillator I16 drawn interface CLK32 and is electrically connected to; 4 ports and the signal of described oscillator I16 drawn interface CLK64 and is electrically connected to;
Described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected to 1 port of buffer I24; 2 ports of described buffer I24 are electrically connected to 1 port of buffer I26; 2 ports of described buffer I26 are electrically connected to signal exit CTRL.
2. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: described transistor M0, transistor M1, transistor M2 are PMOS pipe; The cut-in voltage of described transistor M0 is greater than transistor M1, and the cut-in voltage of transistor M1 equates with the cut-in voltage of transistor M2; Described transistor M4 is NMOS pipe.
3. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: described counter I0, I41, I43, I42, I47, I46 are high level and trigger, and the maximum count value of counter is 64.
4. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: described QB port is connected with D port, forms 2 frequency dividing circuits; The function of its realization is that the frequency of input signal is reduced to original half, the cycle has been expanded to one times.
5. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: the number of the inverter in described ring oscillator circuit is N.
6. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: the input of described oscillator I18, oscillator I16 is 3 NAND gate.
7. the high performance electrify restoration circuit of described a kind of super low-power consumption according to claim 1, is characterized in that: described buffer I26 connects with buffer I24, for receiving the pulse signal of CTRL, and the power-on reset signal of stable output.
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| CN201310564390.0A CN103595378B (en) | 2013-11-14 | 2013-11-14 | The high performance electrify restoration circuit of a kind of super low-power consumption |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736458A (en) * | 2018-07-20 | 2018-11-02 | 浙江机电职业技术学院 | DA powers on anti-impact circuit in multichannel microcontroller |
| CN113746460A (en) * | 2021-08-19 | 2021-12-03 | 北京中科胜芯科技有限公司 | Multi-power-supply power-on reset circuit |
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| US6040722A (en) * | 1997-05-02 | 2000-03-21 | Samsung Electronics, Co., Ltd. | Power-on reset circuit with adjustable interval |
| US6173436B1 (en) * | 1997-10-24 | 2001-01-09 | Vlsi Technology, Inc. | Standard cell power-on-reset circuit |
| CN1479186A (en) * | 2002-07-23 | 2004-03-03 | ���µ�����ҵ��ʽ���� | Clock multiple circuit |
| CN1481075A (en) * | 2002-07-18 | 2004-03-10 | 三星电子株式会社 | Open reset circuit and method |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| JP2006179139A (en) * | 2004-12-24 | 2006-07-06 | Renesas Technology Corp | Semiconductor device |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
-
2013
- 2013-11-14 CN CN201310564390.0A patent/CN103595378B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040722A (en) * | 1997-05-02 | 2000-03-21 | Samsung Electronics, Co., Ltd. | Power-on reset circuit with adjustable interval |
| US6173436B1 (en) * | 1997-10-24 | 2001-01-09 | Vlsi Technology, Inc. | Standard cell power-on-reset circuit |
| CN1481075A (en) * | 2002-07-18 | 2004-03-10 | 三星电子株式会社 | Open reset circuit and method |
| CN1479186A (en) * | 2002-07-23 | 2004-03-03 | ���µ�����ҵ��ʽ���� | Clock multiple circuit |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| JP2006179139A (en) * | 2004-12-24 | 2006-07-06 | Renesas Technology Corp | Semiconductor device |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108736458A (en) * | 2018-07-20 | 2018-11-02 | 浙江机电职业技术学院 | DA powers on anti-impact circuit in multichannel microcontroller |
| CN108736458B (en) * | 2018-07-20 | 2023-10-17 | 浙江机电职业技术学院 | DA power-on anti-impact circuit in multichannel microcontroller chip |
| CN113746460A (en) * | 2021-08-19 | 2021-12-03 | 北京中科胜芯科技有限公司 | Multi-power-supply power-on reset circuit |
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| Publication number | Publication date |
|---|---|
| CN103595378B (en) | 2016-01-13 |
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