CN103595378B - The high performance electrify restoration circuit of a kind of super low-power consumption - Google Patents
The high performance electrify restoration circuit of a kind of super low-power consumption Download PDFInfo
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- CN103595378B CN103595378B CN201310564390.0A CN201310564390A CN103595378B CN 103595378 B CN103595378 B CN 103595378B CN 201310564390 A CN201310564390 A CN 201310564390A CN 103595378 B CN103595378 B CN 103595378B
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Abstract
The invention discloses a kind of novel electrify restoration circuit, mainly comprise counter reset signal and produce circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; Described counter signals produces circuit and is electrically connected with counter circuit; Described counter circuit is electrically connected with annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected with combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected with reset terminal circuit respectively.The present invention adopts digital circuit structure to realize electrification reset function; Hold level height information by rolling counters forward display CTRL, the level held by the CTRL of the signal output part of oscillator height controls the work of oscillator; And in the end add two buffers I24, I26, receive the pulse signal of CTRL, and the reset signal of stable output, realize reset function; The reset function of high-performance, low-power consumption is achieved while satisfied saving chip area.
Description
Technical field
The present invention relates to a kind of electrify restoration circuit, particularly relate to the high performance electrify restoration circuit of a kind of super low-power consumption for hand-held electronic very product.
Background technology
Electrify restoration circuit exists in the circuit of electronic product, and its performance generally affects the performance of integrated circuit directly or indirectly.And the electrify restoration circuit of extensive use in the market, generally all adopt simulation circuit structure, mainly decided the broadband of reset pulse by RC discharge and recharge; When use powers on slowly, the form of electric resistance partial pressure is usually adopted to decide the voltage of electrification reset.Its circuit structure as shown in Figure 1, mainly comprises input voltage Vdd, earth terminal GND, reset terminal RESET, circuit R0, resistance R1, resistance R2, resistance R3, electric capacity C0, counter I1, counter I12, oscillator I7, transistor NM0 and transistor NM1; Input voltage Vdd is electrically connected with one end of resistance R0, R1, R3 respectively; The other end of resistance R0 is electrically connected with the positive pole of electric capacity C0, the output 1 of counter I1, the drain D of transistor NM0 respectively; The input 2 of counter I1 is electrically connected with the input 2 of oscillator I7; The other end of resistance R1 is electrically connected with one end of resistance R2, the grid G of transistor NM1 respectively; Resistance R3 is electrically connected with the output 1 of oscillator I7, the drain D of transistor NM1, the grid G of transistor NM0 respectively; 3 ports of oscillator I7 are electrically connected with the output 1 of counter I12; The input 2 of counter I12 connects reset terminal RESET; The negative pole of electric capacity CO, the source S of transistor NM0, the other end of resistance R2, the source S of transistor NM1 are electrically connected with earth terminal GND respectively; Although foregoing circuit structure can realize electrification reset function, there is following defect: if first, this circuit be when will realize wider electrification reset pulse, RC get will be enough large, need to take enough chip areas, cause chip area to increase; The second, there is multiple current branch in circuit, size and the resistance of quiescent current are inversely proportional to, and usually will increase the resistance of resistance when meeting power consumption demand, certainly will cause the increase of the power consumption of integrated circuit like this; Simultaneously due to the increase of resistance, also increase the demand to chip area to a certain extent.
Adopt simulation circuit structure cannot meet low-power consumption and these two requirements little of domain area occupied for solving electrify restoration circuit simultaneously; In order to solve this this problem, the present invention adopts the electrify restoration circuit of numeric structure, and the reset realizing Low Power High Performance controls.
Summary of the invention
The object of the present invention is to provide that a kind of structure is simple, domain area occupied is little, effectively can realize the reset circuit that low power consumption high-precision controls.
The present invention includes counter reset signal and produce circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; Described counter signals produces circuit and is electrically connected with counter circuit; Described counter circuit is electrically connected with annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected with combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected with reset terminal circuit respectively.
Described counter reset signal produces circuit and comprises transistor M0, transistor M1, transistor M2, transistor M3, electric capacity C0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected with the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected with the positive pole of electric capacity C0, the source S of transistor M2, the grid G of transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described electric capacity C0; The drain D ground connection of described transistor M1; The drain D of described transistor M1 is electrically connected with the drain D of transistor M2; The drain D of described transistor M3 is electrically connected with the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET.
Described counter circuit is made up of 6 counters, i.e. counter I0, I41, I43, I42, I47, I46; Described counter I0, I41, I43, I42, I47, I46 being equipped with five connectivity ports, these five connectivity ports, is RESET port, D port, QB port, CLK port, Q port respectively; The RESET of described counter I0, I41, I43, I42, I47, I46 holds the reset exit RESET producing circuit respectively with counter reset signal to be electrically connected; The D port of described counter I0, I41, I43, I42, I47, I46 is all electrically connected with the QB port of himself; The Q port of described counter I0 is electrically connected with the CLK port of counter I41, and is provided with signal extraction interface CLK2 at terminals; The Q port of described counter I41 is electrically connected with the CLK port of counter I43, and is provided with signal extraction interface CLK4 at terminals; The Q port of described counter I43 is electrically connected with the CLK port of counter I42, and is provided with signal extraction interface CLK8 at terminals; The Q port of described counter I42 is electrically connected with the CLK port of counter I47, and is provided with signal extraction interface CLK16 at terminals; The Q port of described counter I47 is electrically connected with the CLK port of counter I46, and is provided with signal extraction interface CLK32 at terminals; The Q end of described counter I46 is provided with signal and draws interface CLK64.
Described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; The input 2 of described oscillator I29 is electrically connected with the output 1 of inverter I23; The output 1 of described oscillator I29 is electrically connected with the CLK port of counter I0, the input 2 of inverter I22 respectively; The output 2 of described inverter I22 is electrically connected with the input 2 of inverter I27; The input 2 of the output 1 and inverter I21 of stating inverter I27 is electrically connected; The input 2 of the output 2 and inverter I23 of stating inverter I21 is electrically connected.
Described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; Input 2 and the signal of described oscillator I18 are drawn interface CLK2 and are electrically connected; 3 ports and the signal of described oscillator I18 are drawn interface CLK4 and are electrically connected; 4 ports and the signal of described oscillator I16 are drawn interface CLK8 and are electrically connected; The output 2 of described oscillator I18 is electrically connected with the input 2 of inverter I17; The output 2 of described inverter I17 is electrically connected with the input 2 of oscillator I19; The output 1 of described oscillator I19 is electrically connected with 3 ports of oscillator I29, and is provided with signal exit CTRL; The input 2 of described oscillator I19 is electrically connected with the output 1 of inverter I15; The input 2 of described inverter I15 is electrically connected with the output 1 of oscillator I16; Input 2 and the signal of described oscillator I16 are drawn interface CLK16 and are electrically connected; 3 ports and the signal of described oscillator I16 are drawn interface CLK32 and are electrically connected; 4 ports and the signal of described oscillator I16 are drawn interface CLK64 and are electrically connected.
Described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected with the output 1 of buffer I24; The input 2 of described buffer I24 is electrically connected with the output 1 of buffer I26; The input 2 of described buffer I26 is electrically connected with signal exit CTRL.
Described transistor M0, transistor M1, transistor M2 are PMOS; Described transistor M3 is NMOS tube.
Described counter is that high level triggers, and the maximum count value of counter is 64.
The number of the inverter in described ring oscillator circuit is N; This circuit selects 6.
The present invention adopts digital circuit structure to realize electrification reset function; Hold level height information by rolling counters forward display CTRL, the level held by the CTRL of the signal output part of oscillator height controls the work of oscillator; And in the end add two buffers I24, I26, receive the pulse signal of CTRL, and the reset signal of stable output, realize reset function; The reset function of high-performance, low-power consumption is achieved while satisfied saving chip area.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of prior art;
Fig. 2 is schematic block diagram of the present invention;
Fig. 3 is that counter reset signal produces circuit theory diagrams;
Fig. 4 is counter circuit schematic diagram;
Fig. 5 is Combinational Logic Control circuit theory diagrams;
Fig. 6 is ring oscillator circuit schematic diagram;
Fig. 7 is the integrally-built circuit theory diagrams of the present invention.
Embodiment
The invention will be further described for the embodiment provided below in conjunction with accompanying drawing:
As described in Figure 2, the present invention includes counter reset signal and produce circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; Described counter signals produces circuit and is electrically connected with counter circuit; Described counter circuit is electrically connected with annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected with combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected with reset terminal circuit respectively.
As described in Figure 3, described counter reset signal generation circuit comprises transistor M0, transistor M1, transistor M2, transistor M3, electric capacity C0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected with the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected with the positive pole of electric capacity C0, the source S of transistor M2, the grid G of transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described electric capacity C0; The drain D ground connection of described transistor M1; The drain D of described transistor M1 is electrically connected with the drain D of transistor M2; The drain D of described transistor M3 is electrically connected with the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET;
The effect of this part circuit is when power supply electrifying, and provide an of short duration reset pulse to counter circuit, make counter resets, namely the initial count value of counter is 0;
In this circuit, described transistor M0, transistor M1, transistor M2 all select PMOS, and the cut-in voltage of transistor M0 is greater than transistor M1, and the cut-in voltage of transistor M1 is equal with the cut-in voltage of transistor M2; Described transistor M3 selects NMOS tube, and selects fall than pipe larger than length of the width of the pipe of crystal, and the electric current contributing to like this flowing through when pipe conducting is less;
Switch on power voltage Vdd, makes power on circuitry; When voltage does not reach the cut-in voltage of transistor M1, M2, because the cut-in voltage of M0 is also greater than M1, so M0 and M1 ends, the current branch at their places does not have electric current, M2 directly accesses power supply due to grid end, for the ceiling voltage of circuit, its source and grid terminal voltage difference may arrive cut-in voltage value never in normal state, so it is also cut-off.Transistor M0, M1, M2, M3 that now whole counter reset signal produces in circuit are all in by state, and do not have current loss in circuit, output voltage is also extremely low, supply voltage Vdd continues to rise, when supply voltage Vdd is greater than transistor M1, the cut-in voltage of M2, but when being only less than the cut-in voltage of transistor M0, now transistor M0 ends, the current branch at its place do not have electric current, so A point in circuit, namely the upper end of electric capacity C0 is not because have charging current, so voltage is 0V, and now on transistor M1 the voltage difference of source electrode and grid G end be more than or equal to the cut-in voltage of transistor M1, transistor M1 starts ON operation, start the drain D end having electric current by transistor M1, the voltage of the point of the Y in circuit is made to start to rise, because MOSM3 is below down than pipe, equivalent resistance is very large, so charging current is obviously greater than discharging current, Y point voltage is constantly raised and progressively close to supply voltage Vdd, after this, supply voltage Vdd continues to rise, until the magnitude of voltage of X point reaches the cut-in voltage value of transistor M0, and now transistor M0 conducting, electric current, through transistor M0, charges to electric capacity C0, along with the positive pole of electric capacity C0 constantly charges, the voltage of A point starts to rise, and progressively close to supply voltage, along with the rising of A point voltage, transistor M1 is progressively in closedown, until cut-off work, now the voltage of the drain D of transistor M1 is zero, and transistor M3 is in discharge condition, and the voltage of Y point is reduced, and progressively close to zero, this state is maintained to supply voltage Vdd and keeps stable,
Not only in the circuit of this part, the voltage of Y point experienced by the process that rising declines again, and be reduced to low level state after reaching supply voltage, this state creates the reset signal of counter, and flows to the trigger in counter circuit.
As described in Figure 4, described counter circuit is made up of 6 counters, i.e. counter I0, I41, I43, I42, I47, I46; Described counter I0, I41, I43, I42, I47, I46 being equipped with five connectivity ports, these five connectivity ports, is RESET port, D port, QB port, CLK port, Q port respectively; The RESET of described counter I0, I41, I43, I42, I47, I46 holds the reset exit RESET producing circuit respectively with counter reset signal to be electrically connected; The D port of described counter I41, I42, I43, I44, I45, I46 is all electrically connected with the QB port of himself; The described Q port of meter counter I0 is electrically connected with the CLK port of counter I41, and is provided with signal extraction interface CLK2 at terminals; The Q port of described counter I41 is electrically connected with the CLK port of counter I43, and is provided with signal extraction interface CLK4 at terminals; The Q port of described counter I43 is electrically connected with the CLK port of counter I42, and is provided with signal extraction interface CLK8 at terminals; The Q port of described counter I42 is electrically connected with the CLK port of counter I47, and is provided with signal extraction interface CLK16 at terminals; The Q port of described counter I47 is electrically connected with the CLK port of counter I46, and is provided with signal extraction interface CLK32 at terminals; The Q end of described counter I46 is provided with signal and draws interface CLK64;
Preferably, the quantity of trigger that this part circuit is connected is N; This circuit selects 6;
Preferably, the trigger in the circuit of this part is all adopt high level to trigger, and when namely detecting that the level that CLK holds changes from high to low, the value of output Q changes with the value difference of input D;
Preferably, QB port is connected with D port, forms 2 frequency dividing circuits; Its function realized is that the frequency of input signal is reduced to original half, namely the cycle is expanded one times;
Preferably, the Q port of counter I0 is connected with the CLK port of counter I41; Counter I0 and counter I41 forms a two-stage trigger structure; After QB port is connected with D port, form 2 frequency divisions at the Q port of counter I0, then the frequency division formed at the Q port of counter I41 is 4 frequency divisions; The like, partial circuit, connects six triggers altogether, and the output signal cycle that in the end the output Q of one-level counter I46 produces is exactly 64 times of input signal; It is coded representation that signal in intention draws interface, is CLK64=64CLK.
As described in Figure 6, described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; The input 2 of described oscillator I29 is electrically connected with the output 1 of inverter I23; The output 2 of described oscillator I29 is electrically connected with the CLK port of counter I0, the input 2 of inverter I22 respectively; The output 2 of described inverter I22 is electrically connected with the input 2 of inverter I27; The output 2 of described inverter I27 is electrically connected with the input 2 of inverter I21; The input 2 of the output 1 and inverter I23 of stating inverter I21 is electrically connected;
Preferably, this part circuit is for generation of the clock pulse signal of counting;
Preferably, described signal exit CTRL is the Enable Pin of this part circuit; When CTRL is high level, the NAND gate signal of oscillator, not by the interference of this level signal, works on, and whole annular oscillation circuit produces the pulse signal of one fixed width; Be that the output CLK of NAND gate is high level when CTRL is low level, make the level of each node in pierce circuit maintain a fixed value, now whole annular oscillation circuit no longer produces pulse signal;
Preferably, ring oscillator is normally by the raw cyclic pulse signal of the inverter stage coproduction of odd level; And this part circuit can carry out the adjustment of sum of series every grade time delay according to the width of actual reset pulse; Suppose that N represents the number of the inverter that cascade is used, Tdelay represents the time delay of every grade of inverter, then be T=2*N*Tdelay the cycle of oscillation of this ring oscillator, in order to obtain a wider reset pulse, we can adopt counter circuit to count this cyclic pulse signal, by counter and logic control, we can obtain our predetermined reset pulsewidth.Suppose that the value that we identify counting is that M is to control the width Treset of final reset pulse, then Treset=2*M*N*Tdelay; Such as: finally to expect the reseting pulse signal of 1us width, select N=7, M=64, namely 7 grades of inverter cascades, are counted as 64, then the time delay of every grade is Tdelay=1us/2*64*7=2.23ns.
As described in Figure 5, described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; Input 2 and the signal of described oscillator I18 are drawn interface CLK2 and are electrically connected; 3 ports and the signal of described oscillator I18 are drawn interface CLK4 and are electrically connected; 4 ports and the signal of described oscillator I16 are drawn interface CLK8 and are electrically connected; The output 2 of described oscillator I18 is electrically connected with the input 2 of inverter I17; The output 2 of described inverter I17 is electrically connected with the input 2 of oscillator I19; The output 1 of described oscillator I19 is electrically connected with 3 ports of oscillator I29, and is provided with signal exit CTRL; The input 2 of described oscillator I19 is electrically connected with the output 2 of inverter I15; The input 2 of described inverter I15 is electrically connected with the output 2 of oscillator I16; Input 2 and the signal of described oscillator I16 are drawn interface CLK16 and are electrically connected; 3 ports and the signal of described oscillator I16 are drawn interface CLK32 and are electrically connected; 4 ports and the signal of described oscillator I16 are drawn interface CLK64 and are electrically connected;
Preferably, the input of oscillator I18, oscillator I16 is 3 NAND gate;
In counter circuit, the Q of every grade of trigger holds signals to draw interface and CLK2, CLK4, CLK8, CLK16, CLK32, CLK64, each port exports a signal, put them into 2 groups, often organize 3 signals, namely CLK2, CLK4, CLK8 are connected with 2,3,4 ports of oscillator I18 respectively; CLK16, CLK32, CLK64 are connected with 2,3,4 ports of oscillator I16 respectively; The function that then whole combinational logic circuit realizes is exactly, when CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=H (H is high level), be low level with the CTRL of logic output terminal, if when having any one signal not in these six signals of CLK2, CLK4, CLK8, CLK16, CLK32, CLK64 for high level, CTRL is just high level;
Further, when counter circuit counting CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=111111, CTRL is just low level;
Preferably, the output level of described CTRL is for controlling ring oscillator; When CTRL is low level, ring oscillator quits work.
As described in Figure 7, described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected with the output 2 of buffer I24; The input 2 of described buffer I24 is electrically connected with the output 2 of buffer I26; The input 2 of described buffer I26 is electrically connected with signal exit CTRL;
Preferably, described buffer I26 connects with buffer I24; For receiving the pulse signal of CTRL, and the power-on reset signal of stable output.
The course of work: power on to circuit, switch on power voltage Vdd, supply voltage Vdd slowly rises, when supply voltage Vdd is greater than transistor M1, the cut-in voltage of M2, but when being only less than the cut-in voltage of transistor M0, counter reset signal produces circuit and starts working, electric current is through M1, the voltage of RESET end starts to rise to close to supply voltage, the RESET end that counter reset signal produces in circuit is connected with the RESET port of triggers all in counter, signal is made to draw interface and CLK2, CLK4, CLK8, CLK16, CLK32, the signal of CLK64 is low level, and signal is drawn interface and CLK2, CLK4, CLK8, CLK16, CLK32, CLK64 and is divided into two groups and is connected with 2,3,4 ports of oscillator I18 in combinational logic circuit, 2,3,4 ports of oscillator I16 respectively, after the NAND gate and gate action of oscillator I18, oscillator I16 in combinational logic circuit, the level of CTRL is high level, and now, ring oscillator is started working, and produces cyclic pulse signal, the pulse signal that oscillator exports is that counter circuit provides clock signal, counter in counter circuit starts counting, as CLK2=CLK4=CLK8=CLK16=CLK32=CLK64=111111, the NAND gate of oscillator I18, oscillator I16 and gate action in combinational logic circuit, the level of CTRL becomes low level, now oscillator quits work, no longer output pulse signal, counter also maintains the count value of 111111 always, no longer changes, until whole down circuitry or power down, repeatedly repeat above-mentioned steps afterwards,
In whole power up, there is a high level along with power supply electrifying in the value of CTRL, the time maintaining high level is 64 cycles, the i.e. width of reset pulse; This signal meets the requirement of electrification reset, also add two buffers I24, I26 in circuit, receives the pulse signal of CTRL, and the reset signal of stable output; Power on stable after, the signal of CTRL becomes low level, ring oscillator, and whole circuit is in a static state, and the electric current consumed in combinational logic circuit is zero; Namely, after having powered on, whole circuit completes reset function.
Claims (4)
1. the high performance electrify restoration circuit of super low-power consumption, comprises counter reset signal and produces circuit, annular oscillation circuit, counter circuit, combinational logic circuit and reset terminal circuit; It is characterized in that: described counter signals produces circuit and is electrically connected with counter circuit; Described counter circuit is electrically connected with annular oscillation circuit, combinational logic circuit respectively; Described annular oscillation circuit is electrically connected with combinational logic circuit; Described annular oscillation circuit, combinational logic circuit are electrically connected with reset terminal circuit respectively;
Described counter reset signal produces circuit and comprises transistor M0, transistor M1, transistor M2, transistor M3, electric capacity C0, supply voltage Vdd and earth terminal GND; The source S of described transistor M0 is electrically connected with the grid G of supply voltage Vdd, transistor M2, the source S of transistor M1 respectively; The drain D of described transistor M0 is electrically connected with the positive pole of electric capacity C0, the source S of transistor M2, the grid G of transistor M1 respectively; The grid G ground connection of described transistor M0; The minus earth of described electric capacity C0; The drain D ground connection of described transistor M2; The drain D of described transistor M1 is electrically connected with the drain D of transistor M3; The drain D of described transistor M3 is electrically connected with the grid G of transistor M3; The source S ground connection of described transistor M3; The connecting line of described transistor M1 drain D and transistor M3 drain D is provided with a reset exit RESET;
Described counter circuit is made up of 6 counters, i.e. counter I0, I41, I43, I42, I47, I46; Described counter I0, I41, I43, I42, I47, I46 being equipped with five connectivity ports, these five connectivity ports, is RESET port, D port, QB port, CLK port, Q port respectively; The RESET of described counter I0, I41, I43, I42, I47, I46 holds the reset exit RESET producing circuit respectively with counter reset signal to be electrically connected; The D port of described counter I0, I41, I43, I42, I47, I46 is all electrically connected with the QB port of himself; The Q port of described counter I0 is electrically connected with the CLK port of counter I41, and is provided with signal extraction interface CLK2 at terminals; The Q port of described counter I41 is electrically connected with the CLK port of counter I43, and is provided with signal extraction interface CLK4 at terminals; The Q port of described counter I43 is electrically connected with the CLK port of counter I42, and is provided with signal extraction interface CLK8 at terminals; The Q port of described counter I42 is electrically connected with the CLK port of counter I47, and is provided with signal extraction interface CLK16 at terminals; The Q port of described counter I47 is electrically connected with the CLK port of counter I46, and is provided with signal extraction interface CLK32 at terminals; The Q end of described counter I46 is provided with signal and draws interface CLK64;
Described ring oscillator circuit comprises oscillator I29, inverter I22, inverter I27, inverter I21 and inverter I23; The input 2 of described oscillator I29 is electrically connected with the output 1 of inverter I23; The output 1 of described oscillator I29 is electrically connected with the CLK port of counter I0, the input 2 of inverter I22 respectively; The output 1 of described inverter I22 is electrically connected with the input 2 of inverter I27; The input 2 of the output 1 and inverter I21 of stating inverter I27 is electrically connected; The input 2 of the output 1 and inverter I23 of stating inverter I21 is electrically connected;
Described combinational logic circuit comprises oscillator I16, oscillator I18, oscillator I19, inverter I15 and inverter I17; Input 2 and the signal of described oscillator I18 are drawn interface CLK2 and are electrically connected; Input 3 and the signal of described oscillator I18 are drawn interface CLK4 and are electrically connected; Input port 3 and the signal of described oscillator I18 are drawn interface CLK8 and are electrically connected; The output 1 of described oscillator I18 is electrically connected with the input 2 of inverter I17; The output 1 of described inverter I17 is electrically connected with the input 2 of oscillator I19; The output 1 of described oscillator I19 is electrically connected with the port 3 of oscillator I29, and is provided with signal exit CTRL; The input 3 of described oscillator I19 is electrically connected with the output 1 of inverter I15; The input 2 of described inverter I15 is electrically connected with the output 1 of oscillator I16; Input 2 and the signal of described oscillator I16 are drawn interface CLK16 and are electrically connected; Input 3 and the signal of described oscillator I16 are drawn interface CLK32 and are electrically connected; Input 4 and the signal of described oscillator I16 are drawn interface CLK64 and are electrically connected;
Described reset terminal circuit comprises reset terminal RST, buffer I26 and buffer I24; Described reset terminal RST is electrically connected with the output 1 of buffer I24; The input 2 of described buffer I24 is electrically connected with the output 1 of buffer I26; The input 2 of described buffer I26 is electrically connected with signal exit CTRL
Described transistor M0, transistor M1, transistor M2 are PMOS; The cut-in voltage of described transistor M0 is greater than transistor M1, and the cut-in voltage of transistor M1 is equal with the cut-in voltage of transistor M2; Described transistor M3 is NMOS tube.
2. the high performance electrify restoration circuit of a kind of super low-power consumption according to claim 1, is characterized in that: described counter I41, I42, I43, I44, I45, I46 are high level and trigger, and the maximum count value of counter is 64.
3. the high performance electrify restoration circuit of a kind of super low-power consumption according to claim 1, is characterized in that: described QB port is connected with D port, forms 2 frequency dividing circuits; Its function realized is that the frequency of input signal is reduced to original half, namely the cycle is expanded one times.
4. the high performance electrify restoration circuit of a kind of super low-power consumption according to claim 1, is characterized in that: described buffer I26 connects with buffer I24, for receiving the pulse signal of CTRL, and the power-on reset signal of stable output.
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| CN113746460A (en) * | 2021-08-19 | 2021-12-03 | 北京中科胜芯科技有限公司 | Multi-power-supply power-on reset circuit |
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| CN1481075A (en) * | 2002-07-18 | 2004-03-10 | 三星电子株式会社 | Open reset circuit and method |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| JP2006179139A (en) * | 2004-12-24 | 2006-07-06 | Renesas Technology Corp | Semiconductor device |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
-
2013
- 2013-11-14 CN CN201310564390.0A patent/CN103595378B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6040722A (en) * | 1997-05-02 | 2000-03-21 | Samsung Electronics, Co., Ltd. | Power-on reset circuit with adjustable interval |
| US6173436B1 (en) * | 1997-10-24 | 2001-01-09 | Vlsi Technology, Inc. | Standard cell power-on-reset circuit |
| CN1481075A (en) * | 2002-07-18 | 2004-03-10 | 三星电子株式会社 | Open reset circuit and method |
| CN1479186A (en) * | 2002-07-23 | 2004-03-03 | ���µ�����ҵ��ʽ���� | Clock multiple circuit |
| US7057427B2 (en) * | 2004-07-15 | 2006-06-06 | Freescale Semiconductor, Inc | Power on reset circuit |
| JP2006179139A (en) * | 2004-12-24 | 2006-07-06 | Renesas Technology Corp | Semiconductor device |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN102497181A (en) * | 2011-12-22 | 2012-06-13 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
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| CN103595378A (en) | 2014-02-19 |
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