CN100568728C - A kind of clock signal detection circuit - Google Patents
A kind of clock signal detection circuit Download PDFInfo
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- CN100568728C CN100568728C CNB2005101168922A CN200510116892A CN100568728C CN 100568728 C CN100568728 C CN 100568728C CN B2005101168922 A CNB2005101168922 A CN B2005101168922A CN 200510116892 A CN200510116892 A CN 200510116892A CN 100568728 C CN100568728 C CN 100568728C
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Abstract
The invention discloses a kind of clock signal detection device, comprise a voltage control delay cell, XOR gate, inverter, low pass filter, PMOS pipe, constant-current source, resistance, electric capacity and level shifting circuit.Input clock connects the input end of clock of voltage control delay cell and an input of XOR gate simultaneously, and the output of voltage control delay cell connects another input of XOR gate; The output of XOR gate connects the input of inverter and the input of low pass filter simultaneously, the voltage controling end of the output termination voltage control delay cell of low pass filter; The output of inverter connects the grid of PMOS pipe; The output of the source termination constant-current source of PMOS pipe, an other termination power of constant-current source; The drain terminal of PMOS pipe connects an end of parallel resistor and electric capacity and the input of level shifting circuit simultaneously, an other end ground connection of parallel resistance and electric capacity; The output of level shifting circuit is exactly the output of testing circuit.
Description
Technical field
What the present invention relates to is the digital circuit field, and what be specifically related to is clock signal detection circuit.
Background technology
In the sequential logic digital circuit, clock signal is very crucial signal, if clock signal is lost or be wrong, the function of these digital circuits just can not be implemented so, so it is just very necessary to detect this clock signal.When detecting clock signal, if, will additionally provide a very reliable clock to be this testing circuit service again with sequential logic commonly used.And if realize that with combinational logic circuit just do not need with extra clock signal, testing circuit work is also more reliable.
In the testing circuit of realizing with combinational logic, U.S. Patent number provides a kind of clock detection circuit for the patent of US6707320B2, as shown in Figure 1.Clock signal one tunnel is directly imported XOR gate, one tunnel an other end through input XOR gate after the time-delay of certain hour, obtain a pulse signal through each rising and falling edges at clock behind the xor operation, the Kai Heguan of this signal controlling NMOS pipe, thereby the charging and the discharge of the electric capacity of control and the parallel connection of PMOS pipe.
Clock signal just often, the NMOS pipe is in continuous on off state electric capacity is discharged and recharged, here the PMOS pipe to the capacitance discharges electric current greater than the charging current of NMOS pipe to electric capacity, the voltage of Schmidt trigger input constantly reduces like this, output low level when being lower than its low level threshold value is high through clock detection circuit indication behind the inverter.
When if clock signal is lost, the XOR gate output low level, NMOS manages shutoff, and to high level, indicate low through clock detection circuit behind the inverter by trigger output high level by the PMOS tube discharge for electric capacity.
The shortcoming of this circuit is embodied in the following aspects: the one, when coming the delayed clock circuit with buffer, because the influence of process deviation, working temperature etc., alter a great deal the time of delay of circuit, the pulse duration that causes XOR gate output can not correctly detect clock signal also in very big range when the poorest; The 2nd, when the frequency change of input clock signal, also can change the time of delay of buffer.
Summary of the invention
A kind of clock signal detection circuit that the problem that purpose of the present invention changed with process deviation, working temperature and frequency input signal for the time of delay that solves buffer of the prior art proposes.
In order to realize the foregoing invention purpose, the present invention specifically is achieved in that
A kind of clock signal detection circuit is characterized in that, comprising:
Voltage control delay cell, XOR gate, inverter, low pass filter, PMOS pipe, constant-current source, resistance, electric capacity and a level shifting circuit;
Input clock connects the input end of clock of voltage control delay cell and an input of XOR gate simultaneously, and the output of voltage control delay cell connects another input of XOR gate; The output of XOR gate connects the input of inverter and the input of low pass filter simultaneously, the voltage controling end of the output termination voltage control delay cell of low pass filter; The output of inverter connects the grid of PMOS pipe; The output of the source termination constant-current source of PMOS pipe, an other termination power of constant-current source; The drain terminal of PMOS pipe connects an end of parallel resistor and electric capacity and the input of level shifting circuit simultaneously, an other end ground connection of parallel resistance and electric capacity; The output of level shifting circuit is exactly the output of testing circuit.
Described voltage control delay cell specifically comprises four basic voltage control delay cells and a buffer;
Described basic voltage control delay cell comprises two NMOS pipes and a PMOS pipe;
Described buffer is used for the clock of voltage control delay cell output is carried out shaping.
The time of delay of described voltage control delay cell and control voltage are inversely proportional to, and when control voltage was high, time of delay was little, when control voltage is low, become time of delay big;
The maximum delay time of voltage control delay cell and the difference of minimum delay time are less than the cycle of input clock signal.
The output pulse width of XOR gate can be maintained fixed constant.
Described constant-current source comprises two PMOS pipes and 1 NMOS pipe;
The electric current of described constant-current source is greater than the electric current of the described resistance of process to described capacitor discharge;
The product of described resistance and electric capacity is greater than the cycle of the input clock signal of twice.
Described low pass filter can adopt passive low ventilating filter, also can adopt active low-pass filter.
Described low pass filter comprises NMOS pipe, PMOS pipe, resistance and two electric capacity.
Described level shifting circuit can adopt Schmidt trigger, slow phase device to realize, also can adopt circuit such as comparator to realize.
Adopt clock signal detection circuit of the present invention, compare with clock signal detection circuit of the prior art, can control the pulse duration that XOR gate is exported by the loop that XOR gate, voltage control delay cell and low pass filter are formed, avoided because variations such as technology, temperature cause the XOR gate output pulse width too little, and made the switching circuit cisco unity malfunction of back.When frequency input signal changed, because circuit of the present invention has the function of voltage delay time adjusting, the output pulse width of XOR gate also can be maintained fixed constant, and clock detection circuit can be worked more reliably simultaneously.
Description of drawings
Fig. 1 is that the patent No. is the US6707320B2 structure chart;
Fig. 2 is a clock signal detection circuit structure chart of the present invention;
Fig. 3 is the graph of a relation of voltage control delay cell time of delay of the present invention and control voltage;
Fig. 4 is the key point oscillogram of clock signal detection circuit of the present invention;
Fig. 5 is the structure chart of the embodiment of the invention;
Fig. 6 is the embodiment of voltage control delay cell in the embodiment of the invention.
Embodiment
Do explanation in further detail below in conjunction with the embodiment of device of the present invention.
A kind of clock signal detection circuit comprises that a voltage control delay cell, XOR gate X, inverter I, low pass filter, PMOS manage M, constant-current source I
0, resistance R, capacitor C and level shifting circuit, physical circuit sees Fig. 2 for details.
The concrete connection of clock signal detection circuit is as follows: input clock connects the input end of clock of voltage control delay cell and the input of XOR gate X simultaneously, and the output of voltage control delay cell connects another input of XOR gate X; The output of XOR gate connects the input of inverter and the input of low pass filter simultaneously, the voltage controling end of the output termination voltage control delay cell of low pass filter; The output of inverter connects the grid of PMOS pipe M; The output of the source termination constant-current source of M pipe, an other termination power of constant-current source; The drain terminal of M pipe connects an end of parallel resistor R and capacitor C and the input of level shifting circuit simultaneously, the other end ground connection of R in parallel and C; The output of level shifting circuit is exactly the output index signal of clock signal detection circuit.Clock signal detection circuit output high level represents that clock signal is normal, and the clock signal detection circuit output low level represents that clock signal loses.
The relation of the time of delay of voltage control delay cell and control voltage is seen Fig. 3, and time of delay and control voltage are inversely proportional to.When control voltage was high, time of delay was little; When control voltage is low, become time of delay big.The maximum delay time of voltage control delay cell and the difference of minimum delay time are less than the cycle of input clock signal.
Fig. 4 is the oscillogram of main nodes of the present invention.The A point is the oscillogram of control PMOS pipe M, and PMOS opens the capacitor C charging during low level, and the B point is the voltage waveform on the capacitor C, and this voltage is exported through after the level conversion.
Fig. 5 is the structure chart of device embodiment of the present invention.PMOS pipe M2, M3 and NMOS pipe M4 constitute current source I
0, NMOS pipe M5, PMOS pipe M6, resistance R 2, capacitor C 2 and C3 constitute low pass filter.Low pass filter is charge pump the discharging and recharging of being made up of NMOS pipe M5 and PMOS pipe M6 by the pulse signal control of XOR gate X output capacitor C 2 and C 3, M5 opens capacitor C 2, C3 discharge during high level, M6 opens capacitor C 2, C 3 chargings during low level, thereby realizes filter function.
Fig. 6 is the circuit diagram of voltage control delay cell, and NMOS pipe M11, M12 and PMOS pipe M13 have formed a basic voltage control delay cell, can control size time of delay of basic delay cell by the size of current of voltage control NMOS pipe M11; M14, M15, M16, M17, M18, M19 and M20, M21, M22 form other three basic voltage control delay cells respectively, four such delay cell and buffer buf form complete voltage control delay cell, and the effect of buffer buf is that the clock signal of delay cell output is carried out shaping.
The level shifting circuit Schmitt trigger circuit.
The operation principle of this clock signal detection circuit is: when the clock dropout, because delay cell is to not influence of direct current signal, two input end signals that are input to XOR gate are identical, and the XOR gate output low level is turn-offed through output high level control M behind the inverter.Electric charge on the capacitor C 1 discharges by R1, when discharging into the conversion low level that is lower than Schmitt trigger circuit, and the level shifting circuit output low level, the expression clock signal is lost.
When the clock signal just often, voltage control delay cell can produce certain delay to the clock signal of input, through the clock signal that postpones with not carry out xor operation through the clock signal that postpones, will be at each clock along producing a pulse.
When pulse was low level, the M pipe was opened, and current source is to capacitor C 1 charging; When pulse was high level, the M pipe was closed, and current source is to capacitor C 1 discharge.
If change owing to reasons such as process deviation, temperature change can cause the time of delay of delay cell, the output pulse width of XOR gate X narrows down or broadens.The output of XOR gate X has filtered radio-frequency component wherein, output dc voltage through low pass filter.
When the pulse duration of XOR gate X output narrowed down, the direct voltage of low pass filter output diminished, and become big the time of delay of control voltage control delay cell, and the output of XOR gate X can broaden; When the pulse duration of XOR gate X output broadens, the direct voltage of low pass filter output becomes big, diminish the time of delay of control voltage control delay cell, the pulse duration of the output of XOR gate can narrow down, realized the output pulse width of automatic control XOR gate, the pulse duration that the output of XOR gate X is maintained fixed.
The electric current of constant-current source described here is greater than the electric current that C1 is discharged through R1, if the constant-current source electric current is I
0, when supply voltage is VDD, then require I
0＞2VDD/R1, and R1C1＞2T, T are the cycle of input clock signal.Because the charging current of capacitor C 1 is greater than the discharging current through R1, the voltage at capacitor C 1 two ends constantly rises, when the voltage at electric capacity two ends during greater than the conversion high level of level shifting circuit, level shifting circuit output high level, through output high level index signal behind the Schmidt trigger, the expression clock signal is normal.
In the present embodiment, low pass filter has adopted passive low ventilating filter, also can adopt active low-pass filter.
Level shifting circuit can adopt circuit such as Schmidt trigger, slow phase device, comparator to realize.
Claims (8)
1, a kind of clock signal detection circuit is characterized in that, comprising:
Voltage control delay cell, XOR gate, inverter, low pass filter, PMOS pipe, constant-current source, resistance, electric capacity and a level shifting circuit;
Input clock connects the input end of clock of voltage control delay cell and an input of XOR gate simultaneously, and the output of voltage control delay cell connects another input of XOR gate; The output of XOR gate connects the input of inverter and the input of low pass filter simultaneously, the voltage controling end of the output termination voltage control delay cell of low pass filter; The output of inverter connects the grid of PMOS pipe; The output of the source termination constant-current source of PMOS pipe, an other termination power of constant-current source; The drain terminal of PMOS pipe connects an end of parallel resistor and electric capacity and the input of level shifting circuit simultaneously, an other end ground connection of parallel resistance and electric capacity; The output of level shifting circuit is exactly the output of testing circuit.
2, clock signal detection circuit as claimed in claim 1 is characterized in that:
Described voltage control delay cell specifically comprises four basic voltage control delay cells and a buffer;
Described basic voltage control delay cell comprises two NMOS pipes and a PMOS pipe;
Described buffer is used for the clock of voltage control delay cell output is carried out shaping.
3, clock signal detection circuit as claimed in claim 1 or 2 is characterized in that:
The time of delay of described voltage control delay cell and control voltage are inversely proportional to, and when control voltage was high, time of delay was little, when control voltage is low, become time of delay big;
The maximum delay time of voltage control delay cell and the difference of minimum delay time are less than the cycle of input clock signal.
4, clock signal detection circuit as claimed in claim 1 is characterized in that:
The output pulse width of XOR gate is maintained fixed constant.
5, clock signal detection circuit as claimed in claim 1 is characterized in that:
Described constant-current source comprises two PMOS pipes and a NMOS pipe;
The electric current of described constant-current source is greater than the electric current of the described resistance of process to described capacitor discharge;
The product of described resistance and electric capacity is greater than the cycle of the input clock signal of twice.
6, clock signal detection circuit as claimed in claim 1 is characterized in that:
Described low pass filter has adopted passive low ventilating filter or active low-pass filter.
7, clock signal detection circuit as claimed in claim 1 is characterized in that:
Described low pass filter comprises NMOS pipe, PMOS pipe, resistance and two electric capacity.
8, clock signal detection circuit as claimed in claim 1 is characterized in that:
Described level shifting circuit adopts Schmidt trigger, slow phase device or comparator circuit to realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101168922A CN100568728C (en) | 2005-10-31 | 2005-10-31 | A kind of clock signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101168922A CN100568728C (en) | 2005-10-31 | 2005-10-31 | A kind of clock signal detection circuit |
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| CN1960180A CN1960180A (en) | 2007-05-09 |
| CN100568728C true CN100568728C (en) | 2009-12-09 |
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| CNB2005101168922A Active CN100568728C (en) | 2005-10-31 | 2005-10-31 | A kind of clock signal detection circuit |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387901B (en) * | 2007-09-10 | 2010-11-24 | 英业达股份有限公司 | Multi-voltage supply apparatus for considering power starting sequence and power supply enabling circuit thereof |
| CN101252405B (en) * | 2008-03-27 | 2012-09-05 | 华为技术有限公司 | Clock detection and auto switching method and system |
| CN101534108B (en) * | 2009-04-14 | 2011-05-11 | 清华大学 | Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration |
| CN102169140B (en) * | 2010-12-27 | 2013-04-24 | 上海贝岭股份有限公司 | Clock frequency detection circuit |
| CN103034148B (en) * | 2011-10-10 | 2014-10-22 | 联创汽车电子有限公司 | Time relay circuit |
| CN102565529B (en) * | 2011-12-21 | 2014-02-12 | 深圳国微技术有限公司 | Low-power-consumption clock frequency detection circuit |
| CN106407486A (en) * | 2015-07-27 | 2017-02-15 | 深圳市中兴微电子技术有限公司 | Process deviation detection circuit and method |
| CN105869386B (en) * | 2016-06-15 | 2019-05-24 | 湖南工业大学 | Locomotive speed sensor device signal filtering equipment |
| KR20180041319A (en) * | 2016-10-14 | 2018-04-24 | 엘에스산전 주식회사 | Apparatus for recognizing pulse signal |
| CN107425822B (en) * | 2017-05-09 | 2024-03-26 | 广州慧智微电子股份有限公司 | Filtering circuit and method |
| CN109412581A (en) * | 2017-08-18 | 2019-03-01 | 杭州晶华微电子有限公司 | A kind of clock failure of oscillation detection circuit |
| CN113364432B (en) * | 2021-04-26 | 2023-06-09 | 西安交通大学 | Reference clock signal loss detection circuit |
| CN117200752B (en) * | 2023-09-18 | 2024-04-05 | 江苏帝奥微电子股份有限公司 | Synchronous high-frequency square wave signal circuit |
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Application publication date: 20070509 Assignee: SANECHIPS TECHNOLOGY Co.,Ltd. Assignor: ZTE Corp. Contract record no.: 2015440020319 Denomination of invention: Clock signal detection circuit Granted publication date: 20091209 License type: Common License Record date: 20151123 |
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Effective date of registration: 20221121 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Department of law, Zhongxing building, South hi tech Industrial Park, Nanshan District hi tech Industrial Park, Guangdong, Shenzhen Patentee before: ZTE Corp. |