CN102324928B - Frequency calibration circuit of active RC (Resistor-Capacitor) filter - Google Patents
Frequency calibration circuit of active RC (Resistor-Capacitor) filter Download PDFInfo
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- CN102324928B CN102324928B CN 201110133841 CN201110133841A CN102324928B CN 102324928 B CN102324928 B CN 102324928B CN 201110133841 CN201110133841 CN 201110133841 CN 201110133841 A CN201110133841 A CN 201110133841A CN 102324928 B CN102324928 B CN 102324928B
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Abstract
The invention discloses a frequency calibration circuit of an active RC (Resistor-Capacitor) filter, comprising a capacitor array charging-discharging circuit module of an analog part, a voltage window comparison circuit module and a capacitor array control signal feedback circuit module of a digital part, wherein a capacitor array in the capacitor array charging-discharging circuit module completely copies a capacitor array in the active RC filter, a voltage obtained through the copying is compared with an expected voltage in the voltage window comparison circuit module, then a signal obtained through voltage comparison is output to the capacitor array control signal feedback circuit module and is processed by the capacitor array control signal feedback circuit module to form feedback with the analog part, so that a control signal of the capacitor array is obtained, and furthermore, the capacitance of the capacitor array in the active RC filter is adjusted to realize the adjustment for frequency response of a main circuit of the active RC filter. The invention has the advantage of overcoming the defect of frequency response of the active RC filter due to influences from a process, a power voltage, a temperature and the like.
Description
Technical field
The present invention relates to a kind of frequency calibration circuit, particularly a kind of frequency calibration circuit of active RC filter.
Background technology
In the existing active RC filter, because electric capacity can cause the drift of the cut-off frequency of active RC filter along with the variation of technique, temperature etc. on the sheet, therefore be necessary the cut-off frequency of active RC filter is calibrated, to obtain needed cut-off frequency.
Summary of the invention
The objective of the invention is to realize a kind of frequency automatic calibration circuit that can be applicable to active RC filter.
In order to realize goal of the invention of the present invention, realize by adopting following technical scheme:
A kind of frequency calibration circuit of active RC filter, the capacitor array charge-discharge circuit module that comprises the simulation part, the capacitor array control signal feedback circuit module of voltage window comparison circuit module and numerical portion, wherein the capacitor array in the capacitor array charge-discharge circuit module copies the capacitor array in the active RC filter fully, it holds the variation of capacitor array appearance value in the value trace active RC filter, and both have identical control signal, the voltage that obtains by capacitor array charge-discharge circuit module, compare with the voltage in the voltage window comparison circuit module of expecting, the signal that again voltage ratio is obtained outputs to capacitor array control signal feedback circuit module, by the processing of numerical portion to voltage comparison signal, divide the formation feedback with simulation part, obtain the control signal of capacitor array, and then remove to adjust the capacitance of the capacitor array in the active RC filter, realize the adjustment to the response of active RC filter main body channel frequency.
Described capacitor array charge-discharge circuit module comprises capacitor array, transmission gate, tail current source It, nmos switch pipe M1 and nmos switch pipe M2, the anode connecting power line of capacitor array wherein, and have appearance value control word S＜3 〉, S＜2, S＜1, S＜0; Tail current source It negativing ending grounding; Nmos switch pipe M1 links to each other with the source electrode of nmos switch pipe M2, and link to each other with the anode of tail current source It, the grid of nmos switch pipe M1 connects the reverse clock SW2_B of clock signal SW2, its connecting power line that drains, the grid of nmos switch pipe M2 connects clock signal SW2, and drain electrode connects the negative terminal Vcap of described capacitor array; The conducting of transmission gate or turn-off by clock signal SW1 with and oppositely clock SW1_B decide, its anode connecting power line, negative terminal connect the negative terminal Vcap of described capacitor array.
Described voltage window comparison circuit module comprises the first comparator C OMP1, the second comparator C OMP2, the first d type flip flop DFF1, the second d type flip flop DFF2, wherein the first comparator C OMP1 has positive input terminal and negative input end, positive input terminal links to each other with the negative terminal Vcap of described capacitor array, and described negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP2 has positive input terminal and negative input end, and positive input terminal links to each other with the negative terminal Vcap of described capacitor array, and described negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF1 has data input pin and input end of clock, and data input pin links to each other with the output of the first comparator C OMP1, and input end of clock is clock signal SW3; The second d type flip flop DFF2 has data input pin and input end of clock, and data input pin links to each other with the output of the second comparator C OMP2, and input end of clock is clock signal SW3.
Described capacitor array control signal feedback circuit module comprises same or door XNOR and digital coding, wherein a same or door XNOR has anode input and negative terminal input, the anode input receives the Q end output signal VH_OUT from the first d type flip flop DFF1, and the negative terminal input receives the Q end output signal VL_OUT from the second d type flip flop DFF2; Digital coding has three input ports, wherein the VIN port receives the Q end output signal VH_OUT from the first d type flip flop DFF1, the LOCK port is connected to output same or door XNOR, SW4 is the clock end, the output S of digital coding part＜3 〉, S＜2, S＜1, S＜0 deliver to the corresponding control word end of capacitor array.
Beneficial effect of the present invention is: overcome the variation of the frequency response that the active RC filter circuit causes owing to the impact of technique, supply voltage and temperature etc., prevented that the drift of cut-off frequency of active RC filter is on the impact of circuit.
Description of drawings
Fig. 1 is the frequency calibration electrical block diagram of active RC filter of the present invention;
Fig. 2 is the frequency calibration circuit clock distribution map of active RC filter of the present invention;
Fig. 3 is the frequency calibration circuit working flow chart of active RC filter of the present invention.
Wherein, the symbol description of Fig. 1 to Fig. 3 is as follows:
1, capacitor array charge-discharge circuit module, 11, capacitor array, 12, transmission gate, 13, nmos switch pipe M1,14, nmos switch pipe M2,15, tail current source It, 2, voltage window comparison circuit module, 21, the first comparator C OMP1, the 22, second comparator C OMP2, the 23, first d type flip flop DFF1,24, the second d type flip flop DFF2,3, capacitor array control signal feedback circuit module, 31, digital coding, 32, with or door XNOR.
Embodiment
As shown in Figure 1, be the frequency calibration electrical block diagram of active RC filter of the present invention.Its structure comprises the capacitor array control signal feedback circuit module 3 of capacitor array charge-discharge circuit module 1, voltage window comparison circuit module 2 and the numerical portion of simulation part.
Described capacitor array charge-discharge circuit module 1 comprises capacitor array 11, transmission gate 12, nmos switch pipe M113, nmos switch pipe M214, tail current source It15, the anode connecting power line of capacitor array 11 wherein, and have appearance value control word S＜3 〉, S＜2, S＜1, S＜0; Tail current source It15 negativing ending grounding; Nmos switch pipe M113 links to each other with the source electrode of nmos switch pipe M214, and link to each other with the anode of tail current source It15, the grid of nmos switch pipe M113 connects the reverse clock SW2_B of clock signal SW2, its connecting power line that drains, the grid of nmos switch pipe M214 connects clock signal SW2, and drain electrode connects the negative terminal Vcap of described capacitor array 11; The conducting of transmission gate 12 or turn-off by clock signal SW1 with and oppositely clock SW1_B decide, its anode connecting power line, negative terminal connect the negative terminal Vcap of described capacitor array 11.
Described voltage window comparison circuit module comprises the first comparator C OMP121, the second comparator C OMP222, the first d type flip flop DFF123, the second d type flip flop DFF224, wherein the first comparator C OMP121 has positive input terminal and negative input end, positive input terminal links to each other with the negative terminal Vcap of described capacitor array 11, and described negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP222 has positive input terminal and negative input end, and positive input terminal links to each other with the negative terminal Vcap of described capacitor array 11, and described negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF123 has data input pin and input end of clock, and data input pin links to each other with the output of the first comparator C OMP121, and input end of clock is clock signal SW3; The second d type flip flop DFF224 has data input pin and input end of clock, and data input pin links to each other with the output of the second comparator C OMP222, and input end of clock is clock signal SW3.
Described capacitor array control signal feedback circuit module 3 comprises same or door XNOR32 and digital coding 31, wherein a same or door XNOR32 has anode input and negative terminal input, the anode input receives the Q end output signal VH_OUT from the first d type flip flop DFF123, and the negative terminal input receives the Q end output signal VL_OUT from the second d type flip flop DFF224; Digital coding 31 has three input ports, wherein the VIN port receives the Q end output signal VH_OUT from the first d type flip flop DFF123, the LOCK port is connected to output same or door XNOR32, SW4 is the clock end, the output S of digital coding 31 parts＜3 〉, S＜2, S＜1, S＜0 deliver to the corresponding control word end of capacitor array 11.
As shown in Figure 2, be the frequency calibration circuit clock distribution map of active RC filter of the present invention.SW1/SW1_B among Fig. 1, SW2/SW2_B, SW3/SW3_B, SW4/SW4_B are one group of clock signal, its phase place situation as shown in Figure 2, their duty ratios separately are respectively: 1/5,2/5,2/5,1/5.Clock SW3 falls behind clock SW2, and delaying time is D1, and clock SW4 falls behind clock SW3, and delaying time is D2.Clock SW1/SW1_B is the replacement clock, and the control transmission gate is moved power supply potential at the magnitude of voltage that SW1=1 in the cycle stores electric capacity.SW2=1 is the charging clock cycle, when SW2=1, nmos switch pipe M2 conducting, the voltage Vcap of capacitor array lower end discharges by M2 and tail current source It, until the SW3=1 clock cycle, at this moment, SW2_B=1, nmos switch pipe M1 conducting, tail current It flows into power line VDDA by M1, capacitor array lower end Vcap then no longer the discharge, and this moment SW1=0, SW1_B=1, the transmission gate cut-off, capacitor array lower end Vcap voltage no longer includes discharge path, and therefore capacitor array lower end Vcap voltage remains unchanged after the SW2=1 cycle ends, and is used for comparing with reference voltage window.The setting of reference voltage window is corresponding with needed capacitor array value, namely in this reference voltage window, and the cut-off frequency value that expression capacitor array integral capacitor value can corresponding active-RC filter.At the SW3 rising edge, d type flip flop gathers the output information of prime comparator, and the output of d type flip flop will be delivered to digital circuit and partly judge processing, finally provide corresponding action.
As shown in Figure 3, be the frequency calibration circuit working flow chart of active RC filter of the present invention.Concrete working condition is as follows, after the SW2=1 cycle ends, when if capacitor array lower end Vcap magnitude of voltage is between reference voltage window VREF_L and the VREF_H, capacitor array can remain unchanged, the capacitor array appearance value of expression this moment can access need active-RC filter cutoff frequency, and the automatic frequency calibration can be finished.And if capacitor array lower end Vcap magnitude of voltage is not between reference voltage window VREF_L and VREF_H the time, numerical portion then needs the output signal according to the simulation part, judge that need to which kind of need to be done to capacitor array adjusts, so that the Vcap magnitude of voltage can remain in the reference voltage window under current flow-route and temperature.
The output VH_OUT of simulation part and VL_OUT warp are same or obtain behind the door the LOCK signal, deliver in the digital module with the VH_OUT signal.Three kinds of situations of the relatively existence of aforementioned Vcap magnitude of voltage and reference voltage window VREF_L and VREF_H, be Vcap＜VREF_L＜VREF_H, VREF_L＜Vcap＜VREF_H, VREF_L＜VREF_H＜Vcap, so that three kinds of situations also can appear in the combination of the value of VH_OUT and LOCK, be VH_OUT=L, LOCK=H; VH_OUT=L, LOCK=L and VH_OUT=H, LOCK=H.Digital module is analyzed the value of VH_OUT and LOCK at the rising edge of clock signal SW4, when LOCK=L, can think that the appearance value of capacitor array this moment can access suitable filter cutoff frequency, be the control word S＜3 of capacitor array 〉, S＜2 〉, S＜1 〉, S＜0〉can keep current state, the automatic frequency calibration of filter is finished.And when LOCK=H, have two kinds of situations, and need to be to the control word S of capacitor array＜3 〉, S＜2 〉, S＜1〉and, S＜0〉adjust.VH_OUT=L means that capacitor array is owing to the impact that is subject to flow-route and temperature drift etc. shows less appearance value, when clock signal SW4 rising edge, the control word S of a capacitor array of increase＜3 〉, S＜2 〉, S＜1 〉, S＜0〉improve its appearance value, through cycle criterion, final Vcap magnitude of voltage enters in the reference voltage window, LOCK=L, can stop to increase S＜3 this moment 〉, S＜2 〉, S＜1 〉, S＜0 〉, the automatic frequency calibration of expression filter this moment is finished.And during another kind of situation VH_OUT=H, mean that capacitor array is owing to the impact that is subject to flow-route and temperature drift etc. shows larger appearance value, when rising edge appears in clock signal SW4, reduce the control word S of a capacitor array＜3 〉, S＜2 〉, S＜1 〉, S＜0〉reduce its appearance value, through cycle criterion, final Vcap magnitude of voltage enters in the reference voltage window, LOCK=L, can stop to reduce S＜3 this moment 〉, S＜2 〉, S＜1 〉, S＜0 〉, the automatic frequency calibration of expression filter this moment is finished.
Claims (3)
1. the frequency calibration circuit of an active RC filter, the capacitor array charge-discharge circuit module (1) that comprises the simulation part, the capacitor array control signal feedback circuit module (3) of voltage window comparison circuit module (2) and numerical portion, wherein the capacitor array (11) in the capacitor array charge-discharge circuit module (1) copies the capacitor array in the active RC filter fully, it holds the variation of capacitor array appearance value in the value trace active RC filter, and both have identical control signal, the voltage that obtains by capacitor array charge-discharge circuit module (1), compare with the voltage in the voltage window comparison circuit module (2) of expecting, the signal that again voltage ratio is obtained outputs to capacitor array control signal feedback circuit module (3), capacitor array control signal feedback circuit module (3) by numerical portion is to the processing of voltage comparison signal, form feedback with the capacitor array charge-discharge circuit module (1) of simulation part, obtain the control signal of capacitor array (11), and then remove to adjust the capacitance of the capacitor array in the active RC filter, realization is to the adjustment of active RC filter main body channel frequency response, it is characterized in that: described capacitor array charge-discharge circuit module (1) comprises capacitor array (11), transmission gate (12), nmos switch pipe M1(13), nmos switch pipe M2(14), tail current source It(15), the anode connecting power line of capacitor array (11) wherein, and have appearance value control word S＜3 〉, S＜2 〉, S＜1 〉, S＜0 〉; Tail current source It(15) negativing ending grounding; Nmos switch pipe M1(13) with nmos switch pipe M2(14) source electrode link to each other, and with tail current source It(15) anode link to each other, nmos switch pipe M1(13) grid connects the reverse clock SW2_B of clock signal SW2, its connecting power line that drains, nmos switch pipe M2(14) grid connects clock signal SW2, and drain electrode connects the negative terminal Vcap of described capacitor array (11); The conducting of transmission gate (12) or turn-off by clock signal SW1 with and oppositely clock SW1_B decide, its anode connecting power line, negative terminal connect the negative terminal Vcap of described capacitor array (11).
2. the frequency calibration circuit of active RC filter as claimed in claim 1, it is characterized in that: described voltage window comparison circuit module (2) comprises the first comparator C OMP1(21), the second comparator C OMP2(22), the first d type flip flop DFF1(23), the second d type flip flop DFF2(24), the first comparator C OMP1(21 wherein) has positive input terminal and negative input end, positive input terminal links to each other with the negative terminal Vcap of described capacitor array (11), and described negative input end links to each other with reference voltage VREF_H electricity; The second comparator C OMP2(22) have positive input terminal and negative input end, positive input terminal links to each other with the negative terminal Vcap of described capacitor array (11), and described negative input end links to each other with reference voltage VREF_L electricity; The first d type flip flop DFF1(23) have data input pin and input end of clock, data input pin and the first comparator C OMP1(21) output link to each other, input end of clock is clock signal SW3; The second d type flip flop DFF2(24) have data input pin and input end of clock, data input pin and the second comparator C OMP2(22) output link to each other, input end of clock is clock signal SW3.
3. the frequency calibration circuit of active RC filter as claimed in claim 1, it is characterized in that: described capacitor array control signal feedback circuit module (3) comprises same or door XNOR(32) and digital coding (31), wherein with or door XNOR(32) have anode input and negative terminal is inputted, anode input receives from the first d type flip flop DFF1(23) Q end output signal VH_OUT, the negative terminal input receives from the second d type flip flop DFF2(24) Q end output signal VL_OUT; Digital coding (31) has three input ports, wherein the VIN port receives from the first d type flip flop DFF1(23) Q end output signal VH_OUT, the LOCK port be connected to or the door XNOR(32) output, SW4 is the clock end, the output S of digital coding (31) part＜3 〉, S＜2, S＜1, S＜0 deliver to the corresponding control word end of capacitor array (11).
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| CN 201110133841 CN102324928B (en) | 2011-05-23 | 2011-05-23 | Frequency calibration circuit of active RC (Resistor-Capacitor) filter |
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| CN 201110133841 CN102324928B (en) | 2011-05-23 | 2011-05-23 | Frequency calibration circuit of active RC (Resistor-Capacitor) filter |
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| CN102324928A CN102324928A (en) | 2012-01-18 |
| CN102324928B true CN102324928B (en) | 2013-04-10 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102916679B (en) * | 2012-10-19 | 2016-03-16 | 钜泉光电科技(上海)股份有限公司 | Circuit and the control method thereof of accurate low-frequency clock signal are provided |
| CN102983836B (en) * | 2012-11-27 | 2015-11-18 | 重庆西南集成电路设计有限责任公司 | Active RC filter automatic frequency tuning circuit |
| CN103078630B (en) * | 2012-12-20 | 2015-09-30 | 香港应用科技研究院有限公司 | For the bandwidth calibration of filter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239654B1 (en) * | 1999-05-28 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | Filter circuit |
| CN1551501A (en) * | 2003-05-12 | 2004-12-01 | 因芬尼昂技术股份公司 | Apparatus and method for calibrating resistance/ capacitor filter circuit |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN202068398U (en) * | 2011-05-23 | 2011-12-07 | 中科芯集成电路股份有限公司 | Frequency calibration circuit of active RC filter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7050781B2 (en) * | 2002-05-16 | 2006-05-23 | Intel Corporation | Self-calibrating tunable filter |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239654B1 (en) * | 1999-05-28 | 2001-05-29 | Mitsubishi Denki Kabushiki Kaisha | Filter circuit |
| CN1551501A (en) * | 2003-05-12 | 2004-12-01 | 因芬尼昂技术股份公司 | Apparatus and method for calibrating resistance/ capacitor filter circuit |
| CN101656519A (en) * | 2009-08-13 | 2010-02-24 | 捷顶微电子（上海）有限公司 | Calibration circuit of RC filter and method |
| CN202068398U (en) * | 2011-05-23 | 2011-12-07 | 中科芯集成电路股份有限公司 | Frequency calibration circuit of active RC filter |
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Address after: 2 / F, building 9, plot 04-6 (100 didui Road), Liyuan Development Zone, Binhu District, Wuxi City, Jiangsu Province Patentee after: ZHONGKEXIN INTEGRATED CIRCUIT Co.,Ltd. Address before: 214072 Jiangsu province Wuxi City Liyuan Development Zone, Road No. 100 building 9 layer 2 Patentee before: CHINA KEY SYSTEM & INTEGRATED CIRCUIT Co.,Ltd. |