CN103066989A - Single power electric level shift circuit with digital filtering function - Google Patents
Single power electric level shift circuit with digital filtering function Download PDFInfo
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- CN103066989A CN103066989A CN2012105591437A CN201210559143A CN103066989A CN 103066989 A CN103066989 A CN 103066989A CN 2012105591437 A CN2012105591437 A CN 2012105591437A CN 201210559143 A CN201210559143 A CN 201210559143A CN 103066989 A CN103066989 A CN 103066989A
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Abstract
The invention discloses a single power electric level shift circuit with a digital filtering function. The single power electric level shift circuit with the digital filtering function mainly resolves the problems that an existing electric level shift circuit is too large in static power consumption, fluctuating in output voltage and difficult in multi-power-signal transmission. The electric level shift circuit comprises source drain interchange circuits (1), a single power supply circuit (2), a schmitt trigger (3), an electric level shifter (4) and a digital filter (5). The source drain interchange circuits (1) output voltage signal V1 and are respectively connected on the schmitt trigger (3) and the electric level shifter (4). The single power supply circuit (2) provides voltage control signal V4 for the schmitt trigger (3). The schmitt trigger (3) provides voltage control signal V2 for the electric level shifter (4). The electric level shifter (4) provides voltage signal V3 for the digital filter (5). The digital filter (5) outputs voltage signal V OUT. According to the single power electric level shift circuit with the digital filtering function, the stability of output voltage is improved, the static power consumption is reduced, the accuracy of electric level transformation is improved and sharp plus interference waves are removed by filtering. The single power electric level shift circuit with the digital filtering function can be used for an analogue integrated circuit.
Description
Technical field
The invention belongs to the electronic circuit technology field, particularly contain the single supply level shift circuit of digital filtering function, can be used for analog integrated circuit.
Background technology
Along with the rise of smart mobile phone, nearly body detects, light detecting sensor chip becomes instantly study hotspot.In order to strengthen its versatility, the sensors with auxiliary electrode were chip is compatible I all
2The C agreement, the operating voltage range of chip is 2.15V～3.6V usually, I
2The operating voltage range of C interface is 1.7V～3.6V, and level shift circuit becomes one of requisite module.
In the multichip system design, the chip chamber supply power voltage is different, and required power line is long, and the obstruction between signal is serious, and level shift circuit becomes one of requisite module.
Traditional level shift circuit shown in Figure 1 comprises dual power supply module and level shift circuit.The supply power voltage of not gate I1 is V
L, the supply power voltage of level shift circuit is V
HNMOS pipe MN1, MN2 and PMOS pipe MP1, MP2 consist of level shift circuit.When input voltage vin is low level, NMOS pipe MN2 conducting, NMOS pipe MN1 cut-off, output voltage V a is low level, PMOS pipe MP1 conducting, output voltage V b is high level, PMOS pipe MP2 cut-off; When input voltage vin is high level, NMOS pipe MN2 cut-off, NMOS pipe MN1 conducting, output voltage V b is low level, PMOS pipe MP2 conducting, output voltage V a is high level, PMOS pipe MP1 cut-off.Level shift circuit is low level voltage V
LConvert high level voltage V to
H
Above-mentioned duplicate supply level shift circuit has increased quiescent dissipation, has increased design complexities and the cost of chip, makes signal transmission difficulty, and there is fluctuation in output voltage.
Summary of the invention
The object of the invention is to for the deficiencies in the prior art, a kind of single supply level shift circuit that contains the digital filtering function is provided, to realize I
2The C interface operating voltage is eliminated the fluctuation of output voltage to the conversion of chip internal operating voltage, filtering spike disturbing wave, the reliability and stability of raising circuit.
For achieving the above object, the present invention includes level shifter 4, it is characterized in that: the first input end of level shifter 4 is connected with Schmidt trigger 3, is used to level shifter 4 that voltage control signal V2 is provided; The second input of level shifter 4 is connected with source-drain electrode interchange circuit 1, is used to level shifter 4 that voltage signal V1 is provided; The output of level shifter 4 is connected with digital filter 5, and this digital filter 5 is used for output voltage signal V
OUTThe first input end of Schmidt trigger 3 is connected with single power supply circuit 2, is used to Schmidt trigger 3 that voltage signal V4 is provided; The second input of Schmidt trigger 3 is connected with source-drain electrode interchange circuit 1, is used to Schmidt trigger 3 that voltage signal V1 is provided.
The above-mentioned source-drain electrode interchange circuit 1 that contains the single supply level shift circuit of digital filtering function, M20 consists of by the 20 NMOS pipe; The grid of the 20 NMOS pipe M20 and the supply voltage V of its place chip
DLink to each other, its source electrode and drain electrode have the exchange function, respectively as input B and the output C of source-drain electrode interchange circuit 1, and the voltage signal V that this input B and its place chip provide
INLink to each other, this output C links to each other with level shifter 4 with Schmidt trigger 3 respectively, output voltage signal V1.
The above-mentioned single power supply circuit 2 that contains the single supply level shift circuit of digital filtering function, M1 consists of by PMOS pipe; The source electrode of the one PMOS pipe M1 and the supply voltage V of its place chip
DLink to each other, its grid links to each other with drain electrode, and as the output G of single power supply circuit 2, this output G links to each other with Schmidt trigger 3, output voltage signal V4.
The above-mentioned Schmidt trigger 3 that contains the single supply level shift circuit of digital filtering function, be provided with two inputs and an output, its first input end D links to each other with the voltage signal V1 of source-drain electrode interchange circuit 1 input, its second input E links to each other with the voltage signal V4 of single power supply circuit 2 inputs, its output F links to each other with level shifter 4, output voltage control signal V2.
The above-mentioned digital filter 5 that contains the single supply level shift circuit of digital filtering function, comprise 4 PMOS pipes, 4 NMOS pipes, 4 inverters, i.e. the 6th PMOS pipe M6, the 7th PMOS pipe M7, the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 8th NMOS pipe M8, the 9th NMOS pipe M9, the 12 NMOS pipe M12, the 13 NMOS pipe M13, the first inverter I1, the second inverter I2, the 3rd inverter I3, the 4th inverter I4, resistance R 1 and capacitor C 1;
Described the first inverter I1, its input link to each other with the voltage control signal V3 of level shift circuit 4 inputs as the input L of digital filter 5; Its output links to each other with the input of the second inverter I2;
The output of described the second inverter I2 links to each other with an end of resistance R 1;
The other end of described resistance R 1 links to each other with the drain electrode of the 7th PMOS pipe M7;
Described capacitor C 1 is connected across between the drain electrode and ground of the 7th PMOS pipe M7;
Described the 7th PMOS pipe M7 and the 8th NMOS pipe M8, its drain electrode links to each other, and links to each other with the grid of the 11 PMOS pipe M11; Its grid links to each other, and links to each other with the output of the first inverter I1; The source electrode of the 7th PMOS pipe M7 links to each other with the drain electrode of the 6th PMOS pipe M6; The source electrode of the 8th NMOS pipe M8 links to each other with the drain electrode of the 9th NMOS pipe M9;
Described the 6th PMOS pipe M6 and the 9th NMOS pipe M9, its grid links to each other, and links to each other with the input of the 3rd inverter I3; The source electrode of the 6th PMOS pipe M6 and the supply voltage V of its place chip
DLink to each other; The source electrode of the 9th NMOS pipe M9 is connected to the ground;
The grid of described the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 12 NMOS pipe M12 and the 13 NMOS pipe M13 links to each other respectively, and links to each other with the drain electrode of the 7th PMOS pipe M7; The source electrode of the tenth PMOS pipe M10 and the supply voltage V of its place chip
DLink to each other; The drain electrode of the tenth PMOS pipe M10 links to each other with the source electrode of the 11 PMOS pipe M11; The drain electrode of the 11 PMOS pipe M11 links to each other with the drain electrode of the 12 NMOS pipe M12, and links to each other with the input of the 3rd inverter I3; The source electrode of the 12 NMOS pipe M12 links to each other with the drain electrode of the 13 NMOS pipe M13; The source electrode of the 13 NMOS pipe M13 is connected to the ground;
The output of described the 3rd inverter I3 links to each other with the input of the 4th inverter I4;
The output of described the 4th inverter I4 is as the output M of digital filter (5), output voltage signal V
OUT
The present invention compared with prior art has following advantage:
1, the present invention has reduced power supply power consumption owing to adopt the single power supply circuit, has simplified power supply routing problem in the multi-chip design.
2, the present invention has reduced the output voltage unsteadiness that causes because of input voltage fluctuation owing to adopt Schmidt trigger.
3, the present invention is owing to adopt the source-drain electrode interchange circuit, realized that displacement from the low level to the supply voltage and supply voltage to the displacement of low level voltage, have increased the performance of level shift.
4, the present invention is owing to adopt digital filter, filtering I
2The C cabling is long and at I
2The spike that the C input produces has guaranteed the stability of output level.
Description of drawings
Fig. 1 is existing level shift circuit schematic diagram;
Fig. 2 is the structured flowchart of level shift circuit of the present invention;
Fig. 3 is the circuit theory diagrams of level shift circuit of the present invention.
Embodiment
The invention will be further described referring to accompanying drawing and embodiment.
With reference to figure 2, the single supply level shift circuit that contains the digital filtering function of the present invention comprises: source-drain electrode interchange circuit 1, single power supply circuit 2, Schmidt trigger 3, level shifter 4 and digital filter 5; The voltage signal V that the input B of this source-drain electrode interchange circuit 1 and its place chip provide
INLink to each other, the output C of this source-drain electrode interchange circuit 1 links to each other with level shifter 4 with Schmidt trigger 3 respectively, output voltage signal V1; The output G of this single power supply circuit 2 links to each other with Schmidt trigger 3, output voltage signal V4; The first input end D of this Schmidt trigger 3 links to each other with the voltage signal V1 of source-drain electrode interchange circuit 1 input, the second input E of this Schmidt trigger 3 links to each other with the voltage signal V4 of single power supply circuit 2 inputs, the output F of this Schmidt trigger 3 links to each other with level shifter 4, output voltage control signal V2; The output J of this level shifter 4 links to each other with digital filter 5, output voltage control signal V3; The output M output voltage signal V of this digital filter 5
OUT
With reference to figure 3, circuit structure of the present invention is as follows:
Described source-drain electrode interchange circuit 1, M20 consists of by the 20 NMOS pipe; The grid of the 20 NMOS pipe M20 and the supply voltage V of its place chip
DLink to each other, its source electrode and drain electrode have the exchange function, respectively as input B and the output C of source-drain electrode interchange circuit 1, and the voltage signal V that this input B and its place chip provide
INThe voltage signal V that provides according to its place chip is provided
INSupply voltage V with its place chip
DDifference size, determine the source-drain electrode of the 20 NMOS pipe M20, this output C output voltage signal V1 is connected respectively to Schmidt trigger 3 and level shifter 4.
Described single power supply circuit 2, M1 consists of by PMOS pipe; The source electrode of the one PMOS pipe M1 and the supply voltage V of its place chip
DLink to each other, its grid links to each other with drain electrode, and as the output G of single power supply circuit 2, this output G links to each other with Schmidt trigger 3, output voltage signal V4.Single power supply circuit 2 is with the supply voltage V of its place chip
DM1 reduces a threshold voltage V by PMOS pipe
TH, realize the single power supply function.
Described Schmidt trigger 3, include but not limited to 3 PMOS pipes, 3 NMOS pipes, namely the 17 PMOS pipe M17, the 18 PMOS pipe M18, the 19 PMOS pipe M19, the 14 NMOS pipe M14, the 15 NMOS manage M15 and the 16 NMOS pipe M16, wherein:
The grid of the 17 PMOS pipe M17, the 18 PMOS pipe M18, the 14 NMOS pipe M14 and the 15 NMOS pipe M15 links to each other respectively, as the first input end D of Schmidt trigger 3, and links to each other with voltage signal V1 that source-drain electrode interchange circuit 1 is inputted;
The drain electrode of the drain electrode of the 18 PMOS pipe M18 and the 15 NMOS pipe M15 links to each other, and as the output F of Schmidt trigger 3, and links to each other output voltage control signal V2 with level shifter 4;
The 17 PMOS manages the source electrode of M17 as the second input E of Schmidt trigger 3, and links to each other with the voltage signal V4 of single power supply circuit 2 inputs;
When voltage signal V1 is zero level, the 14 NMOS pipe M14, the 15 NMOS pipe M15 and all not conductings of the 16 NMOS pipe M16; The 15 NMOS pipe M15 and the 16 NMOS pipe M16 form feedback network, are used for controlling forward trigger voltage V
+Value; Along with the increase of voltage signal V1, the poor V of drain-source voltage of the 14 NMOS pipe M14
DS14Reduce gradually, be increased to gradually the poor V of drain-source voltage of the 14 NMOS pipe M14 as voltage signal V1
DS14The poor V of gate source voltage with the 15 NMOS pipe M15
GS15During sum, i.e. V1=V
DS14+ V
GS15, output voltage signal V2 is low level; In like manner, the 18 NMOS pipe M18 and the 19 NMOS pipe M19 consist of feedback network, are used for controlling reverse trigger voltage V
-Value, be reduced to gradually the poor V of drain-source voltage of voltage signal V4 and the 18 NMOS pipe M18 from voltage signal V4 as voltage signal V1
DS18The poor V of gate source voltage with the 19 NMOS pipe M19
GS19Difference the time, i.e. V1=V4-V
DS18-V
DS19The time, output voltage signal V2 is high level.
Described digital filter 5, include but not limited to 4 PMOS pipes, 4 NMOS pipes, 4 inverters, namely the 6th PMOS pipe M6, the 7th PMOS pipe M7, the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 8th NMOS manage M8, the 9th NMOS pipe M9, the 12 NMOS pipe M12, the 13 NMOS pipe M13, the first inverter I1, the second inverter I2, the 3rd inverter I3, the 4th inverter I4, resistance R 1 and capacitor C 1, wherein:
The first inverter I1, its input link to each other with the voltage control signal V3 of level shift circuit 4 inputs as the input L of digital filter 5; Its output links to each other with the input of the second inverter I2; High-low level according to voltage control signal V3 decides output voltage V
OUTHigh-low level, when voltage control signal V3 is high level, the 6th PMOS pipe M6 and the 7th PMOS pipe M7 conducting, capacitor C 1 is in charged state, output voltage V
OUTBe low level; Otherwise, when voltage control signal V3 is low level, the 8th NMOS pipe M8 and the 9th NMOS pipe M9 conducting, capacitor C 1 is in discharge condition, output voltage V
OUTBe high level;
The output of the second inverter I2 links to each other with an end of resistance R 1;
The other end of resistance R 1 links to each other with the drain electrode of the 7th PMOS pipe M7;
The drain electrode of the 7th PMOS pipe M7 links to each other with the drain electrode of the 8th NMOS pipe M8, and links to each other with the grid of the 11 PMOS pipe M11; The grid of the 7th PMOS pipe M7 links to each other with the grid of the 8th NMOS pipe M8, and is connected to the output of the first inverter I1; The source electrode of the 7th PMOS pipe M7 links to each other with the drain electrode of the 6th PMOS pipe M6; The source electrode of the 8th NMOS pipe M8 links to each other with the drain electrode of the 9th NMOS pipe M9;
The grid of the 6th PMOS pipe M6 links to each other with the grid of the 9th NMOS pipe M9, and is connected to the input of the 3rd inverter I3; The source electrode of the 6th PMOS pipe M6 and the supply voltage V of its place chip
DLink to each other; The source electrode of the 9th NMOS pipe M9 is connected to the ground;
The grid of the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 12 NMOS pipe M12 and the 13 NMOS pipe M13 links to each other respectively, and links to each other with the drain electrode of the 7th PMOS pipe M7, consists of the charging and discharging circuit of digital filter 5; The source electrode of the tenth PMOS pipe M10 and the supply voltage V of its place chip
DLink to each other; The drain electrode of the tenth PMOS pipe M10 links to each other with the source electrode of the 11 PMOS pipe M11; The drain electrode of the 11 PMOS pipe M11 links to each other with the drain electrode of the 12 NMOS pipe M12, and link to each other with the input of the 3rd inverter I3, this structure plays delayed action in digital filter 5, output end voltage is discharged and recharged in the time in the maximum of defined remain unchanged; The source electrode of the 12 NMOS pipe M12 links to each other with the drain electrode of the 13 NMOS pipe M13; The source electrode of the 13 NMOS pipe M13 is connected to the ground;
The output of the 3rd inverter I3 links to each other with the input of the 4th inverter I4;
The output of the 4th inverter I4 is as the output M of digital filter 5, output voltage signal V
OUT
Below only be a best specific embodiment of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to circuit, but all at the row of protection of the present invention.
Specific works principle of the present invention is as follows:
Supply voltage V when its place chip
DThe voltage signal V that provides with its place chip
INDifference greater than threshold voltage V
THThe time, the voltage signal V that its place chip of the 20 NMOS pipe M20 drain terminal voltage follow in the source-drain electrode interchange circuit 1 provides
INVariation and change; Supply voltage V when its place chip
DThe voltage signal V that provides with its place chip
INDifference less than threshold voltage V
THThe time, source electrode and the drain electrode of the 20 NMOS pipe M20 are exchanged, and the source voltage terminal of the 20 NMOS pipe M20 is V
D-V
THThis moment, the 20 NMOS managed the source of M20 as the output C of source-drain electrode interchange circuit 1, this output C links to each other with level shifter 4 with Schmidt trigger 3 respectively, thereby realized that displacement from the low level to the supply voltage and supply voltage to the displacement of low level voltage, have improved the performance of level shift.Single power supply circuit 2 is with the supply voltage V of its place chip
DReduce a threshold voltage V
TH, i.e. output voltage signal V4=V
D-V
TH, and output be connected to Schmidt trigger 3, realized the single power supply function.Feedback network the 15 NMOS pipe M15 and the 16 NMOS pipe M16 control forward trigger voltage V in the Schmidt trigger 3
+Value; When voltage signal V1 is low level, the 14 NMOS pipe M14, the 15 NMOS pipe M15 and all not conductings of the 16 NMOS pipe M16; When voltage signal V1 is the threshold voltage V that the 14 NMOS manages M14
THThe time, the 14 NMOS pipe M14 begins conducting; If the 15 NMOS pipe M15 conducting, voltage signal V1 need equal the gate source voltage sum of drain-source voltage and the 15 NMOS pipe M15 of the 14 NMOS pipe M14, i.e. voltage signal V1=V
DS14+ V
GS15, this moment, voltage signal V2 was low level; In like manner, feedback network the 18 PMOS pipe M18 and the 19 PMOS pipe M19 control reverse trigger voltage V
-Value, if the 18 PMOS pipe M18 and the equal conducting of the 19 PMOS pipe M19, then voltage signal V1 is required to be the poor V of drain-source voltage that voltage signal V4 and the 18 NMOS manage M18
DS18The poor V of gate source voltage with the 19 NMOS pipe M19
GS19Poor, i.e. V1=V4-V
DS18-V
DS19, this moment, voltage control signal V2 was high level; The voltage control signal V2 of Schmidt trigger 3 output is the voltage signal with upset amount of hysteresis Δ V, and output is connected to level shifter 4, has reduced the output voltage unsteadiness that causes because of input voltage fluctuation.Level shifter 4 is to convert voltage control signal V2 to voltage control signal V3, and output is connected to digital filter 5.When voltage control signal V3 is high level, the 6th PMOS pipe M6 in the digital filter 5 and the 7th PMOS pipe M7 conducting, capacitor C 1 is in charged state, at this moment output voltage signal V
OUTBe low level; When voltage control signal V3 becomes low level from high level, the 8th NMOS pipe M8 conducting, the first inverter I1 exports high level, when voltage on the capacitor C 1 reaches the turnover voltage of the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 12 NMOS pipe M12 and the 13 NMOS pipe M13, the input terminal voltage of the 3rd inverter I3 becomes high level by low level, thereby make the 9th NMOS pipe M9 conducting, make capacitor C 1 be in discharge condition, output voltage V
OUTBecome high level by low level; If voltage control signal V3 is that low level time is shorter, output voltage V
OUTLevel does not change; In like manner, when voltage control signal V3 was low level, the input terminal voltage of the 3rd inverter I3 was high level, and the voltage on the capacitor C 1 is low level, output voltage V
OUTEnd is high level; When voltage control signal V3 becomes high level by low level, the 7th PMOS pipe M7 conducting, capacitor C 1 is by resistance R 1 and the second inverter I2 discharge, when if voltage reaches the turnover voltage of the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 12 NMOS pipe M12 and the 13 NMOS pipe M13 on the capacitor C 1, the input terminal voltage of the 3rd inverter I3 becomes low level from high level, the 6th PMOS pipe M6 conducting, the voltage perseverance is low level on the capacitor C 1, output voltage V
OUTBecome low level by high level; If voltage control signal V3 is that high level time is shorter, output voltage V
OUTMay not overturn; The big or small influence time constant τ of resistance R 1 and capacitor C 1, but and then determine the maximum sharpness pulse duration of the time that discharges and recharges and filtering, realize the stability of output voltage.
Below only be a preferred example of the present invention, do not consist of any limitation of the invention, obviously under design of the present invention, can carry out different changes and improvement to its circuit, but these are all at the row of protection of the present invention.
Claims (5)
1. single supply level shift circuit that contains the digital filtering function, comprise level shifter (4), it is characterized in that: the first input end of level shifter (4) is connected with Schmidt trigger (3), is used to level shifter (4) that voltage control signal V2 is provided; The second input of level shifter (4) is connected with source-drain electrode interchange circuit (1), is used to level shifter (4) that voltage signal V1 is provided; The output of level shifter (4) is connected with digital filter (5), and this digital filter (5) is used for output voltage signal V
OUTThe first input end of Schmidt trigger (3) is connected with single power supply circuit (2), is used to Schmidt trigger (3) that voltage signal V4 is provided; The second input of Schmidt trigger (3) is connected with source-drain electrode interchange circuit (1), is used to Schmidt trigger (3) that voltage signal V1 is provided.
2. the single supply level shift circuit that contains the digital filtering function according to claim 1 is characterized in that source-drain electrode interchange circuit (1), and M20 consists of by the 20 NMOS pipe; The grid of the 20 NMOS pipe M20 and the supply voltage V of its place chip
DLink to each other, its source electrode and drain electrode have the exchange function, respectively as input B and the output C of source-drain electrode interchange circuit (1), and the voltage signal V that this input B and its place chip provide
INLink to each other, this output C links to each other output voltage signal V1 with Schmidt trigger (3) with level shifter (4) respectively.
3. the single supply level shift circuit that contains the digital filtering function according to claim 1 is characterized in that single power supply circuit (2), and M1 consists of by PMOS pipe; The source electrode of the one PMOS pipe M1 and the supply voltage V of its place chip
DLink to each other, its grid links to each other with drain electrode, and as the output G of single power supply circuit (2), this output G links to each other output voltage signal V4 with Schmidt trigger (3).
4. the single supply level shift circuit that contains the digital filtering function according to claim 1, it is characterized in that Schmidt trigger (3), be provided with two inputs and an output, its first input end D links to each other with the voltage signal V1 of source-drain electrode interchange circuit (1) input, its second input E links to each other with the voltage signal V4 of single power supply circuit (2) input, its output F links to each other output voltage control signal V2 with level shifter (4).
5. the single supply level shift circuit that contains the digital filtering function according to claim 1, it is characterized in that digital filter (5), comprise 4 PMOS pipes, 4 NMOS pipes, 4 inverters, i.e. the 6th PMOS pipe M6, the 7th PMOS pipe M7, the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 8th NMOS pipe M8, the 9th NMOS pipe M9, the 12 NMOS pipe M12, the 13 NMOS pipe M13, the first inverter I1, the second inverter I2, the 3rd inverter I3, the 4th inverter I4, resistance R 1 and capacitor C 1;
Described the first inverter I1, its input link to each other with the voltage control signal V3 of level shift circuit (4) input as the input L of digital filter (5); Its output links to each other with the input of the second inverter I2;
The output of described the second inverter I2 links to each other with an end of resistance R 1;
The other end of described resistance R 1 links to each other with the drain electrode of the 7th PMOS pipe M7;
Described capacitor C 1 is connected across between the drain electrode and ground of the 7th PMOS pipe M7;
Described the 7th PMOS pipe M7 and the 8th NMOS pipe M8, its drain electrode links to each other, and links to each other with the grid of the 11 PMOS pipe M11; Its grid links to each other, and links to each other with the output of the first inverter I1; The source electrode of the 7th PMOS pipe M7 links to each other with the drain electrode of the 6th PMOS pipe M6; The source electrode of the 8th NMOS pipe M8 links to each other with the drain electrode of the 9th NMOS pipe M9;
Described the 6th PMOS pipe M6 and the 9th NMOS pipe M9, its grid links to each other, and links to each other with the input of the 3rd inverter I3; The source electrode of the 6th PMOS pipe M6 and the supply voltage V of its place chip
DLink to each other; The source electrode of the 9th NMOS pipe M9 is connected to the ground;
The grid of described the tenth PMOS pipe M10, the 11 PMOS pipe M11, the 12 NMOS pipe M12 and the 13 NMOS pipe M13 links to each other respectively, and links to each other with the drain electrode of the 7th PMOS pipe M7; The source electrode of the tenth PMOS pipe M10 and the supply voltage V of its place chip
DLink to each other; The drain electrode of the tenth PMOS pipe M10 links to each other with the source electrode of the 11 PMOS pipe M11; The drain electrode of the 11 PMOS pipe M11 links to each other with the drain electrode of the 12 NMOS pipe M12, and links to each other with the input of the 3rd inverter I3; The source electrode of the 12 NMOS pipe M12 links to each other with the drain electrode of the 13 NMOS pipe M13; The source electrode of the 13 NMOS pipe M13 is connected to the ground;
The output of described the 3rd inverter I3 links to each other with the input of the 4th inverter I4;
The output of described the 4th inverter I4 is as the output M of digital filter (5), output voltage signal V
OUT
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| CN107508590A (en) * | 2017-06-28 | 2017-12-22 | 西安电子科技大学 | Level shift circuit |
| CN107528580A (en) * | 2017-09-22 | 2017-12-29 | 上海安其威微电子科技有限公司 | Level shifting circuit |
| CN108322210A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of level shifting circuit |
| CN110545092A (en) * | 2018-05-28 | 2019-12-06 | 深圳市汇春科技股份有限公司 | schmitt trigger and control method thereof |
| CN110995245A (en) * | 2019-12-27 | 2020-04-10 | 成都九芯微科技有限公司 | Input circuit |
| CN111342816A (en) * | 2020-03-30 | 2020-06-26 | 潍柴动力股份有限公司 | Signal filtering method, device, system and readable medium |
| CN113946882A (en) * | 2021-10-20 | 2022-01-18 | 深圳大学 | Schmitt trigger-based ultralow-power-consumption weak physical unclonable function circuit |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108322210A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of level shifting circuit |
| CN107508590A (en) * | 2017-06-28 | 2017-12-22 | 西安电子科技大学 | Level shift circuit |
| CN107528580A (en) * | 2017-09-22 | 2017-12-29 | 上海安其威微电子科技有限公司 | Level shifting circuit |
| CN107528580B (en) * | 2017-09-22 | 2020-09-08 | 上海安其威微电子科技有限公司 | Level conversion circuit |
| CN110545092A (en) * | 2018-05-28 | 2019-12-06 | 深圳市汇春科技股份有限公司 | schmitt trigger and control method thereof |
| CN110995245A (en) * | 2019-12-27 | 2020-04-10 | 成都九芯微科技有限公司 | Input circuit |
| CN111342816A (en) * | 2020-03-30 | 2020-06-26 | 潍柴动力股份有限公司 | Signal filtering method, device, system and readable medium |
| CN111342816B (en) * | 2020-03-30 | 2023-04-18 | 潍柴动力股份有限公司 | Signal filtering method, device, system and readable medium |
| CN113946882A (en) * | 2021-10-20 | 2022-01-18 | 深圳大学 | Schmitt trigger-based ultralow-power-consumption weak physical unclonable function circuit |
| CN113946882B (en) * | 2021-10-20 | 2023-04-18 | 深圳大学 | Schmitt trigger-based ultralow-power-consumption weak physical unclonable function circuit |
| CN117318697A (en) * | 2023-09-15 | 2023-12-29 | 辰芯半导体（深圳）有限公司 | Level shift circuit and power supply device |
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