CN203883674U - Light-load switching power supply chip - Google Patents
Light-load switching power supply chip Download PDFInfo
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- CN203883674U CN203883674U CN201420189084.3U CN201420189084U CN203883674U CN 203883674 U CN203883674 U CN 203883674U CN 201420189084 U CN201420189084 U CN 201420189084U CN 203883674 U CN203883674 U CN 203883674U
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Abstract
The utility model discloses a light-load switching power supply chip, and relates to the electrical field. Switching between connection between the output end of the light-load switching power supply chip and a power end and connection between the output end of the light-load switching power supply chip and a grounding end is controlled through compensation signals outputted by a compensation control circuit, the switching frequency of the light-load switching power supply chip is determined by clock signals inputted to a switching assembly, reduction in the switching frequency is realized, and the efficiency of a light-load switching power supply becomes high, thereby achieving a purpose that voltage ripple becomes great. When a clock signal outputted by a clock signal generation unit is a rising edge, the output end of the light-load switching power supply chip is connected with the power end; and when current between the power end and the output end is detected to be greater than a set current value by a current detection branch circuit, second compensation signals outputted by the current detection branch circuit control the compensation control circuit, thereby enabling compensation signals outputted by the compensation control circuit to enable the output end to be connected with the grounding end until the next clock signal. The process is repeated again and again.
Description
Technical field
The utility model relates to a kind of Switching Power Supply, relates in particular to the efficient Switching Power Supply of a kind of underloading.
Background technology
Switching Power Supply is widely used in all kinds of portable products such as mobile phone, panel computer and digital camera as important power management class circuit.Than linear voltage regulator, Switching Power Supply managing chip, as DC-DC transducer, maximum advantage is exactly that efficiency is high.And in portable use, the height of DC-DC efficiency under underload has determined the stand-by time of portable product system to a great extent.Therefore, in recent years, low-power consumption, high efficiency one of the study hotspot for numerous portable use that is designed to.
The power consumption of Switching Power Supply is generally by conduction loss, and quiescent dissipation three parts of switching loss and chip internal analog circuit form.
Conduction loss is mainly that electric current flows through the energy that the conducting resistance of power tube consumes, and increases with the increase of chip load current;
The moment of switching loss conducting has the loss of charge or discharge, and determines the loss that has a resistance on electric device of triangular wave that inducing current produces, and Switching Power Supply satisfied formula in the time of conducting is: VDDD=V
oUT;
Wherein, VDD is input power, and D is duty ratio, V
oUTfor output voltage;
Quiescent dissipation is the consumption of chip internal analog circuit in the time of work.
Wherein, switching loss and quiescent dissipation are all irrelevant with chip load current size.So chip is in the time of heavy duty, conduction loss is main loss, and in the time of underloading, switching loss and quiescent dissipation have formed the main loss of transducer.Efficiency during due to portable set standby depends primarily on the power consumption of Switching Power Supply under underload situation, improves the efficiency of Switching Power Supply in the time of underload, just can effectively extend the service time of battery of portable set.But current Switching Power Supply exists switching frequency high, the problem that light load efficiency is low.
Summary of the invention
The utility model exists switching frequency high for solving existing Switching Power Supply, the problem that light load efficiency is low, thus a kind of technical scheme of underload switch power supply chip is provided.
A kind of underload switch power supply chip described in utility model, comprising:
Switch module, under a clock signal and a compensation signal control, make an output in be connected with power end and and earth terminal be connected between switch;
Feedback network, is connected to described switching device by a feedback voltage, in order to form one first compensating signal and a feedback signal according to described feedback voltage;
Current detecting branch road, is connected between described output and described power end, in order to detect the electric current between described power end and described output and to form one second compensating signal;
Clock signal generation unit, connects described switch module, in order to generate described clock signal, and produces the 3rd compensating signal according to the second compensating signal;
Compensation control circuit, be connected between described feedback network and described switch module, and between described current detecting branch road and described switch module, and between described clock signal generation unit and described switch module, in order to generate described compensating signal and to export described switch module to according to described the first compensating signal, described the second compensating signal and described the 3rd compensating signal.
Preferably, comprise the first testing circuit, described the first testing circuit is connected with the Enable Pin of underload switch power supply chip described in described feedback network and, enables control signal to control described underload switch power supply chip in work or holding state in order to the described feedback signal that forms according to described feedback network and one first reference voltage and one second reference voltage to described Enable Pin output one.
Preferably, comprise the second testing circuit, described the second testing circuit is connected with described feedback network and described clock signal generation unit;
Described the second testing circuit generates high-frequency described clock signal or generates low-frequency described clock signal in order to clock signal generation unit described in the described feedback signal that forms according to described feedback network and one the 3rd reference voltage control, and/or
Described the second testing circuit forms an overload signal in order to the described feedback signal and one the 4th reference voltage that form according to described feedback network.
Preferably; comprise overload protecting circuit; described overload protecting circuit is connected with described feedback network and described the second testing circuit, in order to described first compensating signal of feedback network output described in the described overload signal control forming according to described the second testing circuit in ground connection and connect between described compensation control circuit and switch.
Preferably, also comprise and enable control circuit, described in enable control circuit according to underload switch power supply chip described in an enable signal and one the 5th reference voltage control in work or holding state.
Preferably, described switch module comprises:
Rest-set flip-flop, the S end of described rest-set flip-flop connects described clock signal generation unit, and the R end of described rest-set flip-flop connects described compensation control circuit, generates the first output signal and the second output signal according to described compensating signal and described clock signal;
The first buffer, described the first buffer comprises the control end of one first buffer, first input end, the second input of one first buffer and the output of one first buffer of one first buffer, the control end of described the first buffer connects the Q end of described rest-set flip-flop, the first input end of described the first buffer connects a drive end, the second input of described the first buffer connects described output, in order to form the first control signal according to described the first output signal;
The first switch, be connected between described power end and described output, described the first switch comprises the control end of one first switch, and the control end of described the first switch connects the output of described the first buffer, according to described the first control signal to control the shutoff of described the first switch;
The second buffer, shown in the second buffer comprise the control end of one second buffer and the output of one second buffer, the control end of described the second buffer connects described rest-set flip-flop
end, in order to form the second control signal according to described the second output signal;
Second switch, be connected between described earth terminal and described output, described second switch comprises the control end of a second switch, and the control end of described second switch connects the output of described the second buffer, according to described the second control signal to control the shutoff of described second switch.
Preferably, described feedback network comprises:
Error amplifier, the in-phase input end of described error amplifier connects described feedback voltage, and the inverting input of described error amplifier connects one the 6th reference voltage, and the first compensating signal of described error amplifier output is to described compensation control circuit.
Preferably, described current detecting branch road comprises:
Current sense amplifier, the in-phase input end of described current sense amplifier connects described power end, the inverting input of described current sense amplifier is connected between described power end and described output, and the second compensating signal of described current sense amplifier output is to described compensation control circuit and described clock signal generation unit;
One resistance R 1 is parallel between the in-phase input end and inverting input of described current sense amplifier.
Preferably, described compensation control circuit comprises:
The first comparator, the in-phase input end of described the first comparator connects described the second compensating signal, and the inverting input of described the first comparator connects one the 7th reference voltage;
The second comparator, the in-phase input end of described the second comparator connects described the 3rd compensating signal, the first compensating signal described in the anti-phase input termination of described the second comparator;
Or, first input end described or door connects the output of described the first comparator, and the second input described or door connects the output of described the second comparator, described or extremely described switch module of a compensating signal of exporting.
Preferably, described the first testing circuit comprises:
The 3rd comparator, the in-phase input end of described the 3rd comparator connects described feedback signal, and the inverting input of described the 3rd comparator connects described the first reference voltage, enables control signal described in the output of the output of described the 3rd comparator;
The 4th comparator, the in-phase input end of described the 4th comparator connects described feedback signal, and the inverting input of described the 4th comparator connects described the second reference voltage, enables control signal described in the output of the output of described the 4th comparator.
Preferably, described the second testing circuit comprises:
The 5th comparator, the in-phase input end of described the 5th comparator connects described feedback signal, and the inverting input of described the 5th comparator connects described the 4th reference voltage, and described the 5th comparator output terminal is exported described overload signal,
The 6th comparator, the in-phase input end of described the 6th comparator connects described feedback signal, and the inverting input of described the 6th comparator connects described the 3rd reference voltage, and described the 6th comparator output terminal connects described clock signal generation unit.
Preferably, described in, enabling control circuit comprises:
Close comparator, described in close comparator in-phase input end connect described enable signal, described in close the 5th reference voltage described in the anti-phase input termination of comparator;
NMOS pipe, the grid of described NMOS pipe connects closes comparator output terminal, and the source electrode of described NMOS pipe connects described earth terminal, and the drain electrode of described NMOS pipe connects between described feedback network and described compensation control circuit.
The beneficial effects of the utility model:
The utility model changes the ripple of voltage by compensation control circuit, in the time that power supply chip output actual current is greater than the electric current of load resistance of setting, unnecessary electric current is to capacitor charging, it is large that ripple becomes, and output voltage raises, thereby produce the ripple of output voltage, now power end is connected with output, the electric current of load resistance is less, and the first switch is longer in the time of closed state, has reduced switching frequency.The switching of the output of having realized switch module by described the second testing circuit between power end and earth terminal, thus light load efficiency improved.
Brief description of the drawings
Fig. 1 is a kind of underload switch power supply chip block diagram described in the utility model;
Fig. 2 is the internal circuit diagram of a kind of underload switch power supply chip described in the utility model.
Fig. 3 is a kind of underload switch power supply chip peripheral circuit diagram described in the utility model.
In accompanying drawing: 1. the second testing circuit; 11. the 5th comparators; 12. the 6th comparators; 2. clock signal generation unit; 3. the first testing circuit; 31. the 3rd comparators; 32. the 4th comparators; 4. overload protecting circuit; 5. current detecting branch road; 6. feedback network; 7. compensation control circuit; 71. first comparators; 72. second comparators; 73. or door; 8. switch module; 81.RS trigger; 82. first buffers; 83. first switches; 84. second buffers; 85. second switches; 9. enable control circuit; 91. close comparator; 92.NMOS pipe.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite of not making creative work, belongs to the scope that the utility model is protected.
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the utility model can combine mutually.
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail, but not as restriction of the present utility model.
As depicted in figs. 1 and 2, provide a kind of underload switch power supply chip, comprising:
Switch module 8, under a clock signal clk and a compensation signal control, make an output SW in be connected with power end IN and and earth terminal GND be connected between switch;
Feedback network 6, is connected to switching device by a feedback voltage FB, in order to form one first compensating signal and a feedback signal according to feedback voltage FB;
Current detecting branch road 5, is connected between output SW and power end IN, in order to detect the electric current between power end IN and output SW and to form one second compensating signal;
Clock signal generation unit 2, connecting valve assembly 8, in order to generated clock signal CLK, and produces the 3rd compensating signal according to the second compensating signal;
Compensation control circuit 7, be connected between feedback network 6 and switch module 8, and between current detecting branch road 5 and switch module 8, and between clock signal generation unit 2 and switch module 8, in order to generate compensating signal and to export switch module 8 to according to the first compensating signal, the second compensating signal and the 3rd compensating signal.
In the present embodiment, between the output SW of underload switch power supply chip is connected with power end IN and earth terminal GND, switching is that the compensating signal of exporting by compensation control circuit 7 is realized, the clock signal clk that inputs to switch module 8 has determined the switching frequency of underload switch power supply chip, the frequency that has realized reduction switch uprises the efficiency of underloading, becomes large object thereby reach voltage ripple.
When the clock signal clk of exporting when clock signal generation unit 2 is rising edge, the output SW of underload switch power supply chip connects power end IN; In the time that current detecting branch road 5 detects electric current between power end IN and output SW and is greater than the current value of setting, the second compensation signal control compensation control circuit 7 that current detecting branch road 5 is exported, the compensating signal that compensation control circuit 7 is exported makes output SW be connected with earth terminal GND, until next clock signal, circulation goes round and begins again to obtain.
Switch module 8 in the present embodiment comprises: rest-set flip-flop 81, the first buffer 82, the first switch 83, the second buffer 84 and second switch 85,
Rest-set flip-flop 81 connects compensation control circuit 7 and clock signal generation unit 2, generates the first output signal and the second output signal according to compensating signal and clock signal clk;
The first buffer 82 is connected between rest-set flip-flop 81, drive end BOOT and output SW, in order to form the first control signal according to the first output signal;
The first switch 83 is connected between the first buffer 82, power end IN and output SW, according to the first control signal with the break-make between control output end SW and power end IN;
The second buffer 84 is connected between rest-set flip-flop 81, earth terminal GND and output SW, in order to form the second control signal according to the second output signal;
Second switch 85 is connected between the second buffer 84, earth terminal GND and output SW, according to the second control signal with the break-make between control output end SW and earth terminal GND;
The positive pole of diode D connects 5V voltage, and the negative pole of diode D meets drive end BOOT.
Feedback network 6 in the present embodiment comprises: error amplifier;
The in-phase input end of error amplifier connects feedback voltage FB, and the inverting input of error amplifier connects one the 6th reference voltage, and the first compensating signal of error amplifier output is to compensation control circuit 7.
Current detecting branch road 5 in the present embodiment comprises: current sense amplifier and resistance R 1;
The in-phase input end of current sense amplifier connects power end IN, the inverting input of current sense amplifier is connected between power end IN and output SW, and the second compensating signal of current sense amplifier output is to compensation control circuit 7 and clock signal generation unit 2;
Resistance R 1 is parallel between the in-phase input end and inverting input of current sense amplifier.
Compensation control circuit 7 in the present embodiment comprises: the first comparator 71, the second comparator 72 and or door 73;
The in-phase input end of the first comparator 71 connects the second compensating signal, and the inverting input of the first comparator 71 connects one the 7th reference voltage;
The in-phase input end of the second comparator 72 connects the 3rd compensating signal, anti-phase input termination first compensating signal of the second comparator 72;
Or door 73 first input end connects the output of the first comparator 71, or the second input of door 73 connects the output of the second comparator 72, or the compensating signals of door 73 outputs are to switch module 8.
Shown in Fig. 2 and Fig. 3, the first comparator 71 changes the ripple of output voltage, in the time that the actual current of underload switch power supply chip is greater than the electric current of the load resistance R2 setting in underload switch power supply chip peripheral circuit, unnecessary electric current charges to inductance L, it is large that ripple becomes, output voltage raises, thereby produce the ripple of output voltage, now the first switch 83 is always in closure state (being equivalent to be provided with minimum output current threshold), load resistance R2 electric current is less, the first switch 83 is longer in the time of closed state, has reduced switching frequency.
The break-make of this underload switch power supply chip is to realize by the second comparator 72 of pulsed drive in the present embodiment, the switching frequency of power supply chip is fixed under normal circumstances, the clock signal clk that inputs to switch module 8 has determined the switching frequency of power supply chip, the second comparator 72 has determined when the first switch 83 disconnects, the efficiency of (the second comparator 72 has determined the length of the time that the first switch 83 turn-offs) underloading uprises and frequency need to be reduced, and it is large that voltage ripple can become; When the clock signal clk of exporting when clock signal generation unit 2 is rising edge, rest-set flip-flop 81 upsets make the first switch 83 conductings, and second switch 85 turn-offs; When the first switch 83 output currents risings (flowing to the output SW of power supply chip from the input IN of power supply chip), until the first switch 83 output currents are greater than the current value of setting, the first comparator 71 upset output high level, after this first switch 83 ON time are determined by error amplifier and the second comparator 72, when rising, the first switch 83 output currents make the second comparator 72 upsets be output as high level, rest-set flip-flop 81 upsets are turn-offed the first switch 83, second switch 85 conductings.Until next clock signal, circulation goes round and begins again to obtain.
As a kind of preferred embodiment of the present utility model, comprise the first testing circuit 3, the first testing circuit 3 is connected with the Enable Pin of feedback network 6 and a underload switch power supply chip, enables control signal to control underload switch power supply chip in work or holding state in order to the feedback signal that forms according to feedback network 6 and one first reference voltage and one second reference voltage to Enable Pin output one.
Shown in Fig. 2 and Fig. 3, between being connected with power end IN and earth terminal GND, the output SW that has realized underload switch power supply chip by the first testing circuit 3 in the present embodiment switches, in the time that feedback signal is greater than the first reference voltage, the output SW of underload switch power supply chip is connected with earth terminal GND, and the inductance L in underload switch power supply chip peripheral circuit enters discharge condition; In the time that feedback signal is less than the second reference voltage, the output SW of underload switch power supply chip is connected with power end IN, and inductance L enters charged state.
The first testing circuit 3 in the present embodiment comprises: the 3rd comparator 31 and the 4th comparator 32,
The in-phase input end of the 3rd comparator 31 connects feedback signal, and the inverting input of the 3rd comparator 31 connects the first reference voltage, the output output enable control signal of the 3rd comparator 31;
The in-phase input end of the 4th comparator 32 connects feedback signal, and the inverting input of the 4th comparator 32 connects the second reference voltage, the output output enable control signal of the 4th comparator 32.
In the present embodiment, load needs hour (underloading pattern) of electric current: after the clock signal clk that clock signal generation unit 2 is exported is rising edge, the second comparator 72 is output as high level can be output as high level prior to the first comparator 71 upsets, now the first switch 83 still conducting until the first comparator 71 comparators upsets, make the electric current of output be greater than the required circuit of load, therefore feedback voltage FB rises; Through several cycles, feedback voltage FB rises to and is greater than the first reference voltage, the 3rd comparator 31 upset output high level, and power supply chip enters park mode (sleep), makes the Q=0 of rest-set flip-flop 81,
Q=0, now, except the 3rd comparator 31 and the 4th comparator 32, other circuit quit work, and the first switch 83 and second switch 85 all turn-off; Under the effect of load current, feedback voltage FB declines, when feedback voltage FB drops to while being less than the second reference voltage, and the 4th comparator 32 upset output high level, power supply chip reenters mode of operation (work), makes the Q=1 of rest-set flip-flop 81,
the first switch 83 conductings, second switch 85 turn-offs.If load circuit is still less, sleep → work → sleep → work ..., circulation again and again.Because in the time of sleep pattern, chip quiescent current is little, the first switch 83 and second switch 85 do not have switching motion simultaneously, thus reduce the internal power consumption of chip self, thus the conversion efficiency while having improved underloading.
As a kind of preferred embodiment of the present utility model, comprise that the second testing circuit 1, the second testing circuit 1 is connected with feedback network 6 and clock signal generation unit 2;
The second testing circuit 1 generates high-frequency clock signal clk or generates low-frequency clock signal clk in order to the feedback signal and one the 3rd reference voltage control clock signal generation unit 2 that form according to feedback network 6, and/or
The second testing circuit 1 forms an overload signal OVP in order to the feedback signal and one the 4th reference voltage that form according to feedback network 6.
As a kind of preferred embodiment of the present utility model; comprise overload protecting circuit 4; overload protecting circuit 4 is connected with feedback network 6 and the second testing circuit 1, controls in order to the overload signal OVP forming according to the second testing circuit 1 the first compensating signal switching between ground connection and connection compensation control circuit 7 that feedback network 6 is exported.
As a kind of preferred embodiment of the present utility model, also comprise and enable control circuit 9, enable control circuit 9 according to an enable signal and one the 5th reference voltage control underload switch power supply chip in work or holding state.
As a kind of preferred embodiment of the present utility model, the second testing circuit 1 comprises: the 5th comparator 11 and the 6th comparator 12;
The in-phase input end of the 5th comparator 11 connects feedback signal, and the inverting input of the 5th comparator 11 connects the 4th reference voltage, the 5th comparator 11 output output overloading signal OVP,
The in-phase input end of the 6th comparator 12 connects feedback signal, and the inverting input of the 6th comparator 12 connects the 3rd reference voltage, and the 6th comparator 12 outputs connect clock signal generation unit 2.
As a kind of preferred embodiment of the present utility model, enable control circuit 9 and comprise: close comparator 91 and NMOS pipe 92;
The in-phase input end of closing comparator 91 connects enable signal EN, and the inverting input of closing comparator 91 connects the 5th reference voltage;
The grid of NMOS pipe 92 connects closes comparator 91 outputs, and the source electrode of NMOS pipe 92 meets earth terminal GND, and 92 drain electrodes of NMOS pipe connect between feedback network 6 and compensation control circuit 7.
In the time that enable signal EN is greater than the 5th reference voltage, close comparator 91 output low level control NMOS and manage 92 conductings, make the output signal ground connection of error amplifier, make power supply chip enter park mode; In the time that enable signal EN is less than the 5th reference voltage, close comparator 91 and export 92 cut-offs of high level control NMOS pipe, what make error amplifier outputs signal to compensation control circuit 7, makes power supply chip enter mode of operation.
As a kind of preferred embodiment of the present utility model, illustrate the present embodiment as an example of one group of reference voltage example: the first reference voltage is as 0.808V, the second reference voltage is 0.796V, the 3rd reference voltage is 0.3V, the 4th reference voltage is 0.88V, the 5th reference voltage is 1.3V, and the 6th reference voltage is 0.8V, and the 7th reference voltage is 0.05V.
In above-described embodiment, related switching circuit is only a kind of topological diagram of switching circuit, and the utility model is applicable in all switching circuits, and wherein the first switch 83 and second switch 85 can be metal-oxide-semiconductor, triode, diode or rectifying tube etc.
The foregoing is only the utility model preferred embodiment; not thereby limit execution mode of the present utility model and protection range; to those skilled in the art; the scheme that being equal to of should recognizing that all utilization the utility model specifications and diagramatic content done replaces and apparent variation obtains, all should be included in protection range of the present utility model.
Claims (12)
1. a underload switch power supply chip, is characterized in that, comprising:
Switch module, under a clock signal and a compensation signal control, make an output in be connected with power end and and earth terminal be connected between switch;
Feedback network, is connected to described switching device by a feedback voltage, in order to form one first compensating signal and a feedback signal according to described feedback voltage;
Current detecting branch road, is connected between described output and described power end, in order to detect the electric current between described power end and described output and to form one second compensating signal;
Clock signal generation unit, connects described switch module, in order to generate described clock signal, and produces the 3rd compensating signal according to the second compensating signal;
Compensation control circuit, be connected between described feedback network and described switch module, and between described current detecting branch road and described switch module, and between described clock signal generation unit and described switch module, in order to generate described compensating signal and to export described switch module to according to described the first compensating signal, described the second compensating signal and described the 3rd compensating signal.
2. underload switch power supply chip as claimed in claim 1, it is characterized in that, comprise the first testing circuit, described the first testing circuit is connected with the Enable Pin of underload switch power supply chip described in described feedback network and, enables control signal to control described underload switch power supply chip in work or holding state in order to the described feedback signal that forms according to described feedback network and one first reference voltage and one second reference voltage to described Enable Pin output one.
3. underload switch power supply chip as claimed in claim 1, is characterized in that, comprise the second testing circuit, described the second testing circuit is connected with described feedback network and described clock signal generation unit;
Described the second testing circuit generates high-frequency described clock signal or generates low-frequency described clock signal in order to clock signal generation unit described in the described feedback signal that forms according to described feedback network and one the 3rd reference voltage control, and/or
Described the second testing circuit forms an overload signal in order to the described feedback signal and one the 4th reference voltage that form according to described feedback network.
4. underload switch power supply chip as claimed in claim 3; it is characterized in that; comprise overload protecting circuit; described overload protecting circuit is connected with described feedback network and described the second testing circuit, in order to described first compensating signal of feedback network output described in the described overload signal control forming according to described the second testing circuit in ground connection and connect between described compensation control circuit and switch.
5. underload switch power supply chip as claimed in claim 1, is characterized in that, also comprise and enable control circuit, described in enable control circuit according to underload switch power supply chip described in an enable signal and one the 5th reference voltage control in work or holding state.
6. underload switch power supply chip as claimed in claim 1, is characterized in that, described switch module comprises:
Rest-set flip-flop, the S end of described rest-set flip-flop connects described clock signal generation unit, and the R end of described rest-set flip-flop connects described compensation control circuit, generates the first output signal and the second output signal according to described compensating signal and described clock signal;
The first buffer, described the first buffer comprises the control end of one first buffer, first input end, the second input of one first buffer and the output of one first buffer of one first buffer, the control end of described the first buffer connects the Q end of described rest-set flip-flop, the first input end of described the first buffer connects a drive end, the second input of described the first buffer connects described output, in order to form the first control signal according to described the first output signal;
The first switch, be connected between described power end and described output, described the first switch comprises the control end of one first switch, and the control end of described the first switch connects the output of described the first buffer, according to described the first control signal to control the shutoff of described the first switch;
The second buffer, shown in the second buffer comprise the control end of one second buffer and the output of one second buffer, the control end of described the second buffer connects described rest-set flip-flop
end, in order to form the second control signal according to described the second output signal;
Second switch, be connected between described earth terminal and described output, described second switch comprises the control end of a second switch, and the control end of described second switch connects the output of described the second buffer, according to described the second control signal to control the shutoff of described second switch.
7. underload switch power supply chip as claimed in claim 1, it is characterized in that, described feedback network comprises: error amplifier, the in-phase input end of described error amplifier connects described feedback voltage, the inverting input of described error amplifier connects one the 6th reference voltage, and the first compensating signal of described error amplifier output is to described compensation control circuit.
8. underload switch power supply chip as claimed in claim 1, it is characterized in that, described current detecting branch road comprises: current sense amplifier, the in-phase input end of described current sense amplifier connects described power end, the inverting input of described current sense amplifier is connected between described power end and described output, and the second compensating signal of described current sense amplifier output is to described compensation control circuit and described clock signal generation unit;
One resistance R 1 is parallel between the in-phase input end and inverting input of described current sense amplifier.
9. underload switch power supply chip as claimed in claim 1, is characterized in that, described compensation control circuit comprises:
The first comparator, the in-phase input end of described the first comparator connects described the second compensating signal, and the inverting input of described the first comparator connects one the 7th reference voltage;
The second comparator, the in-phase input end of described the second comparator connects described the 3rd compensating signal, the first compensating signal described in the anti-phase input termination of described the second comparator;
Or, first input end described or door connects the output of described the first comparator, and the second input described or door connects the output of described the second comparator, described or extremely described switch module of a compensating signal of exporting.
10. underload switch power supply chip as claimed in claim 2, is characterized in that, described the first testing circuit comprises:
The 3rd comparator, the in-phase input end of described the 3rd comparator connects described feedback signal, and the inverting input of described the 3rd comparator connects described the first reference voltage, enables control signal described in the output of the output of described the 3rd comparator;
The 4th comparator, the in-phase input end of described the 4th comparator connects described feedback signal, and the inverting input of described the 4th comparator connects described the second reference voltage, enables control signal described in the output of the output of described the 4th comparator.
11. underload switch power supply chips as claimed in claim 3, is characterized in that, described the second testing circuit comprises:
The 5th comparator, the in-phase input end of described the 5th comparator connects described feedback signal, and the inverting input of described the 5th comparator connects described the 4th reference voltage, and described the 5th comparator output terminal is exported described overload signal,
The 6th comparator, the in-phase input end of described the 6th comparator connects described feedback signal, and the inverting input of described the 6th comparator connects described the 3rd reference voltage, and described the 6th comparator output terminal connects described clock signal generation unit.
12. underload switch power supply chips as claimed in claim 5, is characterized in that, described in enable control circuit and comprise:
Close comparator, described in close comparator in-phase input end connect described enable signal, described in close comparator inverting input connect described the 5th reference voltage;
NMOS pipe, the grid of described NMOS pipe connects closes comparator output terminal, and the source electrode of described NMOS pipe connects described earth terminal, and the drain electrode of described NMOS pipe connects between described feedback network and described compensation control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420189084.3U CN203883674U (en) | 2014-04-17 | 2014-04-17 | Light-load switching power supply chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420189084.3U CN203883674U (en) | 2014-04-17 | 2014-04-17 | Light-load switching power supply chip |
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| CN203883674U true CN203883674U (en) | 2014-10-15 |
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|---|---|---|---|
| CN201420189084.3U Expired - Fee Related CN203883674U (en) | 2014-04-17 | 2014-04-17 | Light-load switching power supply chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099184A (en) * | 2014-04-17 | 2015-11-25 | 钰太芯微电子科技（上海）有限公司 | Light-load switching power supply chip |
| CN111865082A (en) * | 2020-08-06 | 2020-10-30 | 成都芯源系统有限公司 | Low quiescent current switching converter and control circuit thereof |
-
2014
- 2014-04-17 CN CN201420189084.3U patent/CN203883674U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105099184A (en) * | 2014-04-17 | 2015-11-25 | 钰太芯微电子科技（上海）有限公司 | Light-load switching power supply chip |
| CN105099184B (en) * | 2014-04-17 | 2017-12-29 | 钰太芯微电子科技（上海）有限公司 | A kind of underload switch power supply chip |
| CN111865082A (en) * | 2020-08-06 | 2020-10-30 | 成都芯源系统有限公司 | Low quiescent current switching converter and control circuit thereof |
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Inventor after: Ye Jinghua Inventor after: Chen Jia Inventor before: Ye Jinghua |
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Free format text: CORRECT: INVENTOR; FROM: YE JINGHUA TO: YE JINGHUA CHEN JIA |
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Granted publication date: 20141015 Termination date: 20200417 |