CN203588106U

CN203588106U - Improved voltage following circuit

Info

Publication number: CN203588106U
Application number: CN201320739320.XU
Authority: CN
Inventors: 王钊
Original assignee: Wuxi Vimicro Corp
Current assignee: Wuxi Vimicro Corp
Priority date: 2013-11-21
Filing date: 2013-11-21
Publication date: 2014-05-07
Anticipated expiration: 2023-11-21

Abstract

The utility model relates to an improved voltage following circuit which comprises an offset calibrating circuit and a programmable operation amplifier. The offset calibrating circuit compares the voltage at the first input end of the programmable operation amplifier and the voltage at the second input end of the programmable operation amplifier and outputs an adjustment signal according to the comparison result. The programmable operation amplifier adjusts the voltage at the second input end of the programmable operation amplifier according to the adjustment signal to reduce the offset voltage of the programmable operation amplifier.

Description

Improved voltage follower circuit

Technical field

The utility model relates to circuit engineering field, relates in particular to a kind of improved voltage follower circuit.

Background technology

Development along with circuit engineering field, complementary metal oxide semiconductor (CMOS) (Complementary Metal Oxide Semiconductor, CMOS) circuit becomes more and more prevailing, its reason is: one, the easily continuous size reduction of CMOS technique, make under CMOS technique circuit area easily with process, reduce and reduce, thereby there is advantage more cheaply; Two, compare with bipolar device, cmos device has lower grid input current, conventionally can ignore grid input current, and bipolar device needs larger base current, unfavorable to low consumption circuit application.But cmos circuit is compared with ambipolar circuit, (offset voltage) is larger for its misalignment voltage, and the misalignment voltage of cmos device arrives 50mV up to 10mV conventionally, and the misalignment voltage of bipolar device is only for 1mV is to 5mV.

Fig. 1 is a kind of structural drawing of voltage follower circuit, if operational amplifier OPA realizes with cmos device, generally all there is larger misalignment voltage, because the input of operational amplifier OPA is to metal-oxide layer-semiconductor-field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET, hereinafter to be referred as metal-oxide-semiconductor) do not mate and not the mating of the load current mirror of input stage, can produce equivalence at the misalignment voltage of the input end of operational amplifier OPA, there is a random misalignment voltage in the first input end and the voltage between the second input end that are OPA.

Utility model content

In view of this, the utility model provides a kind of voltage follower circuit, can effectively reduce the adapt voltages of the input end of the operational amplifier in voltage follower circuit.

First aspect, the utility model embodiment provides a kind of voltage follower circuit, and this voltage follower circuit comprises: mistuning calibration function circuit and programmable operational amplifier;

Described mistuning calibration function circuit compares the voltage of the voltage of the first input end of described programmable operational amplifier and the second input end, and according to comparative result, signal is adjusted in output;

Described programmable operational amplifier is adjusted the voltage of the second input end of described programmable operational amplifier according to described adjustment signal, to reduce the misalignment voltage of described programmable operational amplifier.

Further, described mistuning calibration function circuit comprises: the first comparator circuit, the second comparator circuit and signal output logic circuit; Described the first comparator circuit for the voltage that judges the voltage of first input end of described programmable operational amplifier and whether be greater than the second input end and predefined the first error voltage threshold value with; Described the second comparator circuit is for judging whether the voltage of first input end of described programmable operational amplifier is less than the poor of the voltage of the second input end and predefined the second error voltage threshold value; When the voltage of the first input end of described programmable operational amplifier be greater than the voltage of the second input end and predefined the first error voltage threshold value and time, described signal output logic circuit is adjusted the adjustment signal of its output so that the voltage of the second input end of described programmable operational amplifier is increased; When the voltage of the first input end of described programmable operational amplifier is less than the voltage of the second input end and predefined the second error voltage threshold value poor, described signal output logic circuit is adjusted the adjustment signal of its output so that the voltage of the second input end of described programmable operational amplifier is reduced; When the voltage of the first input end of described programmable operational amplifier be not more than the voltage of the second input end and predefined the first error voltage threshold value and, and when the voltage of the first input end of described programmable operational amplifier is not less than the voltage of the second input end and predefined the second error voltage threshold value poor, described programmable operational amplifier keeps the voltage of the second input end of described programmable operational amplifier constant according to the adjustment signal of described signal output logic circuit output.

Further, described the first comparator circuit comprises: the first switch, second switch, the 3rd switch, the first operational amplifier, the first electric capacity, the first phase inverter, the second phase inverter, the first d type flip flop and the first voltage source, wherein, the first end of described the first switch is connected with the first input end of described programmable operational amplifier, the first end of described second switch is connected with the positive pole of described the first voltage source, the negative pole of described the first voltage source is connected with the second input end of described programmable operational amplifier, the second end of described the first switch and the second end of second switch are connected with the first input end of described the first operational amplifier respectively, the second input end of described the first operational amplifier is connected with the first end of the 3rd switch with the first end of the first electric capacity respectively, the second end of described the 3rd switch is connected with the output terminal of described the first operational amplifier, the output terminal of described the first operational amplifier is also connected with the input end of described the first phase inverter, the output terminal of described the first phase inverter is connected with the input end of described the second phase inverter, the output terminal of described the second phase inverter is connected with the input end of described the first d type flip flop, the first output terminal of described the first d type flip flop is connected with the first input end of described signal output logic circuit, described the second comparator circuit comprises: the 4th switch, the 5th switch, the 6th switch, the second operational amplifier, the second electric capacity, the 3rd phase inverter, the 4th phase inverter, the second d type flip flop and second voltage source, wherein, the first end of described the 4th switch is connected with the positive pole in described second voltage source, the negative pole in described second voltage source is connected with the first input end of described programmable operational amplifier, the first end of described the 5th switch is connected with the second input end of described programmable operational amplifier, the second end of the second end of described the 4th switch and the 5th switch is connected with the first input end of described the second operational amplifier respectively, the second input end of described the second operational amplifier is connected with the first end of the 6th switch with the first end of the second electric capacity respectively, the second end of described the 6th switch is connected with the output terminal of described the second operational amplifier, the output terminal of described the second operational amplifier is also connected with the input end of described the 3rd phase inverter, the output terminal of described the 3rd phase inverter is connected with the input end of described the 4th phase inverter, the output terminal of described the 4th phase inverter is connected with the input end of described the second d type flip flop, the first output terminal of described the second d type flip flop is connected with the second input end of described signal output logic circuit, wherein, described second switch, the 3rd switch, the 5th switch and the 6th switch are controlled by the signal of the first clock output, the signal that described the first switch and the 4th switch are exported after the 5th phase inverter by the signal of described the first clock output is controlled, and the signal that described the first d type flip flop and the second d type flip flop are exported by second clock is controlled.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; Manage PMOS pipe group in parallel with described the 2nd PMOS at least one group, the quantity of described PMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described PMOS pipe group, drain electrode is connected with the grid of PMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that the 2nd PMOS pipe drain electrode is connected; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

Further, described PMOS pipe group comprises the PMOS pipe of two series connection, and the grid of the PMOS pipe that in described PMOS pipe group, drain electrode is connected with the 2nd PMOS pipe drain electrode is connected with the grid of described the 2nd PMOS pipe.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; Manage PMOS pipe group in parallel with a described PMOS at least one group, the quantity of described PMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described PMOS pipe group, source electrode is connected with the grid of PMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that a PMOS pipe source electrode is connected; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

Further, described PMOS pipe group comprises the PMOS pipe of two series connection, and the grid of the PMOS pipe that in described PMOS pipe group, drain electrode is connected with a PMOS pipe source electrode is connected with the tube grid of a described PMOS.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; Manage NMOS pipe group in parallel with a described NMOS at least one group, the quantity of described NMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described NMOS pipe group, drain electrode is connected with the grid of NMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that a NMOS pipe drain electrode is connected; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

Further, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with a NMOS pipe source electrode is connected with the grid of a described NMOS pipe.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; Manage NMOS pipe group in parallel with described the 2nd NMOS at least one group, the quantity of described NMOS pipe group is identical with the number of signals of described mistuning calibration function circuit output, and the grid of the NMOS pipe that in described NMOS pipe group, drain electrode is connected with the 2nd NMOS pipe drain electrode is connected with the signal output part of described mistuning calibration function circuit; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

Further, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with the 2nd NMOS pipe source electrode is connected with described the 2nd NMOS tube grid.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Manage NMOS pipe group in parallel with described the 3rd NMOS at least one group, the quantity of described NMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described NMOS pipe group, drain electrode is connected with the grid of NMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that the 3rd NMOS pipe drain electrode is connected; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

Further, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with the 3rd NMOS pipe source electrode is connected with described the 3rd NMOS tube grid.

Further, described programmable operational amplifier comprises: a PMOS pipe and the 2nd PMOS pipe; Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe; A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection; Between the source electrode of the source electrode of a described PMOS pipe and described the 2nd PMOS pipe, be in series with resistance string, PMOS pipe in parallel on each resistance in described resistance string, resistance quantity in described resistance string is identical with the adjustment number of signals of described mistuning calibration function circuit output, is connected in parallel on the grid of each the ohmically PMOS pipe in described resistance string and the adjustment signal output part of described mistuning calibration function circuit is connected; The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe; Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

By the utility model, embodiment provides voltage follower circuit, the voltage of the first input end of the programmable operational amplifier that the mistuning calibration function circuit that this voltage follower circuit comprises comprises this voltage follower circuit and the voltage of the second input end compare, according to comparative result, signal is adjusted in output, this programmable operational amplifier is adjusted the voltage of the second input end of this programmable operational amplifier according to adjustment signal, within the misalignment voltage of this programmable operational amplifier is controlled to less scope.

Accompanying drawing explanation

Fig. 1 is the structural drawing of a kind of voltage follower circuit of the prior art;

The structural drawing of a kind of voltage follower circuit that Fig. 2 provides for the utility model embodiment;

The structural representation of a kind of mistuning calibration function circuit that Fig. 3 provides for the utility model embodiment;

The structural representation of the first programmable operational amplifier that Fig. 4 provides for the utility model embodiment;

The structural representation of the second programmable operational amplifier that Fig. 5 provides for the utility model embodiment;

The structural representation of the third programmable operational amplifier that Fig. 6 provides for the utility model embodiment;

The structural representation of the 4th kind of programmable operational amplifier that Fig. 7 provides for the utility model embodiment;

The structural representation of the 5th kind of programmable operational amplifier that Fig. 8 provides for the utility model embodiment;

The structural representation of the 6th kind of programmable operational amplifier that Fig. 9 provides for the utility model embodiment.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the utility model is described in further detail, obviously, described embodiment is only a part of embodiment of the utility model, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making all other embodiment that obtain under creative work prerequisite, all belong to the scope of the utility model protection.

The structural representation of a kind of voltage follower circuit that Fig. 2 provides for the utility model embodiment.As shown in Figure 2, this voltage follower circuit comprises: mistuning calibration function circuit 210 and programmable operational amplifier OP1.

The input end of mistuning calibration function circuit 210 is connected with the second input end with programmable operational amplifier OP1 first input end respectively, and the second input end of programmable operational amplifier OP1 is connected with the output terminal of programmable operational amplifier OP1.

Wherein, the voltage VP of the first input end of 210 couples of programmable operational amplifier OP1 of mistuning calibration function circuit and the voltage VN of the second input end compare, and according to comparative result, signal D is adjusted in output ₀～D _n-1;

Programmable operational amplifier OP1 is according to adjusting signal D ₀～D _n-1adjust the voltage VN of the second input end of programmable operational amplifier OP1, to reduce the misalignment voltage Vos of programmable operational amplifier OP1, Vos=VP-VN.

Concrete, mistuning calibration function circuit 210 produces a n position digital signal according to the voltage VN of the voltage VP of the first input end of programmable operational amplifier OP1 and the second input end, adjusts signal D ₀～D _n-1, D wherein _n-1for most significant digit, D ₀for lowest order.Programmable operational amplifier OP1 is according to adjusting signal D ₀～D _n-1regulate the voltage VN of its second input end.Mistuning calibration function circuit 210 detects VP>VN+Ve1(wherein at every turn, and Ve1 is predefined the first error voltage value, this Ve1>=0) time, the adjustment signal D of mistuning calibration function circuit 210 outputs ₀～D _n-1added one, programmable operational amplifier OP1 increases the voltage VN of the second input end, makes the voltage VN rising of the second input end more approach the voltage VP voltage of first input end, thereby reduces positive misalignment voltage+Vos.When mistuning calibration function circuit 210 detects VP<VN-Ve2 at every turn (wherein, Ve2 is predefined the second error voltage value, this Ve2>=0), the adjustment signal D of mistuning calibration function circuit 210 outputs ₀～D _n-1subtracted one, programmable operational amplifier OP1 reduces the voltage VN of the second input end, makes the voltage VN reduction of the second input end more approach the voltage VP of first input end, thereby reduces negative misalignment voltage-Vos.When mistuning calibration function circuit 210 detects VN-Ve2<VP<VN+Ve1 at every turn, the adjustment signal D of mistuning calibration function circuit 210 outputs ₀～D _n-1remain unchanged, represent that misalignment voltage Vos has been calibrated to tolerance interval, programmable operational amplifier OP1 keeps the voltage VN of the second input end constant, thereby it is constant to maintain misalignment voltage Vos, misalignment voltage Vos at this moment meets :-Ve2<Vos<Ve1.As enough hour of predefined the first error voltage threshold value Ve1 and the second error voltage threshold value Ve2, misalignment voltage Vos was limited in enough little scope.

Alternatively, mistuning calibration function circuit 210 specific implementations as shown in Figure 3.Mistuning calibration function circuit 210 comprises: the first comparator circuit 211, the second comparator circuits 212 and signal output logic circuit 213.

The first comparator circuit 211 for judge the voltage VP of the first input end of programmable operational amplifier OP1 whether be greater than the voltage VN of the second input end and predefined the first error voltage threshold value Ve1 and.

Whether the second comparator circuit 212 is less than the poor of the voltage VN of the second input end and predefined the second error voltage threshold value Ve2 for the voltage VP of the first input end of programmable operational amplifier OP1 relatively.

When the voltage VP of the first input end of programmable operational amplifier OP1 be greater than the voltage VN of the second input end and predefined the first error voltage threshold value Ve1's and time, programmable operational amplifier OP1 is according to the adjustment signal D of signal output logic circuit 213 outputs ₀～D _n-1the voltage VN of the second input end of programmable operational amplifier OP1 is increased; When the voltage VP of the first input end of programmable operational amplifier OP1 is less than the voltage VN of the second input end and predefined the second error voltage threshold value Ve2 poor, programmable operational amplifier OP1 is according to the adjustment signal D of signal output logic circuit 213 outputs ₀～D _n-1the voltage VN of the second input end of programmable operational amplifier OP1 is reduced; When the voltage VP of the first input end of programmable operational amplifier OP1 be not more than the second input end voltage VN and predefined the first error voltage threshold value Ve1's and, and when the voltage VP of the first input end of programmable operational amplifier OP1 is not less than the voltage VN of the second input end and predefined the second error voltage threshold value Ve2 poor, programmable operational amplifier OP1 is according to the adjustment signal D of signal output logic circuit 213 outputs ₀～D _n-1the voltage VN of the second input end of maintenance programmable operational amplifier OP1 is constant.

Wherein, the first comparator circuit 211 comprises: the first switch S 1, second switch S2, the 3rd switch S 3, the first operational amplifier OP2, the first capacitor C 1, the first phase inverter INV1, the second phase inverter INV2, the first d type flip flop ffdf1 and the first voltage source U1, wherein, the first end of the first switch S 1 is connected with the first input end of programmable operational amplifier OP1, the first end of second switch S2 is connected with the positive pole of the first voltage source U1, the negative pole of the first voltage source U1 is connected with the second input end of programmable operational amplifier OP1, the second end of the first switch S 1 is connected with the first input end of the first operational amplifier OP2 respectively with the second end of second switch S2, the second input end of the first operational amplifier OP2 is connected with the first end of the 3rd switch S 3 with the first end of the first capacitor C 1 respectively, the second end of the 3rd switch S 3 is connected with the output terminal of the first operational amplifier OP2, the output terminal of the first operational amplifier OP2 is also connected with the input end of the first phase inverter INV1, the output terminal of the first phase inverter INV1 is connected with the input end of the second phase inverter INV2, the output terminal of the second phase inverter INV2 is connected with the input end of the first d type flip flop ffdf1, the first output terminal of the first d type flip flop ffdf1 is connected with the first input end of signal output logic circuit 213.

The second comparator circuit 212 comprises: the 4th switch S 4, the five switch S 5, the six switch S 6, the second operational amplifier OP3, the second capacitor C 2, the three phase inverter INV3, the 4th phase inverter INV4, the second d type flip flop ffdf2 and second voltage source U2, wherein, the first end of the 4th switch S 4 is connected with the positive pole of second voltage source U2, the negative pole of second voltage source U2 is connected with the first input end of programmable operational amplifier OP1, the first end of the 5th switch S 5 is connected with the second input end of programmable operational amplifier OP1, the second end of the second end of the 4th switch S 4 and the 5th switch S 5 is connected with the first input end of the second operational amplifier OP3 respectively, the second input end of the second operational amplifier OP3 is connected with the first end of the 6th switch S 6 with the first end of the second capacitor C 2 respectively, the second end of the 6th switch S 6 is connected with the output terminal of the second operational amplifier OP3, the output terminal of the second operational amplifier OP3 is also connected with the input end of the 3rd phase inverter INV3, the output terminal of the 3rd phase inverter INV3 is connected with the input end of the 4th phase inverter INV4, the output terminal of the 4th phase inverter INV4 is connected with the input end of the second d type flip flop ffdf2, the first output terminal of described the second d type flip flop ffdf2 is connected with the second input end of signal output logic circuit 213,

Wherein, second switch S2, the 3rd switch S 3, the 5th switch S 5 and the 6th switch S 6 are controlled by the signal of the first clock CLK1 output, the first switch S 1 and second switch S2 are controlled by the inversion signal of the signal of the output of the first clock CLK1, wherein, the signal of controlling the first switch S 1 is the signal that the signal of the first clock CLK1 output is exported after the 5th phase inverter INV5, and the signal of controlling second switch S2 is that the signal of the first clock CLK1 output is through the signal of phase inverter INV6 output.The signal that the first d type flip flop ffdf1 and the second d type flip flop ffdf2 are exported by second clock CLK2 is controlled.

Concrete, the first comparator circuit 211 is for comparing the comparator circuit of VP and VN+Ve1 voltage, and wherein, the first voltage source U1 is used for providing Ve1, Ve1 >=0.When VP is greater than VN+Ve1, the output voltage V H of the first comparator circuit 211 exports high level; When VP is not more than VN+Ve1, VH output low level.When the first clock CLK1 output high level, second switch S2 and the 3rd switch S 3 conductings, VN is connected to the first input end of the first operational amplifier OP2, the output terminal of the first operational amplifier OP2 is connected to the negative-phase input of the first operational amplifier OP2, now the misalignment voltage Vos1 of VN and the first operational amplifier OP2 is stored in the first capacitor C 1, and the voltage in the first capacitor C 1 is VN+Ve1-Vos1.When the first clock CLK1 output low level, the first switch S 1 conducting, second switch S2 and the 3rd switch S 3 are turned off, now the first operational amplifier OP2 is operated in comparison state, compare the voltage (VN+Ve1-Vos1) in VP and the first capacitor C 1, the misalignment voltage Vos1 of the first operational amplifier OP2 is constant, so relatively VP is to compare VP and VN+Ve1 with actual effect (VN+Ve1-Vos1).Comparative result is latched into output VH by the first d type flip flop ffdf1.Wherein, the negative edge of the signal of second clock CLK2 output need shift to an earlier date a period of time than the negative edge of the inversion signal of the signal of the first clock CLK1 output, 100nS for example, also can be other times, as long as meet the negative edge of the signal of second clock CLK2 output, need shift to an earlier date than the negative edge of the inversion signal of the signal of the first clock CLK1 output, and avoid sample error.

In like manner, the second comparator circuit 212 for VP+Ve2 relatively and VN(, comparison VP and VN-Ve2) circuit, wherein, second voltage source U2 is used for providing Ve2, Ve2 >=0.When VP+Ve2 is less than VN (when VP is less than VN-Ve2), the output voltage V L output low level of the second comparator circuit 212; When VP+Ve2 is not less than VN (when VP is not less than VN-Ve2), VL exports high level.The principle of the second comparator circuit 212 is identical with the principle of the first comparator circuit 211, does not repeat them here.Signal output logic circuit 213 is at the level of each VH of clock negative edge detection and VL, if VH is high level, by the adjustment signal D of output ₀～D _n-1add 1; If VL is low flat, by the adjustment signal D of output ₀～D _n-1subtract 1.If VH is low level and VL is high level, keep the adjustment signal D of output ₀～D _n-1constant.Certainly can also detect by the mode of rising edge clock the level of VH and VL.

It should be noted that, the signal output logic circuit 213 in the utility model embodiment can adopt any logical circuit that can realize above-mentioned functions to realize, and the utility model embodiment does not limit this.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 4.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

Current mirror, this current mirror comprises a NMOS pipe MN1 and the 2nd NMOS pipe MN2;

The one PMOS pipe MP1 connects with a NMOS pipe MN1, and the drain electrode of a PMOS pipe MP1 is connected with the grid of a NMOS pipe MN1, and the 2nd PMOS pipe MP2 connects with the 2nd NMOS pipe MN2;

At least one group of PMOS pipe group in parallel with the 2nd PMOS pipe MP2, this PMOS pipe group comprises the PMOS pipe of two series connection, the adjustment signal D of the quantity of PMOS pipe group and 210 outputs of mistuning calibration function circuit ₀～D _n-1number is identical, in PMOS pipe group, source electrode is connected with the grid of PMOS pipe and the adjustment signal output part of mistuning calibration function circuit 210 that the 2nd PMOS pipe MP2 source electrode is connected, and in PMOS pipe group, the drain grid of the PMOS pipe that is connected of drain electrode and the 2nd PMOS pipe MP2 is managed MP2 grid with the 2nd PMOS and is connected;

The 3rd NMOS pipe MN3, the grid of the 3rd NMOS pipe MN3 is connected with the drain electrode of the 2nd PMOS pipe MP2;

Wherein, the grid of the one PMOS pipe MP1 is the first input end of programmable operational amplifier OP1, the grid of the 2nd PMOS pipe MP2 is the second input end of programmable operational amplifier OP1, and the drain electrode of the 3rd NMOS pipe MN3 is the output terminal of programmable operational amplifier OP1.

Adjust signal D ₀～D _n-1control respectively the conducting of the PMOS pipe (that is, MPS1～MPSn) being connected with the 2nd PMOS pipe MP2 source electrode with source electrode at least one group of PMOS pipe group or the number that cut-off changes PMOS pipe in parallel with the 2nd PMOS pipe MP2 in PMOS pipe MP21～MP2n.The number that PMOS manages the PMOS pipe that is parallel to the 2nd PMOS pipe MP2 in MP21～MP2n is more, Equivalent conjunction is larger in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1, the number that PMOS manages the PMOS pipe that is parallel to the 2nd PMOS pipe MP2 in MP21～MP2n is fewer, and Equivalent conjunction is less in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1.That is to say, the number that PMOS manages the PMOS pipe that is parallel to the 2nd PMOS pipe MP2 in MP21～MP2n is more, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the number that PMOS manages the PMOS pipe that is parallel to the 2nd PMOS pipe MP2 in MP21～MP2n is fewer, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, PMOS can be managed to MPS1～MPSn and omit, directly will adjust signal D ₀～D _n-1receive the grid of PMOS pipe MP21～MP2n, to control the number that is parallel to the PMOS pipe of the 2nd PMOS pipe MP2 in PMOS pipe MP21～MP2n; Or PMOS is managed to MPS1～MPSn and omit, PMOS is managed to the PMOS Digital Signals switch in parallel in MP21～MP2n, adjust signal D ₀～D _n-1control figure Signal-controlled switch, to control the number that is parallel to the PMOS pipe of the 2nd PMOS pipe MP2 in PMOS pipe MP21～MP2n.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 5.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

At least one group of PMOS pipe group in parallel with a PMOS pipe MP1, this PMOS pipe group comprises the PMOS pipe of two series connection, the adjustment signal D of the quantity of PMOS pipe group and 210 outputs of mistuning calibration function circuit ₀～D _n-1number is identical, the grid of PMOS pipe and the adjustment signal D of mistuning calibration function circuit 210 that in PMOS pipe group, source electrode is connected with a PMOS pipe MP1 source electrode ₀～D _n-1output terminal is connected, and in PMOS pipe group, the drain grid of the PMOS pipe that is connected of drain electrode and a PMOS pipe MP1 is connected with the grid of a PMOS pipe MP1;

The 3rd NMOS pipe MN3, the grid of the 3rd NMOS pipe MN3 is connected with the source electrode of the 2nd PMOS pipe MP2;

Adjust signal D ₀～D _n-1control respectively the conducting of the PMOS pipe (that is, MPS1～MPSn) being connected with a PMOS pipe MP1 source electrode with source electrode at least one group of PMOS pipe group or the number that cut-off changes PMOS pipe in parallel with a PMOS pipe MP1 in PMOS pipe MP11～MP1n.The number that PMOS manages the PMOS pipe that is parallel to a PMOS pipe MP1 in MP11～MP1n is more, Equivalent conjunction is larger in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1, the number that PMOS manages the PMOS pipe that is parallel to a PMOS pipe MP1 in MP11～MP1n is fewer, and Equivalent conjunction is less in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1.That is to say, the number that PMOS manages the PMOS pipe that is parallel to a PMOS pipe MP1 in MP11～MP1n is more, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the number that PMOS manages the PMOS pipe that is parallel to a PMOS pipe MP1 in MP11～MP1n is fewer, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, PMOS can be managed to MPS1～MPSn and omit, directly will adjust signal D ₀～D _n-1receive the grid of PMOS pipe MP11～MP1n, to control the number that is parallel to the PMOS pipe of a PMOS pipe MP1 in PMOS pipe MP11～MP1n; Or PMOS is managed to MPS1～MPSn and omit, PMOS is managed to the PMOS Digital Signals switch in parallel in MP11～MP1n, adjust signal D ₀～D _n-1control figure Signal-controlled switch, to control the number that is parallel to the PMOS pipe of a PMOS pipe MP1 in PMOS pipe MP11～MP1n.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 6.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

The one PMOS pipe MP1 connects with a NMOS pipe MN1, and the source electrode of a PMOS pipe MP1 is connected with the grid of a NMOS pipe MN1, and the 2nd PMOS pipe MP2 connects with the 2nd NMOS pipe MN2;

At least one group of NMOS pipe group in parallel with a NMOS pipe MN1, this NMOS pipe group comprises the NMOS pipe of two series connection, the adjustment signal D of the quantity of NMOS pipe group and 210 outputs of mistuning calibration function circuit ₀～D _n-1number is identical, the grid of NMOS pipe and the adjustment signal D of mistuning calibration function circuit 210 that in NMOS pipe group, drain electrode drains and is connected with a NMOS pipe MN1 ₀～D _n-1output terminal is connected, and the grid of the NMOS pipe that in NMOS pipe group, source electrode is connected with a NMOS pipe MN1 source electrode is connected with the grid of a NMOS pipe NM1;

Adjust signal D ₀～D _n-1control respectively at least one group of NMOS pipe group with drain electrode and a NMOS pipe MN1 the drain conducting of the NMOS pipe (that is, MNS1～MNSn) that is connected or the number that cut-off changes NMOS pipe in parallel with a NMOS pipe MN1 in NMOS pipe MN11～MN1n.The number that NMOS manages the NMOS pipe that is parallel to a NMOS pipe MN1 in MP11～MP1n is more, Equivalent conjunction is larger in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1, the number that NMOS manages the NMOS pipe that is parallel to a NMOS pipe MN1 in MN11～MN1n is fewer, and Equivalent conjunction is less in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1.That is to say, the number that NMOS manages the NMOS pipe that is parallel to a NMOS pipe MN1 in MN11～MN1n is more, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the number that NMOS manages the NMOS pipe that is parallel to a NMOS pipe MN1 in MN11～MN1n is fewer, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, NMOS can be managed to MNS1～MNSn and omit, directly will adjust signal D ₀～D _n-1receive the grid of NMOS pipe MN11～MN1n, to control the number that is parallel to the NMOS pipe of a NMOS pipe MN1 in NMOS pipe MN11～MN1n; Or NMOS is managed to MNS1～MNSn and omit, NMOS is managed to the NMOS Digital Signals switch in parallel in MN11～MN1n, adjust signal D ₀～D _n-1control figure Signal-controlled switch, to control the number that is parallel to the NMOS pipe of a NMOS pipe MN1 in NMOS pipe MN11～MN1n.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 7.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

At least one group of NMOS pipe group in parallel with the 2nd NMOS pipe MN2, this NMOS pipe group comprises the NMOS pipe of two series connection, the adjustment signal D of the quantity of NMOS pipe group and 210 outputs of mistuning calibration function circuit ₀～D _n-1number is identical, the grid of NMOS pipe and the adjustment signal D of mistuning calibration function circuit 210 that in NMOS pipe group, drain electrode drains and is connected with the 2nd NMOS pipe MN2 ₀～D _n-1output terminal is connected, and the grid of the NMOS pipe that in NMOS pipe group, source electrode is connected with the 2nd NMOS pipe MN2 source electrode is connected with the grid of the 2nd NMOS pipe NM2;

Adjust signal D ₀～D _n-1control respectively at least one group of NMOS pipe group with drain electrode and the 2nd NMOS pipe MN2 the drain conducting of the NMOS pipe (that is, MNS1～MNSn) that is connected or the number that cut-off changes NMOS pipe in parallel with the 2nd NMOS pipe MN2 in NMOS pipe MN21～MN2n.The number that NMOS manages the NMOS pipe that is parallel to the 2nd NMOS pipe MN2 in MN21～MN2n is more, Equivalent conjunction is larger in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1, the number that NMOS manages the NMOS pipe that is parallel to the 2nd NMOS pipe MN2 in MN21～MN2n is fewer, and Equivalent conjunction is less in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1.That is to say, the number that NMOS manages the NMOS pipe that is parallel to the 2nd NMOS pipe MN2 in MN21～MN2n is more, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the number that NMOS manages the NMOS pipe that is parallel to the 2nd NMOS pipe MN2 in MN21～MN2n is fewer, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, NMOS can be managed to MNS1～MNSn and omit, directly will adjust signal D ₀～D _n-1receive the grid of NMOS pipe MN21～MN2n, to control the number that is parallel to the NMOS pipe of the 2nd NMOS pipe MN2 in NMOS pipe MN21～MN2n; Or NMOS is managed to MNS1～MNSn and omit, NMOS is managed to the NMOS Digital Signals switch in parallel in MN21～MN2n, adjust signal D ₀～D _n-1control figure Signal-controlled switch, to control the number that is parallel to the NMOS pipe of the 2nd NMOS pipe MN2 in NMOS pipe MN21～MN2n.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 8.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

At least one group of NMOS pipe group in parallel with the 3rd NMOS pipe MN3, this NMOS pipe group comprises the NMOS pipe of two series connection, the adjustment signal D of the quantity of NMOS pipe group and 210 outputs of mistuning calibration function circuit ₀～D _n-1number is identical, the grid of NMOS pipe and the adjustment signal D of mistuning calibration function circuit 210 that in NMOS pipe group, drain electrode drains and is connected with the 3rd NMOS pipe MN3 ₀～D _n-1output terminal is connected, and the grid of the NMOS pipe that in NMOS pipe group, source electrode is connected with the 3rd NMOS pipe MN3 source electrode is connected with the 3rd NMOS pipe MN3 grid;

Adjust signal D ₀～D _n-1control respectively at least one group of NMOS pipe group with drain electrode and the 3rd NMOS pipe MN3 the drain conducting of the NMOS pipe (that is, MNS1～MNSn) that is connected or the number that cut-off changes NMOS pipe in parallel with the 3rd NMOS pipe MN3 in NMOS pipe MN31～MN3n.The number that NMOS manages the NMOS pipe that is parallel to the 3rd NMOS pipe MN3 in MN31～MN3n is more, Equivalent conjunction is larger in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1, the number that NMOS manages the NMOS pipe that is parallel to the 3rd NMOS pipe MN3 in MN31～MN3n is fewer, and Equivalent conjunction is less in the transistor breadth length ratio of the second input end of programmable operational amplifier OP1.That is to say, the number that NMOS manages the NMOS pipe that is parallel to the 3rd NMOS pipe MN3 in MN31～MN3n is more, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the number that NMOS manages the NMOS pipe that is parallel to the 3rd NMOS pipe MN3 in MN31～MN3n is fewer, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, NMOS can be managed to MNS1～MNSn and omit, directly will adjust signal D ₀～D _n-1receive the grid of NMOS pipe MN31～MN3n, to control the number that is parallel to the NMOS pipe of the 3rd NMOS pipe MN3 in NMOS pipe MN31～MN3n; Or NMOS is managed to MNS1～MNSn and omit, NMOS is managed to the NMOS Digital Signals switch in parallel in MN31～MN3n, adjust signal D ₀～D _n-1control figure Signal-controlled switch, to control the number that is parallel to the NMOS pipe of the 3rd NMOS pipe MN3 in NMOS pipe MN31～MN3n.

Alternatively, the specific implementation of programmable operational amplifier OP1 as shown in Figure 9.

Programmable operational amplifier OP1 comprises:

The one PMOS pipe MP1 and the 2nd PMOS pipe MP2;

Between the source electrode of the source electrode of the one PMOS pipe MP1 and the 2nd PMOS pipe MP2, be in series with resistance string, PMOS pipe in parallel on each resistance in this resistance string, the adjustment number of signals of the resistance quantity in resistance string and mistuning calibration function circuit 210 outputs is identical, is connected in parallel on the grid of each the ohmically PMOS pipe in resistance string and the adjustment signal output part of mistuning calibration function circuit 210 is connected;

Adjust signal D ₀～D _n-1control respectively the conducting of PMOS pipe MPS1～MPSn or the resistance value that cut-off changes the resistance string of connecting with the 2nd PMOS pipe MP2.The resistance value of the resistance string of connecting with the 2nd PMOS pipe MP2 is less, the voltage VO of the output terminal of programmable operational amplifier OP1 is higher, the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is higher, the resistance value of the resistance string of connecting with the 2nd PMOS pipe MP2 is larger, the voltage VO of the output terminal of programmable operational amplifier OP1 is lower, and the voltage VN of the second input end that is equivalent to programmable operational amplifier OP1 is lower.

Be understandable that, resistance string can be omitted, PMOS pipe MPS1～MPSn is directly connected with the 2nd PMOS pipe MP2, by the conducting resistance that PMOS manages in MPS1～MPSn, replace resistance string.

In addition, only with power supply and the PMOS pipe source electrode of MP1, be connected to example with the tie point of resistance string and describe in this example, be understandable that, the source electrode that power supply also can be managed MP2 with the 2nd PMOS be connected with the tie point of resistance string.

By the utility model, embodiment provides voltage follower circuit, the voltage of the first input end of the programmable operational amplifier that the mistuning calibration function circuit that this voltage follower circuit comprises comprises this voltage follower circuit and the voltage of the second input end compare, according to comparative result, signal is adjusted in output, this programmable operational amplifier is adjusted the voltage of the second input end of this programmable operational amplifier according to adjustment signal, to reduce the misalignment voltage of this programmable operational amplifier.The voltage follower circuit that the utility model embodiment provides can be along with the variation of the voltage of programmable operational amplifier first input end and/or the voltage of the second input end, adjust at any time the voltage of the second input end, within the misalignment voltage of this programmable operational amplifier is controlled to very little scope.

For example, along with the programmable operational amplifier increase of service time, the variation of ambient temperature or the impact of other extraneous physical factors, the misalignment voltage of the programmable operational amplifier in voltage follower circuit of the prior art may be increasing, and within the voltage follower circuit that the utility model embodiment provides can be controlled at less scope by the misalignment voltage of programmable operational amplifier all the time.

Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only embodiment of the present utility model; and be not used in and limit protection domain of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.

Claims

1. an improved voltage follower circuit, is characterized in that, described voltage follower circuit comprises: mistuning calibration function circuit and programmable operational amplifier;

2. voltage follower circuit according to claim 1, is characterized in that, described mistuning calibration function circuit comprises: the first comparator circuit, the second comparator circuit and signal output logic circuit;

Described the first comparator circuit for the voltage that judges the voltage of first input end of described programmable operational amplifier and whether be greater than the second input end and predefined the first error voltage threshold value with;

Described the second comparator circuit is for judging whether the voltage of first input end of described programmable operational amplifier is less than the poor of the voltage of the second input end and predefined the second error voltage threshold value;

When the voltage of the first input end of described programmable operational amplifier be greater than the voltage of the second input end and predefined the first error voltage threshold value and time, described signal output logic circuit is adjusted the adjustment signal of its output so that the voltage of the second input end of described programmable operational amplifier is increased;

When the voltage of the first input end of described programmable operational amplifier is less than the voltage of the second input end and predefined the second error voltage threshold value poor, described signal output logic circuit is adjusted the adjustment signal of its output so that the voltage of the second input end of described programmable operational amplifier is reduced;

When the voltage of the first input end of described programmable operational amplifier be not more than the voltage of the second input end and predefined the first error voltage threshold value and, and when the voltage of the first input end of described programmable operational amplifier is not less than the voltage of the second input end and predefined the second error voltage threshold value poor, described programmable operational amplifier keeps the voltage of the second input end of described programmable operational amplifier constant according to the adjustment signal of described signal output logic circuit output.

3. voltage follower circuit according to claim 2, is characterized in that,

Described the first comparator circuit comprises: the first switch, second switch, the 3rd switch, the first operational amplifier, the first electric capacity, the first phase inverter, the second phase inverter, the first d type flip flop and the first voltage source;

Wherein, the first end of described the first switch is connected with the first input end of described programmable operational amplifier, the first end of described second switch is connected with the positive pole of described the first voltage source, the negative pole of described the first voltage source is connected with the second input end of described programmable operational amplifier, the second end of described the first switch and the second end of second switch are connected with the first input end of described the first operational amplifier respectively, the second input end of described the first operational amplifier is connected with the first end of the 3rd switch with the first end of the first electric capacity respectively, the second end of described the 3rd switch is connected with the output terminal of described the first operational amplifier, the output terminal of described the first operational amplifier is also connected with the input end of described the first phase inverter, the output terminal of described the first phase inverter is connected with the input end of described the second phase inverter, the output terminal of described the second phase inverter is connected with the input end of described the first d type flip flop, the first output terminal of described the first d type flip flop is connected with the first input end of described signal output logic circuit,

Described the second comparator circuit comprises: the 4th switch, the 5th switch, the 6th switch, the second operational amplifier, the second electric capacity, the 3rd phase inverter, the 4th phase inverter, the second d type flip flop and second voltage source;

Wherein, the first end of described the 4th switch is connected with the positive pole in described second voltage source, the negative pole in described second voltage source is connected with the first input end of described programmable operational amplifier, the first end of described the 5th switch is connected with the second input end of described programmable operational amplifier, the second end of the second end of described the 4th switch and the 5th switch is connected with the first input end of described the second operational amplifier respectively, the second input end of described the second operational amplifier is connected with the first end of the 6th switch with the first end of the second electric capacity respectively, the second end of described the 6th switch is connected with the output terminal of described the second operational amplifier, the output terminal of described the second operational amplifier is also connected with the input end of described the 3rd phase inverter, the output terminal of described the 3rd phase inverter is connected with the input end of described the 4th phase inverter, the output terminal of described the 4th phase inverter is connected with the input end of described the second d type flip flop, the first output terminal of described the second d type flip flop is connected with the second input end of described signal output logic circuit,

Wherein, described second switch, the 3rd switch, the 5th switch and the 6th switch are controlled by the signal of the first clock output, the signal that described the first switch and the 4th switch are exported after the 5th phase inverter by the signal of described the first clock output is controlled, and the signal that described the first d type flip flop and the second d type flip flop are exported by second clock is controlled.

4. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Current mirror, described current mirror comprises a NMOS pipe and the 2nd NMOS pipe;

A described PMOS pipe and a NMOS pipe string connection, the drain electrode of a described PMOS pipe is connected with the grid of a NMOS pipe, described the 2nd PMOS pipe and the 2nd NMOS pipe string connection;

Manage PMOS pipe group in parallel with described the 2nd PMOS at least one group, the quantity of described PMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described PMOS pipe group, drain electrode is connected with the grid of PMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that the 2nd PMOS pipe drain electrode is connected;

The 3rd NMOS pipe, the grid of described the 3rd NMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe;

Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the output terminal that the drain electrode of described the 3rd NMOS pipe is described programmable operational amplifier.

5. voltage follower circuit according to claim 4, is characterized in that, described PMOS pipe group comprises the PMOS pipe of two series connection, and the grid of the PMOS pipe that in described PMOS pipe group, drain electrode is connected with the 2nd PMOS pipe drain electrode is connected with the grid of described the 2nd PMOS pipe.

6. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Manage PMOS pipe group in parallel with a described PMOS at least one group, the quantity of described PMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described PMOS pipe group, source electrode is connected with the grid of PMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that a PMOS pipe source electrode is connected;

Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the drain electrode of described the 3rd NMOS pipe is the output terminal of described programmable operational amplifier, described PMOS pipe group comprises the PMOS pipe of two series connection, and the grid of the PMOS pipe that in described PMOS pipe group, drain electrode is connected with a PMOS pipe source electrode is connected with the tube grid of a described PMOS.

7. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Manage NMOS pipe group in parallel with a described NMOS at least one group, the quantity of described NMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described NMOS pipe group, drain electrode is connected with the grid of NMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that a NMOS pipe drain electrode is connected;

Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the drain electrode of described the 3rd NMOS pipe is the output terminal of described programmable operational amplifier, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with a NMOS pipe source electrode is connected with the grid of a described NMOS pipe.

8. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Manage NMOS pipe group in parallel with described the 2nd NMOS at least one group, the quantity of described NMOS pipe group is identical with the number of signals of described mistuning calibration function circuit output, and the grid of the NMOS pipe that in described NMOS pipe group, drain electrode is connected with the 2nd NMOS pipe drain electrode is connected with the signal output part of described mistuning calibration function circuit;

Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the drain electrode of described the 3rd NMOS pipe is the output terminal of described programmable operational amplifier, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with the 2nd NMOS pipe source electrode is connected with described the 2nd NMOS tube grid.

9. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Manage NMOS pipe group in parallel with described the 3rd NMOS at least one group, the quantity of described NMOS pipe group is identical with the adjustment number of signals of described mistuning calibration function circuit output, and in described NMOS pipe group, drain electrode is connected with the grid of NMOS pipe and the adjustment signal output part of described mistuning calibration function circuit that the 3rd NMOS pipe drain electrode is connected;

Wherein, the grid of a described PMOS pipe is the first input end of described programmable operational amplifier, the grid of described the 2nd PMOS pipe is the second input end of described programmable operational amplifier, the drain electrode of described the 3rd NMOS pipe is the output terminal of described programmable operational amplifier, described NMOS pipe group comprises the NMOS pipe of two series connection, and the grid of the NMOS pipe that in described NMOS pipe group, source electrode is connected with the 3rd NMOS pipe source electrode is connected with described the 3rd NMOS tube grid.

10. according to arbitrary described voltage follower circuit in claim 1-3, it is characterized in that, described programmable operational amplifier comprises:

The one PMOS pipe and the 2nd PMOS pipe;

Between the source electrode of the source electrode of a described PMOS pipe and described the 2nd PMOS pipe, be in series with resistance string, PMOS pipe in parallel on each resistance in described resistance string, resistance quantity in described resistance string is identical with the adjustment number of signals of described mistuning calibration function circuit output, is connected in parallel on the grid of each the ohmically PMOS pipe in described resistance string and the adjustment signal output part of described mistuning calibration function circuit is connected;