CN102045041B - RC oscillator and its implementation - Google Patents
RC oscillator and its implementation Download PDFInfo
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- CN102045041B CN102045041B CN201110009105.XA CN201110009105A CN102045041B CN 102045041 B CN102045041 B CN 102045041B CN 201110009105 A CN201110009105 A CN 201110009105A CN 102045041 B CN102045041 B CN 102045041B
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Abstract
The invention provides a kind of RC oscillator and its implementation, it obtains charging upper limit voltage and electric discharge lower voltage limit by reference voltage generating circuit, by comparing shaping circuit by this charging upper limit voltage, this electric discharge lower voltage limit and charging/discharging voltage compare and produce charging control signal and discharge control signal, control charge and discharge capacitance in playback circuitry and carry out discharge and recharge, to obtain frequency of oscillation RC oscillator comparatively accurately, because the frequency of oscillation of RC oscillator of the present invention does not rely on reference bias current, and only depend on the electric capacity of resistance and charge and discharge capacitance, so use the resistance of low-temperature coefficient and low-voltage drift and electric capacity can obtain the RC oscillator not relying on temperature and supply voltage.
Description
Technical field
The present invention relates to a kind of oscillator and its implementation, particularly relate to a kind of not temperature dependent, the RC oscillator of supply voltage and its implementation.
Background technology
RC oscillator and resistance-capacitance oscillator (R: resistance; C: electric capacity).Need to use RC oscillator in increasing chip design, along with the progress of technology, also more and more higher to the requirement of RC oscillator, require more and more higher to the adaptability of voltage and temperature while reducing costs.
Fig. 1 is a kind of schematic diagram of traditional RC oscillator, and as shown in Figure 1, traditional RC oscillator comprises inverter (102,104 and 108), electric capacity C1, resistance R1 and rp unit 106.Wherein the input of inverter 102 is coupled to node N
11, its output is coupled to the input of inverter 104, and the output of inverter 104 is coupled to node N
12, electric capacity C1 is coupled to node N
11with N
12between, resistance R1 is coupled to node N
11with node N
13between, rp unit 106 is a NAND gate, and it is coupled to node N
12with node N
13between, make RC oscillator be conducting or not conducting according to enable signal EN, to save power consumption, the input of inverter 108 is coupled to node N
13, its output is in order to produce output signal 110.
But for traditional RC oscillator, its frequency of oscillation is often easily subject to the impact of technique change, variations in temperature and change in voltage and causes error, not easily obtains frequency of oscillation accurately.
In sum, the frequency of oscillation of the RC oscillator of known prior art is subject to the problem that the variable effects such as technique, temperature and voltage cause not easily obtaining accurate frequency of oscillation, therefore, is necessary the technological means proposing to improve in fact, solves this problem.
Summary of the invention
For overcoming the problem not easily obtaining accurate frequency of oscillation that above-mentioned prior art exists, main purpose of the present invention is to provide RC oscillator and its implementation, makes its output frequency not with temperature and mains voltage variations, can produce frequency of oscillation comparatively accurately.
For reaching above-mentioned and other object, a kind of RC oscillator of the present invention, at least comprises:
Mirror-image constant flow source produces circuit, and this mirror-image constant flow source produces circuit and at least produces a reference bias current, the bias current of a M times reference bias current and the bias current of a K times reference bias current;
Reference voltage generating circuit, is connected to this mirror-image constant flow source and produces circuit, and the bias current receiving this M times reference bias current also produces the charging upper limit voltage and electric discharge lower voltage limit that differ in size;
Relatively shaping circuit, being connected to this reference voltage generating circuit and obtaining this charging upper limit voltage and this electric discharge lower voltage limit, producing charging control signal and discharge control signal by this charging upper limit voltage, this electric discharge lower voltage limit being compared with charging/discharging voltage respectively; And
Charge-discharge circuit, be connected to this mirror-image constant flow source and produce circuit, receive the bias current of this K times reference bias current, this charge-discharge circuit carries out charge or discharge to a charge and discharge capacitance under the control of this charging control signal and this discharge control signal, and this charging/discharging voltage produced by this charge and discharge capacitance inputs to this compares shaping circuit.
Further, this mirror-image constant flow source produces circuit and at least comprises a reference current generating circuit, a M times reference bias current generation circuit and a K times of reference bias current generation circuit, and the first nmos pass transistor that wherein this reference current generating circuit is connected by current source and grid leak produces this reference bias current; This M times of reference bias current produces circuit and at least comprises the first PMOS transistor, the second PMOS transistor and the second nmos pass transistor, the drain electrode of this first PMOS transistor is connected with this second nmos transistor drain, grid is jointly connected to it after being connected with this second PMOS transistor grid and drains, this the second nmos pass transistor grid is connected to this current source, source ground; This K times of reference bias current produces circuit and at least comprises the 3rd PMOS transistor and the 3rd nmos pass transistor, 3rd PMOS transistor grid is connected with this first PMOS transistor grid, drain electrode is connected with this charge-discharge circuit, 3rd nmos pass transistor grid is connected to this current source, drain electrode is connected with this charge-discharge circuit, wherein, the breadth length ratio of this second PMOS transistor is M times of this first PMOS transistor, and the breadth length ratio of the 3rd nmos pass transistor is K times of this second nmos pass transistor.
Further, this reference voltage generating circuit at least comprises the first resistance and second resistance of series connection mutually, one end that this first resistance is not connected with this second resistance is connected to the drain electrode of this second PMOS transistor, its common node place produces this charging upper limit voltage, the common node place of this first resistance and this second resistance produces this electric discharge lower voltage limit, this second resistance other end ground connection.
Further, this compares shaping circuit and at least comprises the first comparator, the second comparator and a rest-set flip-flop, this electric discharge lower voltage limit and this charging upper limit voltage are input to the positive input terminal of this first comparator and the negative input end of this second comparator respectively, this charging/discharging voltage is input to the negative input end of this first comparator and the positive input terminal of this second comparator, and, the S that the output of this first comparator and this second comparator is connected to this rest-set flip-flop respectively holds and holds with R, exports this charging control signal and this discharge control signal by this rest-set flip-flop.
Further, this charge-discharge circuit at least comprises this charge and discharge capacitance and interconnective first switch and second switch, one end that this first switch is not connected with this second switch is connected to the drain electrode of the 3rd PMOS transistor, this first switch is connected with this charge and discharge capacitance with this second switch common connecting point, and be jointly connected to the negative input end of this first comparator and the positive input terminal of this second comparator to provide this charging/discharging voltage, this second switch other end is connected to the drain electrode of the 3rd nmos pass transistor, wherein, the disconnection of this first switch is controlled by this charging control signal with closed, the disconnection of this second switch is controlled by this discharge control signal with closed.
Further, this charge-discharge circuit also comprises a dummy load circuit, this dummy load circuit and this first switch, this second switch are connected in parallel between the 3rd PMOS transistor and the 3rd nmos pass transistor, for the overshoot current/voltage avoiding recharge-discharge-charging to change moment.
Further, this dummy load circuit at least comprises the 3rd switch, the 4th nmos pass transistor, the 4th switch and the 4th PMOS transistor, 3rd switch one end is connected to the 3rd PMOS transistor drain electrode, the other end is connected to the 4th nmos transistor drain, the 4th nmos pass transistor source ground; One end of 4th switch is connected to the 3rd nmos transistor drain, and the other end is connected to the 4th PMOS transistor drain electrode, and the 4th PMOS transistor source electrode connects supply voltage.
For realizing above-mentioned and other object, present invention also offers a kind of implementation method of RC oscillator, comprising the steps:
The delay of this first comparator and this second comparator is designed to the cycle of oscillation much smaller than this RC oscillator;
Adopt the resistance capacitance of low-temperature coefficient and low voltage coefficient; And
Adopt correcting circuit adjustment direct current offset.
Further, this delay is preferably less than 1/50th of this cycle of oscillation.
Further, the resistance of this low-temperature coefficient and low voltage coefficient obtains by polycrystalline resistor technique being combined with the resistance technique of positive temperature coefficient.
Compared with prior art, a kind of RC oscillator of the present invention and its implementation adopt two high-speed comparators to carry out detection oscillator signal, control circuit carries out charge or discharge to charge and discharge capacitance, two reference voltages (charging upper limit voltage and electric discharge lower voltage limit) used due to high-speed comparator are proportional to reference bias current M bias current doubly by one and flow through resistance and produce, charging and discharging currents is then proportional to reference bias current K doubly, therefore the frequency of oscillation of RC oscillator of the present invention does not rely on reference bias current, and only depend on the electric capacity of resistance and charge and discharge capacitance, so use the resistance of low-temperature coefficient and low-voltage drift and electric capacity can obtain the RC oscillator not relying on temperature and supply voltage.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of traditional RC oscillator;
Fig. 2 is the structural representation of the preferred embodiment of RC oscillator of the present invention;
Fig. 3 is the frequency-temperature characteristic figure of RC oscillator of the present invention preferred embodiment.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this specification also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 1 is the structural representation of a kind of RC oscillator of the present invention.As shown in Figure 1, a kind of RC oscillator of the present invention comprises: mirror-image constant flow source produces circuit 101, reference voltage generating circuit 102, compares shaping circuit 103 and charge-discharge circuit 104.
Fig. 2 is the schematic diagram of the preferred embodiment of a kind of RC oscillator of the present invention, please also refer to Fig. 1 and Fig. 2, mirror-image constant flow source produces circuit 101 and comprises reference current generating circuit, M times of bias current generating circuit and K times of bias current generating circuit, reference current generating circuit is for generation of reference bias current Ibias, it comprises a current source and the first nmos pass transistor MN1, first nmos pass transistor MN1 source ground, grid is connected to form bias current with after drain electrode short circuit with current source Ibias, in present pre-ferred embodiments, the breadth length ratio of the first nmos pass transistor MN1 is W
mN1/ L
mN1, it is M bias current doubly that M times of bias current generating circuit 202 is proportional to reference bias current Ibias for generation of one, it breadth length ratio comprising the first PMOS transistor MP1, the second PMOS transistor MP2 and the second nmos pass transistor MN2, the second PMOS transistor MP2 is that the M of the first PMOS transistor is doubly (if the first PMOS transistor breadth length ratio is W
mP1/ L
mP1, then the breadth length ratio W of the second PMOS transistor MP2
mP2/ L
mP2be then M* (W
mP1/ L
mP1)), second nmos transistor drain drains with the first PMOS transistor MP1 and is connected, its grid is connected to current source Ibias, source ground, be connected to the drain electrode of the first PMOS transistor PMOS transistor after first PMOS transistor MP1 and the second PMOS transistor grid short circuit, source electrode connects power source voltage Vcc, K times of bias current generating circuit 203, being proportional to reference bias current Ibias for generation of one is K bias current doubly, it comprises the 3rd PMOS transistor MP3 and the 3rd nmos pass transistor, 3rd PMOS transistor MP3 grid is connected to the drain electrode of the first PMOS transistor MP1 after connecting with the first PMOS transistor MP1 grid, the 3rd PMOS transistor MP3 breadth length ratio W
mP3/ L
mP3be K times of the first PMOS transistor MP1, the 3rd nmos pass transistor source ground, grid is connected to current source Ibias, drain electrode is connected to charge-discharge circuit 104, and wherein, the first nmos pass transistor is identical with the breadth length ratio of the second nmos pass transistor, but not as limit, the breadth length ratio W of the 3rd nmos pass transistor
mN2/ L
mN2the K being the second nmos pass transistor doubly, is K* (W
mN2/ L
mN2).In present pre-ferred embodiments, the relation between the width of each transistor and length can be comprehensively: L
mP1=L
mP2=L
mP3; W
mP2/ M=W
mP3/ K=W
mP1; L
mN1=L
mN2=L
mN3; K*W
mN2=W
mN3.
Reference voltage generating circuit 102 is connected to M times of bias current generating circuit, for generation of two reference voltages (charging upper limit voltage V
refHwith electric discharge lower voltage limit Vv
refL) to comparing shaping circuit 104, in present pre-ferred embodiments, reference voltage generating circuit 102 at least comprises resistance R1 and the R2 of two series connection, one end that resistance R1 is not connected with resistance R2 is connected to the drain electrode of the second PMOS transistor, one end ground connection that resistance R2 is not connected with resistance R1, wherein, the intermediate node of resistance R1 and the second PMOS transistor produces charging upper limit voltage V
refH, the intermediate node of resistance R1 and R2 produces electric discharge lower voltage limit V
vrefL, export to and compare shaping circuit 103.
Relatively shaping circuit 103 at least comprises two comparators (COMP1, COMP2) and a rest-set flip-flop, in present pre-ferred embodiments, comparator COMP1 and COMP2 is high-speed comparator, the positive input terminal of comparator COMP1 is connected to reference voltage generating circuit 102, for obtaining electric discharge lower voltage limit V
refL, the negative input end of comparator COMP2 is also connected to reference voltage generating circuit 102, for obtaining charging upper limit voltage V
refHthe negative input end of comparator COMP1 and the positive input terminal of comparator COMP2 are connected to charge-discharge circuit 104 respectively to obtain charging/discharging voltage, and the S that the output of comparator COMP1 and comparator COMP2 is connected to rest-set flip-flop respectively holds and holds with R, export charging control signal charge and discharge control signal discharge by rest-set flip-flop, compare shaping circuit 103 mainly through charging upper limit voltage V
refH, electric discharge lower voltage limit V
refLthe charging/discharging voltage produced with charge-discharge circuit 104 compares, and produces the charge and discharge control signal controlling charge-discharge circuit 104.Discharge and recharge is carried out to control charge-discharge circuit 104.
Charge-discharge circuit 104 is connected to K times of bias current generating circuit 203, specifically, charge-discharge circuit 104 is connected to the drain electrode that K times of biasing circuit produces circuit 203 the 3rd PMOS transistor MP3, reference bias current IbiasK charging and discharging currents is doubly proportional to obtain, it at least comprises two switches (K1 and K2) and a charge and discharge capacitance C of series connection mutually, wherein, the disconnection of K switch 1 and K2 controls by comparing charging control signal charge that shaping circuit 103 exports and discharge control signal discharge respectively with closed, one end that K switch 1 is not connected with K switch 2 is connected to the drain electrode of the 3rd PMOS transistor MP3, and one end that K switch 2 is not connected with K1 is connected to the drain electrode of the 3rd nmos pass transistor MN3, K switch 1 is connected to charge and discharge capacitance C with the common node of K2, and be connected to the negative input end of comparator COMP1 and the positive input terminal of comparator COMP2, the other end ground connection of charge and discharge capacitance C.
For the overshoot current/voltage avoiding recharge-discharge-charging to change moment, the charge-discharge circuit 104 of present pre-ferred embodiments also can comprise a dummy load circuit 204.Dummy load circuit 204 and K switch 1, K2 are connected in parallel between the 3rd PMOS transistor MP3 and the 3rd nmos pass transistor MN3, it at least comprises K switch 3, the 4th NNOS transistor MN4, K switch 4 and the 4th PMOS transistor MP4, one end of K switch 3 is connected to the 3rd PMOS transistor MP3 drain electrode, the other end is connected to the drain electrode of the 4th nmos pass transistor MN4, the 4th nmos pass transistor source ground; One end of K switch 4 is connected to the drain electrode of the 3rd nmos pass transistor MN3, and the other end is connected to the drain electrode of the 4th PMOS transistor MP4, and the 4th PMOS transistor source electrode connects power source voltage Vcc.
The operation principle will Fig. 2 being coordinated to further illustrate present pre-ferred embodiments below: when the charging/discharging voltage of charge and discharge capacitance C is lower than electric discharge lower voltage limit V
refLtime, comparator COMP1 exports high level, rest-set flip-flop anode exports the charging control signal charge (charge is " 1 ") of high level, now K switch 1 closes with K switch 4, K switch 3 and K switch 4 disconnect, electric current is via the 3rd PMOS transistor MP3 and K switch 1 to capacitor charging, and charging current is KI
bias, another road electric current provides electric current to the 3rd nmos pass transistor MN3 via K switch 4 and the 4th PMOS transistor, to ensure the continuity of the 3rd nmos pass transistor state, reduces transient effect; Charging/discharging voltage along with charge and discharge capacitance C is increased to and is greater than electric discharge lower voltage limit V
refLand be less than charging upper limit voltage V
refHtime, the output of comparator is " 1 ", and now, rest-set flip-flop keeps current state, continues charging, and when the charging/discharging voltage of charge and discharge capacitance C is higher than charging upper limit voltage V
refHtime, the charging control signal charge that rest-set flip-flop exports is low level, and discharge control signal discharge is that (charge is " 0 " to high level, discharge is " 1 "), then charge and discharge capacitance C starts electric discharge by K switch 2, when charge and discharge capacitance C is discharged to its charging/discharging voltage lower than electric discharge lower voltage limit V
refLtime, then start again charging, so circulation is repeatedly.
To sum up, according to Fig. 2, the following equation about present pre-ferred embodiments frequency of oscillation can be drawn:
Tosc＝((V
refH-V
refL)*C/I
charge+td))+((V
refH-V
refL)*C/I
discharge+td))
V
refH-V
refL＝R1*I*M
I
charge＝I*K
I
discharge＝I*K
In conjunction with above-mentioned equation, can obtain
T
osc＝2*R1*C(M/K)+2*td
Wherein, Tosc is the cycle of oscillation of RC oscillator, V
refH, V
refHfor charging upper limit voltage and electric discharge lower voltage limit, t d is the delay of comparator, and C is the electric capacity of charge and discharge capacitance C, I
chargefor charging current, I
dischargefor discharging current, I is reference bias current, and according to aforesaid equation, the cycle of oscillation of visible RC oscillator of the present invention is only relevant with the delay td of the resistance of resistance R1, the electric capacity of charge and discharge capacitance C and comparator.
So, according to aforesaid equation, in order to obtain the frequency of oscillation of RC oscillator accurately, then realize as follows:
First, td is designed enough little, such as, td < (1/50) * Tosc, usual td is relevant with supply voltage, but enough hour of td, td is usually very little with mains voltage variations, as td < (1/50) * Tosc, almost can ignore, so Tosc then has nothing to do with supply voltage;
Secondly, the resistance capacitance of low-temperature coefficient and low voltage coefficient can be adopted by modern crafts, as rppolyu polycrystalline resistor and MIM (metal-insulator-metal) electric capacity, rppolyu technique is combined with the resistance technique of positive temperature coefficient and can obtains the very low resistance of temperature coefficient, so just can obtain the RC oscillator of frequency of oscillation not temperature dependent and supply voltage;
Finally, because technique change can cause the difference having certain direct current offset between nude film, correcting circuit is adopted to adjust direct current offset.
Fig. 3 is the frequency-temperature characteristic figure of RC oscillator of the present invention preferred embodiment, and it represents the temperature variant situation of present pre-ferred embodiments frequency.Wherein transverse axis is temperature, and the longitudinal axis is the relative change of frequency, and the frequency of visible present pre-ferred embodiments varies with temperature very little, and the frequency of oscillation of RC oscillator of the present invention does not rely on temperature coefficient.
Visible, the present invention really can provide a kind of RC oscillator of accurate generation frequency of oscillation, and its output frequency is not with temperature and mains voltage variations.The present invention carrys out detection oscillator signal by two high-speed comparators, control circuit carries out charge or discharge to charge and discharge capacitance, two reference voltages (charging upper limit voltage and electric discharge lower voltage limit) used due to high-speed comparator are proportional to reference bias current M bias current doubly by one and flow through resistance and produce, charging and discharging currents is then proportional to reference bias current K doubly, therefore the frequency of oscillation of RC oscillator of the present invention does not rely on reference bias current, and only depend on the electric capacity of resistance and charge and discharge capacitance, so use the resistance of low-temperature coefficient and low-voltage drift and electric capacity can obtain the RC oscillator not relying on temperature and supply voltage.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (8)
1. a RC oscillator, at least comprises:
Mirror-image constant flow source produces circuit, and this mirror-image constant flow source produces circuit and at least produces a reference bias current, the bias current of a M times reference bias current and the bias current of a K times reference bias current;
Reference voltage generating circuit, is connected to this mirror-image constant flow source and produces circuit, and the bias current receiving this M times reference bias current also produces the charging upper limit voltage and electric discharge lower voltage limit that differ in size;
Relatively shaping circuit, being connected to this reference voltage generating circuit and obtaining this charging upper limit voltage and this electric discharge lower voltage limit, producing charging control signal and discharge control signal by this charging upper limit voltage, this electric discharge lower voltage limit being compared with charging/discharging voltage respectively; And
Charge-discharge circuit, be connected to this mirror-image constant flow source and produce circuit, receive the bias current of this K times reference bias current, this charge-discharge circuit carries out charge or discharge to a charge and discharge capacitance under the control of this charging control signal and this discharge control signal, and this charging/discharging voltage produced by this charge and discharge capacitance inputs to this compares shaping circuit;
Wherein, the first nmos pass transistor that this reference current generating circuit is connected by current source and grid leak produces this reference current; This M times of reference bias current produces circuit and at least comprises the first PMOS transistor, the second PMOS transistor and the second nmos pass transistor, the drain electrode of this first PMOS transistor is connected with this second nmos transistor drain, grid is jointly connected to it after being connected with this second PMOS transistor grid and drains, this the second nmos pass transistor grid is connected to this current source, source ground; This K times of reference bias current produces circuit and at least comprises the 3rd PMOS transistor and the 3rd nmos pass transistor, 3rd PMOS transistor grid is connected with this first PMOS transistor grid, drain electrode is connected with this charge-discharge circuit, 3rd nmos pass transistor grid is connected to this current source, drain electrode is connected with this charge-discharge circuit, wherein, the breadth length ratio of this second PMOS transistor is M times of this first PMOS transistor, the breadth length ratio of the 3rd PMOS transistor is K times of this first PMOS transistor, and the breadth length ratio of the 3rd nmos pass transistor is K times of this second MOS transistor.
2. RC oscillator as claimed in claim 1, it is characterized in that: this reference voltage generating circuit at least comprises the first resistance and second resistance of series connection mutually, one end that this first resistance is not connected with this second resistance is connected to the drain electrode of this second PMOS transistor, its common node place produces this charging upper limit voltage, the common node place of this first resistance and this second resistance produces this electric discharge lower voltage limit, this second resistance other end ground connection.
3. RC oscillator as claimed in claim 2, it is characterized in that: this compares shaping circuit and at least comprises the first comparator, second comparator and a rest-set flip-flop, this electric discharge lower voltage limit and this charging upper limit voltage are input to the positive input terminal of this first comparator and the negative input end of this second comparator respectively, this charging/discharging voltage is input to the negative input end of this first comparator and the positive input terminal of this second comparator, and, the S that the output of this first comparator and this second comparator is connected to this rest-set flip-flop respectively holds and holds with R, this charging control signal and this discharge control signal is exported by this rest-set flip-flop.
4. RC oscillator as claimed in claim 3, it is characterized in that: this charge-discharge circuit at least comprises this charge and discharge capacitance and interconnective first switch and second switch, one end that this first switch is not connected with this second switch is connected to the drain electrode of the 3rd PMOS transistor, this first switch is connected with this charge and discharge capacitance with this second switch common connecting point, and be jointly connected to the negative input end of this first comparator and the positive input terminal of this second comparator to provide this charging/discharging voltage, this second switch other end is connected to the drain electrode of the 3rd nmos pass transistor, wherein, the disconnection of this first switch is controlled by this charging control signal with closed, the disconnection of this second switch is controlled by this discharge control signal with closed.
5. RC oscillator as claimed in claim 4, it is characterized in that: this charge-discharge circuit also comprises a dummy load circuit, this dummy load circuit and this first switch, this second switch are connected in parallel between the 3rd PMOS transistor and the 3rd nmos pass transistor, for the overshoot current/voltage avoiding recharge-discharge-charging to change moment.
6. RC oscillator as claimed in claim 5, it is characterized in that: this dummy load circuit at least comprises the 3rd switch, the 4th nmos pass transistor, the 4th switch and the 4th PMOS transistor, 3rd switch one end is connected to the 3rd PMOS transistor drain electrode, the other end is connected to the 4th nmos transistor drain, the 4th nmos pass transistor source ground; One end of 4th switch is connected to the 3rd nmos transistor drain, and the other end is connected to the 4th PMOS transistor drain electrode, and the 4th PMOS transistor source electrode connects supply voltage.
7. an implementation method for RC oscillator as claimed in claim 1, comprises the steps:
The delay of comparing shaping circuit is designed to 1/50th of the cycle of oscillation being less than this RC oscillator;
Adopt the resistance capacitance of low-temperature coefficient and low voltage coefficient; And
Adopt correcting circuit adjustment direct current offset.
8. the implementation method of a kind of RC oscillator as claimed in claim 7, is characterized in that: the resistance of this low-temperature coefficient and low voltage coefficient obtains by polycrystalline resistor technique being combined with the resistance technique of positive temperature coefficient.
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| JPH06260837A (en) * | 1993-03-04 | 1994-09-16 | Nec Ic Microcomput Syst Ltd | Oscillation circuit |
| US5656954A (en) * | 1994-11-17 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Current type inverter circuit, current type logic circuit, current type latch circuit, semiconductor integrated circuit, current type ring oscillator, voltage-controlled oscillator and PLL circuit |
| CN101286733A (en) * | 2008-05-26 | 2008-10-15 | 北京中星微电子有限公司 | An oscillator with low voltage and low power consumption |
| CN201222719Y (en) * | 2008-05-27 | 2009-04-15 | 上海复旦微电子股份有限公司 | High-precision ring oscillator |
-
2011
- 2011-01-17 CN CN201110009105.XA patent/CN102045041B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06260837A (en) * | 1993-03-04 | 1994-09-16 | Nec Ic Microcomput Syst Ltd | Oscillation circuit |
| US5656954A (en) * | 1994-11-17 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Current type inverter circuit, current type logic circuit, current type latch circuit, semiconductor integrated circuit, current type ring oscillator, voltage-controlled oscillator and PLL circuit |
| CN101286733A (en) * | 2008-05-26 | 2008-10-15 | 北京中星微电子有限公司 | An oscillator with low voltage and low power consumption |
| CN201222719Y (en) * | 2008-05-27 | 2009-04-15 | 上海复旦微电子股份有限公司 | High-precision ring oscillator |
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| CN102045041A (en) | 2011-05-04 |
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