CN104143968A - On-chip oscillator circuit capable of eliminating control logic delay - Google Patents
On-chip oscillator circuit capable of eliminating control logic delay Download PDFInfo
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Abstract
The invention discloses an on-chip oscillator circuit capable of eliminating control logic delay. The on-chip oscillator circuit mainly comprises a first reference voltage, a second reference voltage, a first charging and discharging current, a first charging and discharging switching group, a first charging and discharging capacitor, a first comparator and a control logic part, wherein the branch of the first charging and discharging capacitor is connected with a first switch tube in series, the first switch tube is in the open state, and the voltage of a starting signal and a power voltage are in positive correlation. According to the on-chip oscillator circuit capable of eliminating control logic delay, influences caused by control logic delay to a clock frequency voltage coefficient and a temperature coefficient can be eliminated, the circuit is especially suitable for the occasion with high clock frequency and big changes of a clock frequency range, the implementation cost is low, and the circuit is simple in structure and easy to implement.
Description
Technical field
The invention belongs to oscillator, particularly a kind of delay circuit of oscillator.
Background technology
Oscillator (OSC) circuit is for providing clock signal at chip, and the oscillator of for example applying on single-chip microcomputer provides the clock signal of a 12MHz, conventionally adopts RC oscillator structure, and concrete circuit diagram as shown in Figure 1.For oscillator structure on the typical sheet of one.This oscillator adopts single comparator configuration, and wherein charging circuit IC0 is to capacitor C 0 top crown charging, and φ 1 is high, and VREF0 connects the anode of comparator C MP; C0 top crown connects and relatively plays negative terminal, bottom crown ground connection; In the time that C0 top crown voltage exceedes VREF0, control logic control logic makes φ 1 for low, and φ 2 is high, thereby discharging current discharges to C0, and VREF1 replaces VREF0 to connect comparator anode; When discharging into C0 top crown and being less than VREF1, φ 1 is high, and φ 2 be low, reenters the cycle that IC0 charges to C0.So go round and begin again, CLK clock signal.Consider the non-ideal factor of control logic, clock cycle T=2*C0* (VREF0-VREF1)/(IC0+IC1)+Tlogic, the time delay that Tlogic is control logic, is an amount with supply voltage and variations in temperature.
The clock cycle of RC oscillator is determined by T=R*C ideally, but owing to there being multiple non-ideal factor to exist, true really not so.The time delay Tlogic that very important non-ideal factor is exactly control logic, therefore a clock cycle T=R*C+Tlogic.In a lot of application scenarios, require on integrated circuit chip clock frequency little with voltage coefficient and temperature coefficient, therefore a lot of structures have been proposed.The for example resistance of serviceability temperature coefficient complementation forms the resistance that temperature coefficient is very little, and the temperature coefficient of T=R*C+Tlogic can reduce greatly like this; Reduce voltage coefficient aspect, thereby can use source of stable pressure to obtain very little voltage coefficient to oscillator power supply etc., but paid the cost of area and power consumption, very inadvisable in the occasion of pursuing low cost low energy consumption; These methods lack the consideration to Tlogic non-ideal factor conventionally; In fact Tlogic is subject to the impact of supply voltage and variations in temperature significantly, and in the time that clock frequency becomes large, during as >20MHz, because the accounting of Tlogic becomes large, its impact can be further remarkable.Although can reduce Tlogic by design optimization as far as possible, its amplitude that can reduce is limited to technique.On the other hand, if the clock signal frequency of oscillator may be many grades can timing, the configuration of optimizing under some frequencies, under other one grade of frequency, because the ratio of Tlogic/T changes, the impact of Tlogic also can change, the consequence causing be exactly its voltage coefficient of clock frequency and the temperature coefficient of different gears be inconsistent, affected reliability.
Summary of the invention
Therefore, primary and foremost purpose of the present invention is to provide pierce circuit on a kind of sheet of eliminating control logic time delay, the means that this pierce circuit can the use low cost low-power consumption voltage coefficient on oscillator clock frequency of control logic time delay and the impact of temperature coefficient in oscillation-damped device effectively, and improve in the time that different frequency is exported the consistency of control logic time delay on clock frequency impact.
Another object of the present invention is to provide pierce circuit on a kind of sheet of eliminating control logic time delay, and this oscillator circuit structure is simple, is easy to realize, and can produce the dysgenic while at elimination logical time delay, effectively reduces production costs.
In order to solve the problems of the technologies described above, the invention provides pierce circuit on a kind of sheet of eliminating control logic time delay, it is characterized in that described upper pierce circuit mainly includes the first reference voltage, the second reference voltage, the first charging and discharging currents, the first charge and discharge switch group, the first charge and discharge capacitance, the first comparator and control logic; Wherein the first reference voltage is electrically connected to the input of the first comparator, and the upper end of the first charge and discharge capacitance branch road is connected to another input of the first comparator, and the lower end of the first charge and discharge capacitance is connected to reference to ground; Control logic control the first charge and discharge switch group is used the first charging and discharging currents that the first charge and discharge capacitance is filled and/or discharged, the top crown voltage of the first charge and discharge capacitance is changed back and forth between the first reference voltage and the second reference voltage, the first comparator outputting oscillation signal; The first charge and discharge capacitance branch road is also connected in series first switching tube, and this first switching tube is in opening state, and the voltage of start signal and supply voltage positive correlation.
The connection of the second reference voltage has multiple, but total effect is to be all the border that limits the top crown voltage of the first charge and discharge capacitance, between the first reference voltage and the second reference voltage.
The size of described the first switching tube, the voltage at switching tube two ends is with the ratio of mains voltage variations absolute value and reference voltage, be time of delay sum absolute value and the ratio of the first charge and discharge capacitance charge or discharge required time 80%～120%.
Specifically, it is exactly the size of switching tube, be make its equivalent resistance and the voltage at the switching tube two ends that the product of charging current of this switching tube of flowing through obtains with the absolute value of the mains voltage variations ratio (difference of first reference voltage and second reference voltage) poor with reference voltage, be the first comparator upset add time of delay control logic overturn time of delay sum with the absolute value of mains voltage variations and the first charge and discharge capacitance with 80%～120% of the ratio of charging and discharging currents charge or discharge required time between above-mentioned two reference voltages.
Further, described the first switching tube is nmos switch pipe, or CMOS complementary switch pipe; The voltage of start signal is supply voltage.
Further, described the first switching tube is serially connected between the first charge and discharge capacitance bottom crown and earth terminal (GND); The first charge and discharge capacitance top crown connects comparator input terminal.
Pierce circuit on the sheet of described elimination control logic time delay, also comprises a road reference voltage; Above-mentioned reference voltage You Yi road reference current flow through reference resistance produce; On described reference resistance, be connected in series another switching tube, this another switching tube is identical with the first switching tube type.
Pierce circuit on the sheet of described elimination control logic time delay, also include the second charge and discharge capacitance and be serially connected in earth terminal and this second charge and discharge capacitance between second switch pipe, second switch is effective in to regulate the clock frequency of oscillator; Described second switch pipe and the first switching tube same type; The ratio of equivalent resistance under equivalent resistance and the first switching tube opening under this second switch pipe opening, be the first charging capacitor and the second charging capacitor ratio 80%～120%.
Pierce circuit on the sheet of described elimination control logic time delay, also includes the 3rd switching tube, and itself and the first paralleled power switches, be subject to a frequency adjustment control signal control folding; The second charging and discharging currents, is subject to the control of above-mentioned same frequency adjustment control signal, for being superimposed upon aforementioned the first charging and discharging currents, for regulating clock frequency; In the time that the second charging and discharging currents is superimposed upon on the first charging and discharging currents, the 3rd switching tube closure; Otherwise the 3rd switching tube disconnects; The size Selection of the 3rd switching tube is that its closed front and back paralleling switch pipe both end voltage is remained unchanged substantially.
Further, above-mentioned the second charging and discharging currents, described charging and discharging currents produces by current mirror, and Qie Yi road current mirror is parallel on the branch road that produces the second charging and discharging currents, is used for regulating charging and discharging currents.
Further, the each auxiliary switch in parallel of the first switching tube and second switch pipe, described auxiliary switch is subject to the control of frequency adjustment control signal, when frequency adjustment control signal is while being high, the closed conducting of above-mentioned auxiliary switch.
Further, on the sheet of described elimination control logic time delay, pierce circuit also comprises the second comparator, the second charge and discharge switch group, the second charge and discharge capacitance, and the second reference voltage is earth terminal; Wherein the first charge and discharge switch group comprises charge switch and discharge switch, and two switches are connected in series, upper termination charging and discharging currents after serial connection, and lower termination earth terminal, serial connection connecting place connects the top crown of the first charge and discharge capacitance, connects the input of the first comparator simultaneously; Another input termination first reference voltage of the first comparator; The connected mode of the second charge and discharge switch group, the second charge and discharge capacitance and the second comparator is also like this; Control logic is according to the output control switch group action of comparator, in the time that the first charge and discharge capacitance top crown voltage is greater than the first reference voltage, the first comparator one overturns, the charge switch of control logic control the first charge and discharge switch group disconnects, discharge switch closure, and the first charge and discharge capacitance one top crown is discharged to reference to ground; Charge switch closure, the discharge switch of controlling the second charge and discharge switch group disconnect simultaneously, to the top crown charging of the second charge and discharge capacitance; In the time that the second charge and discharge capacitance top crown voltage is greater than the first reference voltage, the second comparator upset, the charge switch of control logic control the second charge and discharge switch group disconnects, discharge switch closure, and the second charge and discharge capacitance top crown is discharged to reference to ground; Charge switch closure, the discharge switch of controlling the first charge and discharge switch group disconnect simultaneously, to the first charge and discharge capacitance top crown charging; So go round and begin again, control logic produces oscillator signal output.
The pierce circuit of the present invention's design, can eliminate the impact of control logic time delay on clock frequency voltage coefficient and temperature coefficient, particularly high in clock frequency, and reference clock frequency changes occasion greatly, can effectively reduce voltage coefficient and the temperature coefficient of clock frequency, and it is low to realize cost, circuit structure is simple, is easy to realize.
Brief description of the drawings
Fig. 1 is the circuit diagram of prior art.
Fig. 2 is the circuit diagram of the first implementation of implementing of the present invention.
Fig. 3 is the circuit diagram of the second implementation of implementing of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
Referring to Fig. 2, the pierce circuit of control logic time delay that has been depicted as elimination that the present invention realizes, wherein reference current IREF1 shines upon by current mirror M1 to M2, and the R1 that flows through produces the first reference voltage VREF2, and the second reference voltage is with reference to ground; Current mirror M3 produces the first charging and discharging currents IC2, one of first charge and discharge switch group is made up of PMOS switch MS1+NMOS switch MS2, termination current mirror M3 drain electrode in the first charge and discharge switch group, lower end ground connection, the top crown of indirect the first charge and discharge capacitance C1 and the negative terminal of the first comparator C MP1; Being formed by PMOS switch MS3+NMOS switch MS4 of the second charge and discharge switch group, upper termination current mirror M3 drain electrode, lower end ground connection, the negative terminal of indirect the second charge and discharge capacitance C2 top crown and the second comparator C MP2; Between charge and discharge capacitance C1 bottom crown and ground, be connected in series a cmos switch SW1 (the first switching tube), between charge and discharge capacitance C2 bottom crown and ground, be connected in series a cmos switch SW2 (second switch pipe); SW1 and SW2 are in normal closure state, and the anode NMOS of SW1 and SW2 controls voltage and meets power vd D, and negative terminal PMOS controls voltage ground connection (GND); The positive termination reference voltage VREF2 of comparator C MP1 and CMP2, output meets control logic contro logic1; This control logic comprises a rest-set flip-flop and a buffer stage composition; In the time that CMP2 negative terminal voltage is greater than VREF2, φ 22 uprises, MS4 conducting, and MS3 disconnects, and C2 starts electric discharge; And while φ 21 step-downs, MS1 conducting, MS2 disconnects, and C1 starts charging; CLK1 is the clock signal of exporting after buffer stage.
The mapping ratio of common above-mentioned current mirror is 1:1.
In the ideal case, the time of comparator C MP1/CMP2 single upset is C1*VREF2/IC2 or C2*VREF2/IC2; In order to make clock signal duty cycle consistent, C1=C2 conventionally; Therefore clock cycle T1 is 2*C1*VREF2/IC2; And VREF2=IC2*R1; So T1=2*C1*R1; Due to all very little (1e-5 magnitude) of voltage coefficient of C1 and R1, therefore, ideally T1 is very little with the variation of supply voltage, can ignore.But in fact, because control logic all exists time delay, therefore under truth:
T1=2* (C1*R1+Tlogic1), and Tlogic1 is the transmission delay of control logic part.It is larger that this two-part time delay is affected by supply voltage, is negative correlation, and in the time that supply voltage raises, Tlogic1 also diminishes.A for example oscillator output 16MHz clock signal, supply voltage is from 2.4V～5.5V, and clock frequency changes can reach 3%; When clock frequency improves again, situation is more serious.
Tlogic1=2*Cl*A/{Un*Cox* (W/L) * (VDD-Vthn) }, Vth is the threshold voltage of NMOS, U is mobility, Cox is unit grid capacitance value, Cl is the load capacitance of logical circuit, A is a dimensionless item being made up of VDD, Vthn, Vthp, simplifies and sees that can work as it is a fixed coefficient.
In order to reduce the impact of supply voltage on clock signal frequency, introduce cmos switch pipe SW1 and SW2, its anode NMOS controls voltage and meets power vd D, and negative terminal PMOS controls voltage ground connection (GND).The opening resistor of switching tube SW1/SW2 is relevant with technique, size and cut-in voltage relevant.Connected mode as shown in Figure 2,
Ron＝1/{Un*Cox*(W/L)n*(VDD-Vthn)}//1/{Up*Cox*(W/L)p*(VDD-|Vthp|)}；
Wherein Un, Up are respectively the electron mobility of NMOS and PMOS in cmos switch pipe; (W/L) n, (W/L) p are respectively the length-width ratio of NMOS pipe and PMOS pipe; Vthn, Vthp are respectively the threshold voltage of NMOS pipe and PMOS pipe; Cox is grid specific capacitance value, and VDD is supply voltage.When | when approximating Vthn, Vthp| (under most of process conditions, meets),
Ron＝1/{(Un*Cox*(W/L)n+Up*Cox*(W/L)p)}*(VDD-Vthn)。
When IC2 is to capacitor C 1, C2 charging, pressure drop Vsw=IC2*Ron of the upper existence of switching tube SW1, SW2 has become VREF2-Vsw with reference to ground so originally between the charging zone of VREF2; Be equivalent to the existence due to this pressure drop, between charging zone, diminish, desirable T1 diminishes,
Desirable T1=2*C1* (VREF2-Vsw)/IC2=2*C1* (R1-Ron);
Actual T1=2* (C1* (R1-Ron)+Tlogic1)=2* (C1*R1+Tlogic1-C1*Ron), non-ideal factor is Tlogic1-C1*Ron.
It is known by above-mentioned analysis,
Tlogic1-C1*Ron＝2*Cl*A/{Un*Cox*(W/L)*(VDD-Vthn)}-C1/{(Un*Cox*(W/L)n+Up*Cox*(W/L)p)}*(VDD-Vthn)＝{2*Cl*A/[Un*Cox*(W/L)]-C1/[(Un*Cox*(W/L)n+Up*Cox*(W/L)p)]}/(VDD-Vthn)
Therefore, when
2*Cl*A/[Un*Cox* (W/L)]=C1/[(Un*Cox* (W/L) n+Up*Cox* (W/L) p)] time,
Tlogic1＝C1*Ron。
Non-ideal factor is eliminated, and actual T1=2*R1*C1 has low-down voltage coefficient; Have the resistance string of low-temperature coefficient if R1 is of two kinds of resistance composition with Positive and Negative Coefficient Temperature, or R1 adopts and have the very ppoly resistance of low-temperature coefficient, actual T1=2*R1*C1 also has low-down temperature coefficient.Clock frequency Freq1=1/T1, therefore also has low-down voltage coefficient and temperature coefficient.
But consider that in circuit, also having other non-ideal factor affects voltage or the temperature coefficient of clock frequency, channel modulation benefit, the time delay of comparator etc. of such as current mirror, C1*Ron general using circuit emulator is selected the value of an optimization in the scope of 0.8*Tlogic1～1.2*Tlogic1, determine switch pipe SW1 thus, the size W/L of SW2.
In the time considering that clock frequency can regulate, must increase by a road current mirror and regulate M4 to regulate charging and discharging currents IC2; With aforementioned similar, substitute Freq1 with clock cycle T1 and analyze.In the time that signal F1 is high, SW3F closure, IC2=2*IREF1, therefore T1 reduces by half, and frequency improves 1 times.Now Tlogic1, constant, if the Ron of SW1, SW2 is constant, Vsw can increase by 1 times,
Actual T1=2* (C1* (R1/2-Ron/2)+Tlogic1)=C1*R1+2* (Tlogic1-C1*Ron/2), non-ideal factor Tlogic1 and C1*Ron/2 no longer can offset.That is to say, in the time of clock frequency shift, voltage coefficient and temperature coefficient originally all can change, and the non-ideal factor of control logic time delay manifests.In order to eliminate the impact of control logic time delay under different clock frequencies, need to give SW1 and the each switching tube SW1F in parallel of SW2 and SW2F, and controlled by frequency adjustment control signal F1, when F1 is while being high, the closed conducting of above-mentioned SW1F and SW2F.
If the conducting resistance of paralleling switch pipe is Ronp, if Vsw=2*IC2*Ronp=IC2*Ron, i.e. the pressure drop at frequency adjustment front-rear switch pipe two ends is consistent,
T1＝2*(C1*(R1/2-Ronp/2)+Tlogic1)
＝C1*R1+2*(Tlogic1-C1*Ronp/2)
＝C1*R1+2*(Tlogic1-C1*Ron)
Non-ideal factor Tlogic1 and compensation factor C1*Ron can offset; While regulating different clock frequencies like this, the non-ideal factor of control logic time delay can be eliminated all the time, has ensured all to have low voltage coefficient and temperature coefficient at different frequency gear.
Referring to Fig. 3, for another kind has been eliminated pierce circuit figure on the sheet of control logic delay.Wherein reference current IREF2 shines upon by current mirror M5 to M6, and the R2 that flows through, R3 produce reference voltage VREF3, and VREF4, VREF3=IREF2* (R2+R3), and VREF4=IREF2*R3; Current mirror M7～M10 produces charging and discharging currents IC3 and charge-discharge circuit IC4; Charge and discharge switch group is made up of PMOS switch MS5+NMOS switch MS6, upper termination current mirror M8 drain electrode, lower end M10 drain electrode, the negative terminal of indirect charge and discharge capacitance C4 top crown and comparator C MP3 and the anode of comparator C MP4; Between charge and discharge capacitance C4 bottom crown and ground, be connected in series a nmos switch SW4; SW4 is in normal closure state, and its anode NMOS controls voltage and meets power vd D; The negative terminal of comparator C MP3 anode and CMP4 meets respectively reference voltage VREF3, VREF4, and output meets control logic control_logic2; This control logic comprises a rest-set flip-flop and a buffer stage composition; In the time that the positive terminal voltage of CMP4 is less than VREF4, φ 31 step-downs, MS5 conducting, MS6 disconnects, and C4 starts charging; In the time that CMP3 negative terminal voltage is greater than VREF3, φ 31 uprises, MS6 conducting, and MS5 disconnects, and C4 starts electric discharge; CLK2 is the clock signal of exporting after buffer stage.For setting forth for simplicity, the mapping ratio of establishing above-mentioned current mirror is 1:1, IC3=IC4=IREF2.SW4 eliminates the same with in accompanying drawing 2 of the principle of control logic time delay non-ideal factor, repeats no more.Difference is, in accompanying drawing 3, many capacitor C 5, establish for trimming (trimming electric capacity) object.Due to the deviation of semiconductor fabrication process, conventionally to be provided with and trim electric capacity and trim clock frequency, for example C5 electric capacity top crown connects C4 top crown, bottom crown, through switching tube SW5 ground connection, is trimmed signal TRIM and is controlled, when TRIM is while being high, C5 electric capacity and C4 parallel connection, clock frequency reduces certain value.Before supposing to trim, control logic delay is offset by switching tube SW4, and after trimming, in order to ensure that all the time control logic time delay can be eliminated, the ratio that the size of switching tube SW5 need meet its opening resistor Ron5 and switching tube SW4 opening resistor Ron4 meets:
Ron5/Ron4＝C4/C5；
Be equivalent to the opening resistor of switching tube and the capacitance of respective branch is inversely proportional to, due to Ron inverse ratio and switching tube size W/L, therefore switching tube SW5 size (W/L)
5with switching tube SW4 size (W/L)
4need to meet:
(W/L)
5/(W/L)
4＝C5/C4
Now, can ensure that control logic time delay can be eliminated after trimming.
Therefore, the present invention can eliminate the impact of control logic time delay on clock frequency voltage coefficient and temperature coefficient effectively, and particularly high in clock frequency, and reference clock frequency changes occasion greatly, and the implementation structure of circuit is simple, and cost is low.
In a word, the foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. eliminate a pierce circuit on the sheet of control logic time delay, it is characterized in that described upper pierce circuit mainly includes the first reference voltage, the second reference voltage, the first charging and discharging currents, the first charge and discharge switch group, the first charge and discharge capacitance, the first comparator and control logic; Wherein the first reference voltage is electrically connected to the input of the first comparator, and the upper end of the first charge and discharge capacitance branch road is connected to another input of the first comparator, and the lower end of the first charge and discharge capacitance is connected to reference to ground; Control logic control the first charge and discharge switch group is used the first charging and discharging currents that the first charge and discharge capacitance is filled and/or discharged, the top crown voltage of the first charge and discharge capacitance is changed back and forth between the first reference voltage and the second reference voltage, the first comparator outputting oscillation signal; The first charge and discharge capacitance branch road is also connected in series first switching tube, and this first switching tube is in opening state, and the voltage of start signal and supply voltage positive correlation.
2. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, it is characterized in that the size of described the first switching tube, the voltage at switching tube two ends is with the ratio of mains voltage variations absolute value and reference voltage, be time of delay sum absolute value and the ratio of the first charge and discharge capacitance charge or discharge required time 80%～120%.
3. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, is characterized in that described the first switching tube is nmos switch pipe, or CMOS complementary switch pipe; The voltage of start signal is supply voltage.
4. pierce circuit on the sheet of elimination control logic as claimed in claim 3 time delay, is characterized in that described the first switching tube is serially connected between the first charge and discharge capacitance bottom crown and earth terminal (GND); The first charge and discharge capacitance top crown connects comparator input terminal.
5. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, is characterized in that pierce circuit on the sheet of described elimination control logic time delay, also comprises a road reference voltage; Above-mentioned reference voltage You Yi road reference current flow through reference resistance produce; On described reference resistance, be connected in series another switching tube, this another switching tube is identical with the first switching tube type.
6. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, it is characterized in that pierce circuit on the sheet of described elimination control logic time delay, also include the second charge and discharge capacitance and be serially connected in earth terminal and this second charge and discharge capacitance between second switch pipe, second switch is effective in to regulate the clock frequency of oscillator; Described second switch pipe and the first switching tube same type; The ratio of equivalent resistance under equivalent resistance and the first switching tube opening under this second switch pipe opening, be the first charging capacitor and the second charging capacitor ratio 80%～120%.
7. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, it is characterized in that pierce circuit on the sheet of described elimination control logic time delay, also include the 3rd switching tube, itself and the first paralleled power switches, be subject to a frequency adjustment control signal control folding; The second charging and discharging currents, is subject to the control of above-mentioned same frequency adjustment control signal, for being superimposed upon aforementioned the first charging and discharging currents, for regulating clock frequency; In the time that the second charging and discharging currents is superimposed upon on the first charging and discharging currents, the 3rd switching tube closure; Otherwise the 3rd switching tube disconnects; The size Selection of the 3rd switching tube is that its closed front and back paralleling switch pipe both end voltage is remained unchanged substantially.
8. pierce circuit on the sheet of elimination control logic as claimed in claim 7 time delay, it is characterized in that above-mentioned the second charging and discharging currents, described charging and discharging currents produces by current mirror, and Qie Yi road current mirror is parallel on the branch road that produces the second charging and discharging currents, is used for regulating charging and discharging currents.
9. pierce circuit on the sheet of elimination control logic as claimed in claim 8 time delay, it is characterized in that further, the each auxiliary switch in parallel of the first switching tube and second switch pipe, described auxiliary switch is subject to the control of frequency adjustment control signal, when frequency adjustment control signal is while being high, the closed conducting of above-mentioned auxiliary switch.
10. pierce circuit on the sheet of elimination control logic as claimed in claim 1 time delay, it is characterized in that on the sheet of described elimination control logic time delay, pierce circuit also comprises the second comparator, the second charge and discharge switch group, the second charge and discharge capacitance, and the second reference voltage is earth terminal; Wherein the first charge and discharge switch group comprises charge switch and discharge switch, and two switches are connected in series, upper termination charging and discharging currents after serial connection, and lower termination earth terminal, serial connection connecting place connects the top crown of the first charge and discharge capacitance, connects the input of the first comparator simultaneously; Another input termination first reference voltage of the first comparator; The connected mode of the second charge and discharge switch group, the second charge and discharge capacitance and the second comparator is also like this.
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|---|---|---|---|---|
| CN105162418A (en) * | 2015-09-28 | 2015-12-16 | 上海华力微电子有限公司 | Oscillation circuit for eliminating delay and mismatch of comparator |
| CN105162418B (en) * | 2015-09-28 | 2018-08-28 | 上海华力微电子有限公司 | A kind of oscillating circuit for eliminating comparator delay and mismatch |
| CN105305961A (en) * | 2015-10-29 | 2016-02-03 | 上海华力微电子有限公司 | Oscillating circuit for eliminating comparator delay |
| CN105305961B (en) * | 2015-10-29 | 2018-08-10 | 上海华力微电子有限公司 | Eliminate the oscillating circuit of comparator delay |
| CN107014507A (en) * | 2017-05-24 | 2017-08-04 | 杭州电子科技大学 | A kind of built-in temperature sensor and its temperature checking method based on RC oscillators |
| CN107014507B (en) * | 2017-05-24 | 2019-02-15 | 杭州电子科技大学 | A kind of built-in temperature sensor based on RC oscillator |
| CN107171643A (en) * | 2017-05-30 | 2017-09-15 | 长沙方星腾电子科技有限公司 | A kind of pierce circuit |
| CN107565935A (en) * | 2017-09-06 | 2018-01-09 | 芯海科技（深圳）股份有限公司 | A kind of circuit for reducing oscillator power consumption |
| CN107565935B (en) * | 2017-09-06 | 2021-07-02 | 芯海科技（深圳）股份有限公司 | Circuit for reducing power consumption of oscillator |
| CN114204918A (en) * | 2020-09-17 | 2022-03-18 | 圣邦微电子（北京）股份有限公司 | Oscillator |
| CN112468088A (en) * | 2020-11-16 | 2021-03-09 | 珠海格力电器股份有限公司 | RC oscillator and RC oscillator system |
| WO2023016080A1 (en) * | 2021-08-11 | 2023-02-16 | 华润微集成电路(无锡)有限公司 | High-precision clock circuit structure |
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|---|---|
| CN104143968B (en) | 2017-08-22 |
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Address after: 518000, A building, block 9, garden city digital garden, 1079 Nanhai Road, Guangdong, Shenzhen, Nanshan District Patentee after: Chipsea Technology (Shenzhen) Co., Ltd. Address before: 518067 Nanshan District, Shenzhen, Nanhai Avenue, garden city, No. 1079, building A, block, floor 9 Patentee before: Xinhai Science and Technology Co., Ltd., Shenzhen City |