CN103973227A - Low-voltage oscillator - Google Patents

Abstract

The invention relates to an electronic circuit technology, and particularly relates to a low-voltage oscillator. The low-voltage oscillator disclosed by the invention comprises a self-adjustment current reference module, a first mirror image circuit, a second mirror image circuit, a control module, a hysteresis inverter and a capacitor C1, wherein the output end of the self-adjustment current reference module is connected to the input end of the first mirror image circuit; the output end of the first mirror image circuit is connected with the positive power end of the second mirror image circuit; the input end of the control module is connected with the negative power end of the first mirror image circuit and the input end of the second mirror image circuit; the output end of the control module is connected with the enable end of the first mirror image circuit, the enable end of the second mirror image circuit and the input end of the hysteresis inverter; the output end of the hysteresis inverter is the output end of the oscillator. The low-voltage oscillator has the beneficial effects that the input voltage is as low as 1.2V, the duty ratio and the frequency of an output oscillator signal are not affected by supply voltage, and the structure is simple.

Description

A kind of low voltage oscillator

Technical field

The present invention relates to electronic circuit technology, relate to specifically a kind of low voltage oscillator.

Background technology

As shown in Figure 1, be the circuit diagram of a kind of oscillator conventional in prior art, wherein MP01, MP02, MN01, MN02 and R01 form band gap reference, by charging to after MP03 pipe mirror image capacitor C 01, when C01 charges to high level V _htime, inverter INV01 exports high level, and the conducting of MP04 pipe starts to capacitor discharge.C ₀₁be discharged to low level V _ltime, inverter output low level, MP04 manages cut-off, and C01 continues charging.Capacitor C 01 does not stop to discharge and recharge formation sawtooth signal, after inverter INV01 and INV02 shaping, exports square wave oscillation signal.In the time that supply voltage VDD is too low, oscillator quits work, and the required minimum input voltage of this oscillator is not more than V _gSn-V _gSp+ V _dSp(or V _dSn), under typical CMOS technique, this value is about 1.6V.The charging stage breakover voltage V of capacitor C 01 in this circuit _hwith discharge regime breakover voltage V _lbetween difference V _h-V _lcan be along with input supply voltage V _dDchange and change, the charging current of establishing electric capacity is I _r, discharging current is I _f, the frequency of known oscillator is I _r* I _f/ [(V _h-V _l) (I _r+ I _f)].Input voltage V under normal circumstances _dDwhen change, 1/I _r+ 1/I _fwith V _h-V _lchange is not linear relationship, and therefore the output frequency of oscillator is along with input voltage V _dDchange have larger variation.

Summary of the invention

To be solved by this invention, the output frequency existing for above-mentioned traditional oscillators exactly has the problem of larger change along with the change of input voltage, propose a kind of low voltage oscillator.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of low voltage oscillator, it is characterized in that, and comprise self-regulation current reference module, the first mirror image circuit, the second mirror image circuit, control module, sluggish inverter and capacitor C 1; Wherein, the positive supply termination power vd D of self-regulation current reference module, its negative power end ground connection GND, its output termination first mirror is as the input of circuit; The positive supply termination power vd D of the first mirror image circuit, its negative power end is by the rear ground connection GND of capacitor C 1, and it exports the positive power source terminal of termination the second mirror image circuit; The input of the second mirror image circuit is by capacitor C 1 ground connection GND, its negative power end ground connection GND; The input termination first mirror of control module is as the negative power end of circuit and the input of the second mirror image circuit, and its output termination first mirror is as Enable Pin, the Enable Pin of the second mirror image circuit and the input of sluggish inverter of circuit; The positive supply termination power vd D of sluggish inverter, its negative power end ground connection GND, the output that its output is oscillator; Wherein self-regulation current reference module can be exported different reference currents under different power vd D.

Concrete, described self-regulation current reference module by PMOS manage MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, resistance R 1 forms; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the first mirror image circuit after connecing the grid of MP2, and its drain electrode connects the drain electrode of MN1; The source electrode of MP2 meets power vd D, and its drain electrode connects the drain electrode of MN2; The grid of MN1 and drain electrode interconnection, its grid connects the grid of MN2, its source ground GND; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the drain electrode of MP3; The grid of MN3 is by the rear ground connection GND of resistance R 1; The drain electrode of MP3 and gate interconnection, its source electrode meets power vd D;

Described sluggish inverter is made up of PMOS MP4, MP5, MP6, NMOS pipe MN4, MN5, MN6; Wherein, the gate interconnection of MP4, MP5, MN4, MN5 connects the output of control module; The source electrode of MP4 meets power vd D, and its drain electrode connects the source electrode of MP4 and the source electrode of MP6; The drain electrode of MP5 is connected as output with the grid of the drain electrode of MN5, MP6 and the grid of MN6; The grounded drain GND of MP6; The source electrode of MN5 connects the drain electrode of MN4 and the source electrode of MN6; The source ground GND of MN4; The source ground GND of MN6.

Beneficial effect of the present invention is, minimum input voltage is low to moderate 1.2V, and duty ratio and the frequency of output oscillator signal are not affected by supply voltage, and simple in structure.

Brief description of the drawings

Fig. 1 is the electrical block diagram of traditional vibrator;

Fig. 2 is the electrical block diagram of embodiment;

Fig. 3 is the electrical block diagram of self-regulation current reference module in embodiment;

Fig. 4 is the electrical block diagram of sluggish inverter in embodiment;

Fig. 5 is that embodiment is at V _dDsimulation waveform figure during for 1.2V;

Fig. 6 is that embodiment is at V _dDsimulation waveform figure during for 2.5V.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

As shown in Figure 2, low voltage oscillator of the present invention, comprises self-regulation current reference module, the first mirror image circuit, the second mirror image circuit, control module, sluggish inverter and capacitor C 1; Wherein, the positive supply termination power vd D of self-regulation current reference module, its negative power end ground connection GND, its output termination first mirror is as the input of circuit; The positive supply termination power vd D of the first mirror image circuit, its negative power end is by the rear ground connection GND of capacitor C 1, and it exports the positive power source terminal of termination the second mirror image circuit; The input of the second mirror image circuit is by capacitor C 1 ground connection GND, its negative power end ground connection GND; The input termination first mirror of control module is as the negative power end of circuit and the input of the second mirror image circuit, and its output termination first mirror is as Enable Pin, the Enable Pin of the second mirror image circuit and the input of sluggish inverter of circuit; The positive supply termination power vd D of sluggish inverter, its negative power end ground connection GND, the output that its output is oscillator; Wherein self-regulation current reference module can be exported different reference currents under different power vd D.

Embodiment:

As shown in Figure 3, in this example self-regulation current reference module by PMOS manage MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, resistance R 1 forms; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the first mirror image circuit after connecing the grid of MP2, and its drain electrode connects the drain electrode of MN1; The source electrode of MP2 meets power vd D, and its drain electrode connects the drain electrode of MN2; The grid of MN1 and drain electrode interconnection, its grid connects the grid of MN2, its source ground GND; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the drain electrode of MP3; The grid of MN3 is by the rear ground connection GND of resistance R 1; The drain electrode of MP3 and gate interconnection, its source electrode meets power vd D;

As shown in Figure 4, sluggish inverter is made up of PMOS MP4, MP5, MP6, NMOS pipe MN4, MN5, MN6; Wherein, the gate interconnection of MP4, MP5, MN4, MN5 connects the output of control module; The source electrode of MP4 meets power vd D, and its drain electrode connects the source electrode of MP4 and the source electrode of MP6; The drain electrode of MP5 is connected as output with the grid of the drain electrode of MN5, MP6 and the grid of MN6; The grounded drain GND of MP6; The source electrode of MN5 connects the drain electrode of MN4 and the source electrode of MN6; The source ground GND of MN4; The source ground GND of MN6.

This routine operation principle is:

The reference current that in this example, self-regulation current reference module provides is:

$I_{\mathrm{ref}}=\frac{n*V_{\mathrm{Tn}}*\ln k}{R_s}=\frac{C_1}{R_s}$

Wherein k is the ratio of MN2 and MN1, and n is the ratio of MP2 and MP1, and Rs is the equivalent resistance of the MN3 in linear zone, and voltage and current relationship by metal-oxide-semiconductor when the linear zone can obtain:

$I_{\mathrm{ref}}=\frac{C_1}{R_s}=C_1\mathrm{Cox\μ}\frac{W_{\mathrm{MN}3}}{L_{\mathrm{MN}3}}(V_{\mathrm{GS}3}-V_{\mathrm{Tn}})=C_2(V_{\mathrm{GS}3}-V_{\mathrm{Tn}})$

Wherein W _mN3, L _mN3and V _gS3represent respectively grid width, grid length and the V of NMOS pipe MN3 _gSvalue, C _oX, μ and V _tnrepresent respectively the threshold voltage of metal-oxide-semiconductor grid oxide layer thickness, electron mobility and NMOS pipe under special process, for the ease of statement, use C ₂represent C ₁cox μ.Because the grid level of MN3 is connected to a V through the step-down of diode type of attachment _dD, can obtain:

I _ref＝C ₂(V _GS3-V _Tn)＝C ₂(V _DD+V _Tp-V _Tn)

Wherein V _tpand V _tnrepresent respectively PMOS pipe threshold voltage and NMOS pipe threshold voltage under special process.

The first mirror image circuit that described band enables is with the reference current value of certain multiple (can be less than 1) mirror image self-regulation reference current module, for giving capacitor C ₁charging, when the first mirror image circuit enables to be input as when low, this module quits work, and stops as capacitor C ₁charging.

The second mirror image circuit that described band enables is with the image current value of certain multiple (can be less than 1) mirror image the first mirror image circuit, for giving capacitor C ₁electric discharge, when the second mirror image circuit enables to be input as when high, this module quits work, and stops as capacitor C ₁electric discharge.

Described control module function is as follows: this module has lag function, and input is in ascent stage, and input is higher than V _dD+ V _tptime, control module output low level; When input is in the decline stage, input is lower than V _tntime, control module output high level.

This routine workflow is as follows: when circuit is started working, in capacitor C 1, original levels is 0, and control module is output as height, and the first mirror image circuit is started working, and the second mirror image circuit quits work, capacitor C ₁start to enter the charging stage; Work as capacitor C ₁charge to V _dD+ V _tptime, control module output low level, the first mirror image circuit quits work, and the second mirror image circuit is started working, capacitor C ₁start to enter discharge regime; When capacitor discharge is to V _tntime, controller output high level, the first mirror image circuit is started working, and the second mirror image circuit quits work, capacitor C ₁start to reenter the charging stage.The continuous recharge discharge regime of circuit, controls its lasting outputting oscillation signal, and this oscillator signal is the comparatively desirable oscillator signal of output through described sluggish inverter optimization and after adjusting.According to electric capacity electrical characteristic, charging stage required time t _rwith discharge regime required time t _fas follows:

$t_r=\frac{C*U}{I_r}=\frac{C*(V_{\mathrm{DD}}+V_{\mathrm{Tp}}-V_{\mathrm{Tn}})}{n_r{C}_2(V_{\mathrm{DD}}+V_{\mathrm{Tp}}-V_{\mathrm{Tn}})}=\frac{C}{n_r{C}_2}$

$t_f=\frac{C*U}{I_f}=\frac{C*(V_{\mathrm{DD}}+V_{\mathrm{Tp}}-V_{\mathrm{Tn}})}{n_f{C}_2(V_{\mathrm{DD}}+V_{\mathrm{Tp}}-V_{\mathrm{Tn}})}=\frac{C}{n_f{C}_2}$

Wherein n _rand n _fthe ratio (all can be less than 1) that represents respectively first mirror image current and variable reference electric current, the second image current and variable reference electric current, C represents capacitor C ₁capacitance.Due to C, C ₂, n _rand n _fbe and supply voltage V _dDirrelevant constant, therefore known as input supply voltage V _dDwhen change, output frequency and the duty ratio of oscillator are constant.

Oscillator is at input voltage V _dDas shown in Figure 5, Figure 6, wherein C1 is electric capacity anode waveform to simulation waveform figure during for 1.2V and 2.5V, and Control is control module output waveform, and OSC_OUT is pierce circuit output waveform, and simulation result shows, as supply voltage V _dDwhen change, oscillator output frequency and duty ratio are constant.

Claims (2)

1. a low voltage oscillator, is characterized in that, comprises self-regulation current reference module, the first mirror image circuit, the second mirror image circuit, control module, sluggish inverter and capacitor C 1; Wherein, the positive supply termination power vd D of self-regulation current reference module, its negative power end ground connection GND, its output termination first mirror is as the input of circuit; The positive supply termination power vd D of the first mirror image circuit, its negative power end is by the rear ground connection GND of capacitor C 1, and it exports the positive power source terminal of termination the second mirror image circuit; The input of the second mirror image circuit is by capacitor C 1 ground connection GND, its negative power end ground connection GND; The input termination first mirror of control module is as the negative power end of circuit and the input of the second mirror image circuit, and its output termination first mirror is as Enable Pin, the Enable Pin of the second mirror image circuit and the input of sluggish inverter of circuit; The positive supply termination power vd D of sluggish inverter, its negative power end ground connection GND, the output that its output is oscillator; Wherein self-regulation current reference module can be exported different reference currents under different power vd D.

2. a kind of low voltage oscillator according to claim 1, is characterized in that, described self-regulation current reference module by PMOS manage MP1, MP2, MP3, NMOS pipe MN1, MN2, MN3, resistance R 1 forms; Wherein, the source electrode of MP1 meets power vd D, and its grid connects the first mirror image circuit after connecing the grid of MP2, and its drain electrode connects the drain electrode of MN1; The source electrode of MP2 meets power vd D, and its drain electrode connects the drain electrode of MN2; The grid of MN1 and drain electrode interconnection, its grid connects the grid of MN2, its source ground GND; The source electrode of MN2 connects the drain electrode of MN3; The grid of MN3 connects the drain electrode of MP3; The grid of MN3 is by the rear ground connection GND of resistance R 1; The drain electrode of MP3 and gate interconnection, its source electrode meets power vd D;

Described sluggish inverter is made up of PMOS MP4, MP5, MP6, NMOS pipe MN4, MN5, MN6; Wherein, the gate interconnection of MP4, MP5, MN4, MN5 connects the output of control module; The source electrode of MP4 meets power vd D, and its drain electrode connects the source electrode of MP4 and the source electrode of MP6; The drain electrode of MP5 is connected as output with the grid of the drain electrode of MN5, MP6 and the grid of MN6; The grounded drain GND of MP6; The source electrode of MN5 connects the drain electrode of MN4 and the source electrode of MN6; The source ground GND of MN4; The source ground GND of MN6.