CN105162418A - Oscillation circuit for eliminating delay and mismatch of comparator - Google Patents
Oscillation circuit for eliminating delay and mismatch of comparator Download PDFInfo
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- CN105162418A CN105162418A CN201510626725.6A CN201510626725A CN105162418A CN 105162418 A CN105162418 A CN 105162418A CN 201510626725 A CN201510626725 A CN 201510626725A CN 105162418 A CN105162418 A CN 105162418A
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Abstract
The invention discloses an oscillation circuit for eliminating delay and mismatch of a comparator. The oscillation circuit comprises a constant current source I, a switch K, a switch KB, a double-capacitance oscillation module, a first comparison module, a second comparison module and a logic module LOGIC; the output ends of the first comparison module and the second comparison module are connected with the logic module LOGIC; the double-capacitance oscillation module comprises two groups of square wave generating units, which are connected in parallel and have the same structure, each square wave generating unit is additionally provided with a capacitor, some switches, a voltage control unit and some logic modules and the like, and such factors as the reset of the initial state of the capacitor, the achievement method of the voltage control unit, the performance requirements of voltage control and charge injection of various switches and the like are comprehensively considered, so that the delay and mismatch of the comparison modules can be greatly perfected, namely, a clock signal CLK amplitude and clock signal CLK signal frequency with more stable and accurate frequency are obtained.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to the oscillating circuit in a kind of Analog Circuit Design, more particularly, relate to a kind of oscillating circuit eliminating comparator delay and mismatch.
Background technology
The circuit that can produce oscillating current is called oscillating circuit, it is applied widely in electronic science and technology field, as the signal source etc. in local oscillator, Medical Instruments and the measuring instrument in the carrier oscillator of transmitter in communication system, receiver.The kind of oscillator is a lot, divides, can be divided into sine-wave oscillator and nonsinusoidal oscillator by the waveform of signal.The waveform that sine-wave oscillator produces is in close proximity to sine wave or cosine wave, and frequency of oscillation is more stable; The waveform that nonsinusoidal oscillator produces is non-sinusoidal impulse waveform, as square wave, square wave, sawtooth waveforms etc.
Refer to Fig. 1, Figure 1 shows that two capacitive tank circuit structural representations conventional in prior art.As shown in the figure, this annular oscillation circuit generally includes 4 switches (two K switches and two KB switches), two electric capacity C1 and C2, two comparison circuit COMP and logical block LOGIC.Wherein, K switch and K switch B are two contrary signals, and they make 4 switches be divided into two groups, and two K switches are one group, and two KB switches are other one group; One group another group is certain when closing disconnects, and namely when two K switch opens, two KB switches necessarily disconnect, otherwise when two KB switch opens, two K switches necessarily disconnect.
When supposing two K switch opens, then continuous current source I charges to electric capacity C1, the top crown voltage V1 of electric capacity C1 rises, when voltage V1 is greater than VREF, and the output switching activity of two comparator COMP, in logical block LOGIC, K and KB signal changes, CLK signal produces a rising (or decline) edge, and voltage V1 is by switch discharge to ground, and current source I starts to charge to electric capacity C2 simultaneously, circulation like this, just clocking CLK.
Refer to Fig. 2, the waveform schematic diagram of voltage V1, V2 that Fig. 2 produces for capacitive tank circuit structure two in prior art and clock signal clk.As shown in the figure, when voltage V1 or voltage V2 still rises a period of time after arrival VREF, this is because the reasons such as the delay of comparator COMP and/or input mismatch cause.
Particularly, for common comparator COMP, because the V-VREF postponed and mismatch produces is approximately 0.12V, if VREF=1.2V, so:
1), the absolute value of frequency has the ± deviation of 10%.
2), in different Corner V-VREF has the ± gap of 50%, so can introduce ± the change of 5% frequency.
It will be apparent to those skilled in the art that this can make the frequency of clock signal CLK reduce if voltage V1 or voltage V2 still rises a period of time after arrival VREF.Meanwhile, this section of delay time is unpredictable, and it is subject to the impact of the factor such as temperature and technique, and the output frequency of clock signal clk is changed greatly, and Here it is causes the frequency of the Non-sinusoidal Oscillations device reason that often stability is not high.
Therefore, determine the error of device model or the error of back segment interconnect parasitic resistance capacitance extraction, being the key reducing circuit simulation error, is also industry urgent problem.
Summary of the invention
Main purpose of the present invention is the defect overcoming prior art, a kind of oscillating circuit eliminating comparator delay and mismatch is provided, it postpones and the impact that brings of mismatch by eliminating comparator, makes to obtain frequency more stable with clock signal clk amplitude and clock signal clk signal frequency accurately.
For reaching above-mentioned purpose, technical scheme of the present invention is as follows:
Eliminate an oscillating circuit for comparator delay and mismatch, described oscillating circuit comprises a continuous current source I, K switch, K switch B, the concussion of two electric capacity module, the first comparison module, the second comparison module and a logic module LOGIC; Described first comparison module is connected with described logic module LOGIC with the output of the second comparison module; Described pair of electric capacity concussion module comprises two groups and connects and the identical square wave generation unit of structure, first square wave generation unit and the second square wave generation unit control the break-make with described continuous current source I by described K switch and K switch B respectively, one group when closing, another group is certain to be disconnected; Described first square wave generation unit comprises 6 switches, 2 capacitances electric capacity C1 identical and connected with each other respectively, C2 branch road and have first voltage control unit of normal voltage V-VREF; Wherein, described 6 switches comprise 2 and are serially connected in K switch 1 in described electric capacity C1, C2 branch road and K2, the K switch 3 K switch 1 be connected with the output VOUT of described first voltage control unit with electric capacity C1 contact, the K switch 4 K switch 1 be connected with the input VIN of described first voltage control unit with electric capacity C1 contact, the K switch 3 K switch 2 and electric capacity C2 contact are connected with the input VIN of described first voltage control unit and the K switch 4 K switch 2 be connected with the output VOUT of described first voltage control unit with electric capacity C2 contact respectively; The input anode of described first comparison module is connected with the contact of K switch with described first square wave generation unit, the input negative terminal access normal voltage V-VREF of described first comparison module; Described second square wave generation unit comprises 6 switches, 2 capacitances electric capacity C3 identical and connected with each other respectively, C4 branch road and have second voltage control unit of normal voltage V-VREF; Wherein, described 6 switches comprise 2 and are serially connected in described electric capacity C3 respectively, K switch 3 in C4 branch road and K4, the K switch 3 that K switch 3 is connected with the output VOUT of described second voltage control unit with electric capacity C3 contact, K switch 1 that K switch 3 is connected with the input VIN of described second voltage control unit with electric capacity C3 contact, the K switch 1 that K switch 4 and electric capacity C4 contact are connected with the input VIN of described second voltage control unit and the K switch 2 that K switch 3 is connected with the output VOUT of described second voltage control unit with electric capacity C4 contact; The input anode of described second comparison module is connected with the contact of K switch B with described second square wave generation unit, the input negative terminal access normal voltage V-VREF of described second comparison module; Wherein, described K switch and K switch B are two contrary signals, described continuous current source I loop, a Hui Xiang mono-tunnel charging simultaneously; Four electric capacity C1, C2, C3, C4 capacitance is equal, and when work starts, four electric capacity C1, the top crown of C2, C3, C4 is all reset to ground; In the course of the work, other 12 switches remaining are divided into two groups, are controlled respectively by K switch and K switch B; Work as K, K1, K4 switch conduction, KB, K2, when K3 switch disconnects, described continuous current source I flows to described electric capacity C1, and the top crown voltage V1 of described electric capacity C1 raises, described top crown voltage V1 joins described first voltage control unit input VIN, input voltage VIN and normal voltage VREF are subtracted each other by described first voltage control unit, and now, described electric capacity C2 top crown is then connected on the output VOUT of described first voltage control unit; When the top crown voltage V1 of described electric capacity C1 is elevated to described first comparison module upset, KB, K2, K3 switch conduction, K, K1, K4 switch disconnects, and described continuous current source I charges to described electric capacity C3, and described electric capacity C1 top crown then keeps input voltage V1 during described first comparison module upset, and by described first voltage control unit, V-VREF being passed to the top crown of described electric capacity C2, the top crown voltage V1 of described electric capacity C1 is pulled down to V-VREF; Meanwhile, the top crown voltage V2 of described electric capacity C3 raises, described top crown voltage V2 joins described second voltage control unit input VIN, input voltage VIN and normal voltage VREF are subtracted each other by described second voltage control unit, now, described electric capacity C4 top crown is then connected on the output VOUT of described second voltage control unit; When the top crown voltage V2 of described electric capacity C3 is elevated to described second comparison module upset, KB, K2, K3 switch disconnects, K, K1, K4 switch conduction, described continuous current source I charges to described electric capacity C1 again, described electric capacity C3 top crown then keeps input voltage V2 during described second comparison module upset, and by described second voltage control unit, V-VREF being passed to the top crown of described electric capacity C4, the top crown voltage V1 of described electric capacity C3 is pulled down to V-VREF, enters next cycle period.
Preferably, described first and second voltage control units are realized by amplifier, analog adder or switched-capacitor circuit.
Preferably, described logic module LOGIC comprises described SR latch and two d type flip flops; The output of described first comparison module and the second comparison module meets two input R of described SR latch, S respectively; Two output Q of described SR latch, QB is connected with the input of described two d type flip flops respectively.
Preferably, the value of described voltage V1 and voltage V2 is equal.
Preferably, the value of described voltage V1 and voltage V2 and the ratio of normal voltage VREF are 20:1 ~ 5:1.
Preferably, the value of described voltage V1 and voltage V2 and the ratio of normal voltage VREF are 10:1.
Preferably, the value of described normal voltage VREF is 0.12V.
As can be seen from technique scheme, the design of the oscillating circuit of elimination comparator delay provided by the invention and mismatch, can by increasing by two electric capacity on the circuit base of prior art, a little switch, two voltage control units (can use amplifier, analog adder, the realizations such as switched-capacitor circuit) and some logic modules etc., and, coordinate the reset considering electric capacity initial condition, the implementation method of voltage control unit, voltage-controlled performance requirement (such as, speed and driving force etc.) and various switch in the factor such as charge injection, significantly can improve the delay to comparison module and mismatch.
Accompanying drawing explanation
Figure 1 shows that two capacitive tank circuit structural representations conventional in prior art
The waveform schematic diagram of voltage V1, V2 that Fig. 2 produces for capacitive tank circuit structure two in prior art and clock signal clk
Fig. 3 is the circuit diagram that one embodiment of the invention eliminates the waveform generating portion of comparator delay and mismatch
Figure 4 shows that the present invention eliminates the oscillating circuit schematic diagram that comparator postpones and a preferred embodiment of mismatch is complete
Fig. 5 one embodiment of the invention eliminates a kind of way of realization schematic diagram of the logic module LOGIC in comparator delay and mismatch oscillating circuit
The waveform schematic diagram of K, KB, K1, K2, K3 and K4 that the oscillating circuit that Fig. 6 eliminates comparator delay and mismatch for one embodiment of the invention produces
Embodiment
For making content of the present invention clearly understandable, below in conjunction with Figure of description, content of the present invention is described further.Certain the present invention is not limited to this specific embodiment, and the general replacement known by those skilled in the art is also encompassed in protection scope of the present invention.In this manual and in detail in the claims, should understand when an element be called as ' attach ' to another element or " be connected " with another element time, it can directly connect, and maybe can there is intervention element.
Refer to Fig. 3 and Fig. 4, Fig. 3 is the circuit diagram that one embodiment of the invention eliminates the waveform generating portion of comparator delay and mismatch; Figure 4 shows that the present invention eliminates the oscillating circuit schematic diagram that comparator postpones and a preferred embodiment of mismatch is complete.
As shown in Figure 3, in an embodiment of the present invention, the oscillating circuit of the delay of this elimination comparator and mismatch comprises a continuous current source I, K switch, K switch B, the concussion of two electric capacity module, the first comparison module, the second comparison module and a logic module LOGIC; First comparison module is connected with logic module LOGIC with the output of the second comparison module.
Two electric capacity concussion module comprises two groups and connects and the identical square wave generation unit (i.e. the first square wave generation unit and the second square wave generation unit) of structure, first square wave generation unit and the second square wave generation unit control the break-make with continuous current source I by K switch and K switch B respectively, one group when closing, another group is certain to be disconnected.
First square wave generation unit comprises six switches, two capacitances electric capacity C1 identical and connected with each other respectively, C2 branch road and have first voltage control unit of normal voltage V-VREF.Usually, the value of normal voltage VREF is 0.12V.
These six switches comprise two and are serially connected in K switch 1 in described electric capacity C1, C2 branch road and K2, the K switch 3 K switch 1 be connected with the output VOUT of the first voltage control unit with electric capacity C1 contact, the K switch 4 K switch 1 be connected with the input VIN of described first voltage control unit with electric capacity C1 contact, the K switch 3 K switch 2 and electric capacity C2 contact are connected with the input VIN of described first voltage control unit and the K switch 4 K switch 2 be connected with the output VOUT of described first voltage control unit with electric capacity C2 contact respectively.
The input anode of the first comparison module is connected with the contact of K switch with the first square wave generation unit, the input negative terminal access normal voltage V-VREF of the first comparison module.
Second square wave generation unit also comprises six switches, two each and every one capacitances electric capacity C3 identical and connected with each other respectively, C4 branch road and have second voltage control unit of normal voltage V-VREF; Wherein, these six switches comprise two and are serially connected in electric capacity C3 respectively, K switch 3 in C4 branch road and K4, the K switch 3 that K switch 3 is connected with the output VOUT of the second voltage control unit with electric capacity C3 contact, K switch 1, the K switch 1 that K switch 4 and electric capacity C4 contact are connected with the input VIN of the second voltage control unit and the K switch 2 that K switch 3 is connected with the output VOUT of the second voltage control unit with electric capacity C4 contact that K switch 3 is connected with the input VIN of the second voltage control unit with electric capacity C3 contact.
The input anode of the second comparison module is connected with the contact of K switch B with the second square wave generation unit, the input negative terminal access normal voltage V-VREF of described second comparison module.
What note that K switch and K switch B receive is two contrary signals, that is, and a continuous current source I Hui Xiang mono-road capacitive branch charging simultaneously; Four electric capacity C1, the capacitance of C2, C3, C4 is equal, and when oscillating circuit work starts, four electric capacity C1, the top crown of C2, C3, C4 all needs to be reset to earth potential.In the course of the work, other 12 switches remaining are divided into two groups, are controlled respectively by K switch and K switch B.
Particularly, work as K, K1, K4 switch conduction, when KB, K2, K3 switch disconnects, continuous current source I flows to electric capacity C1, the top crown voltage V1 of electric capacity C1 raises, and this top crown voltage V1 joins the first voltage control unit input VIN, and input voltage VIN and normal voltage VREF are subtracted each other by the first voltage control unit, now, electric capacity C2 top crown is then connected on the output VOUT of the first voltage control unit; When the top crown voltage V1 of electric capacity C1 is elevated to the first comparison module upset, KB, K2, K3 switch conduction, K, K1, K4 switch disconnects, and continuous current source I charges to electric capacity C3, and electric capacity C1 top crown then keeps input voltage V1 during the first comparison module upset, and by the first voltage control unit, V-VREF being passed to the top crown of electric capacity C2, the top crown voltage V1 of electric capacity C1 is pulled down to V-VREF; Meanwhile, the top crown voltage V2 of electric capacity C3 raises, top crown voltage V2 joins the second voltage control unit input VIN, input voltage VIN and normal voltage VREF are subtracted each other by the second voltage control unit, now, electric capacity C4 top crown is then connected on the output VOUT of the second voltage control unit; When the top crown voltage V2 of described electric capacity C3 is elevated to described second comparison module upset, KB, K2, K3 switch disconnects, K, K1, K4 switch conduction, continuous current source I charges to electric capacity C1 again, electric capacity C3 top crown then keeps input voltage V2 during the second comparison module upset, and by the second voltage control unit, V-VREF being passed to the top crown of electric capacity C4, the top crown voltage V1 of electric capacity C3 is pulled down to V-VREF, and the concussion curve of generation enters into again next cycle period.
In an embodiment of the present invention, the value of voltage V1 and voltage V2 is normally equal, and the value of voltage V1 and voltage V2 and the ratio of normal voltage VREF can be 20:1 ~ 5:1, and preferably, the value of voltage V1 and voltage V2 and the ratio of normal voltage VREF are 10:1.
The value of normal voltage V-VREF generally depends on that the frequency need improving oscillating circuit is relevant, and the value of normal voltage VREF is can 0.12V.When practical application, the reset of consideration electric capacity initial condition, the implementation method of voltage control unit, voltage-controlled performance requirement can be coordinated (such as, speed and driving force etc.) and various switch in the factor such as charge injection, just significantly can improve the delay to comparison module and mismatch.
Refer to 4, Figure 4 shows that the present invention eliminates the oscillating circuit schematic diagram that comparator postpones and a preferred embodiment of mismatch is complete.In an embodiment of the present invention, the first and second voltage control units can by circuit realiration such as amplifier, analog adder or switching capacities.
Refer to Fig. 5, one embodiment of the invention eliminates a kind of way of realization schematic diagram of the logic module LOGIC in comparator delay and mismatch oscillating circuit; As shown in the figure, this logic module LOGIC comprises SR latch and two d type flip flops; The output of the first comparison module and the second comparison module meets two input R of SR latch, S respectively; Two output Q of SR latch, QB is connected with the input of two d type flip flops respectively.
Refer to Fig. 6, the waveform schematic diagram of K, KB, K1, K2, K3 and K4 that the oscillating circuit that Fig. 6 eliminates comparator delay and mismatch for one embodiment of the invention produces.As shown in the figure, the output waveform of K, KB, K1, K2, K3 and K4 just eliminates the impact of comparator delay and mismatch.
Although the present invention discloses as above with preferred embodiment; right many embodiments are citing for convenience of explanation only; and be not used to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with claims.
Claims (7)
1. eliminate the oscillating circuit of comparator delay and mismatch for one kind, it is characterized in that, described oscillating circuit comprises a continuous current source I, K switch, K switch B, the concussion of two electric capacity module, the first comparison module, the second comparison module and a logic module LOGIC; Described first comparison module is connected with described logic module LOGIC with the output of the second comparison module;
Described pair of electric capacity concussion module comprises two groups and connects and the identical square wave generation unit of structure, first square wave generation unit and the second square wave generation unit control the break-make with described continuous current source I by described K switch and K switch B respectively, described K switch and K switch B, when closing for one group, another group is certain to be disconnected;
Described first square wave generation unit comprises six switches, two capacitances electric capacity C1 identical and connected with each other respectively, C2 branch road and have first voltage control unit of normal voltage V-VREF; Wherein, described six switches comprise two and are serially connected in K switch 1 in described electric capacity C1, C2 branch road and K2, the K switch 3 K switch 1 be connected with the output VOUT of described first voltage control unit with electric capacity C1 contact, the K switch 4 K switch 1 be connected with the input VIN of described first voltage control unit with electric capacity C1 contact, the K switch 3 K switch 2 and electric capacity C2 contact are connected with the input VIN of described first voltage control unit and the K switch 4 K switch 2 be connected with the output VOUT of described first voltage control unit with electric capacity C2 contact respectively; The input anode of described first comparison module is connected with the contact of K switch with described first square wave generation unit, the input negative terminal access normal voltage V-VREF of described first comparison module;
Described second square wave generation unit comprises six switches, two capacitances electric capacity C3 identical and connected with each other respectively, C4 branch road and have second voltage control unit of normal voltage V-VREF; Wherein, described six switches comprise two and are serially connected in described electric capacity C3 respectively, K switch 3 in C4 branch road and K4, the K switch 3 that K switch 3 is connected with the output VOUT of described second voltage control unit with electric capacity C3 contact, K switch 1 that K switch 3 is connected with the input VIN of described second voltage control unit with electric capacity C3 contact, the K switch 1 that K switch 4 and electric capacity C4 contact are connected with the input VIN of described second voltage control unit and the K switch 2 that K switch 3 is connected with the output VOUT of described second voltage control unit with electric capacity C4 contact; The input anode of described second comparison module is connected with the contact of K switch B with described second square wave generation unit, the input negative terminal access normal voltage V-VREF of described second comparison module;
Wherein, described K switch and K switch B are two contrary signals, described continuous current source I loop, a Hui Xiang mono-tunnel charging simultaneously; Four electric capacity C1, C2, C3, C4 capacitance is equal, and when work starts, four electric capacity C1, the top crown of C2, C3, C4 is all reset to ground; In the course of the work, other 12 switches remaining are divided into two groups, are controlled respectively by K switch and K switch B;
Work as K, K1, K4 switch conduction, KB, K2, when K3 switch disconnects, described continuous current source I flows to described electric capacity C1, and the top crown voltage V1 of described electric capacity C1 raises, described top crown voltage V1 joins described first voltage control unit input VIN, input voltage VIN and normal voltage VREF are subtracted each other by described first voltage control unit, and now, described electric capacity C2 top crown is then connected on the output VOUT of described first voltage control unit;
When the top crown voltage V1 of described electric capacity C1 is elevated to described first comparison module upset, KB, K2, K3 switch conduction, K, K1, K4 switch disconnects, and described continuous current source I charges to described electric capacity C3, and described electric capacity C1 top crown then keeps input voltage V1 during described first comparison module upset, and by described first voltage control unit, V-VREF being passed to the top crown of described electric capacity C2, the top crown voltage V1 of described electric capacity C1 is pulled down to V-VREF; Meanwhile, the top crown voltage V2 of described electric capacity C3 raises, described top crown voltage V2 joins described second voltage control unit input VIN, input voltage VIN and normal voltage VREF are subtracted each other by described second voltage control unit, now, described electric capacity C4 top crown is then connected on the output VOUT of described second voltage control unit;
When the top crown voltage V2 of described electric capacity C3 is elevated to described second comparison module upset, KB, K2, K3 switch disconnects, K, K1, K4 switch conduction, described continuous current source I charges to described electric capacity C1 again, described electric capacity C3 top crown then keeps input voltage V2 during described second comparison module upset, and by described second voltage control unit, V-VREF being passed to the top crown of described electric capacity C4, the top crown voltage V1 of described electric capacity C3 is pulled down to V-VREF, enters next cycle period.
2. the oscillating circuit of elimination comparator delay according to claim 1 and mismatch, it is characterized in that, described first and second voltage control units are realized by amplifier, analog adder or switched-capacitor circuit.
3. the oscillating circuit of elimination comparator delay according to claim 1 and mismatch, it is characterized in that, described logic module LOGIC comprises described SR latch and two d type flip flops; The output of described first comparison module and the second comparison module meets two input R of described SR latch, S respectively; Two output Q of described SR latch, QB is connected with the input of described two d type flip flops respectively.
4. the oscillating circuit of elimination comparator delay according to claim 1 and mismatch, it is characterized in that, the value of described voltage V1 and voltage V2 is equal.
5. the oscillating circuit of elimination comparator delay according to claim 4 and mismatch, it is characterized in that, the value of described voltage V1 and voltage V2 and the ratio of normal voltage VREF are 20:1 ~ 5:1.
6. the oscillating circuit of elimination comparator delay according to claim 5 and mismatch, it is characterized in that, the value of described voltage V1 and voltage V2 and the ratio of normal voltage VREF are 10:1.
7. the oscillating circuit of elimination comparator delay according to claim 1 and mismatch, it is characterized in that, the value of described normal voltage VREF is 0.12V.
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| CN201510626725.6A CN105162418B (en) | 2015-09-28 | 2015-09-28 | A kind of oscillating circuit for eliminating comparator delay and mismatch |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109039304A (en) * | 2018-06-29 | 2018-12-18 | 南京中感微电子有限公司 | Clock circuit |
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