CN209994356U - Zero offset comparator circuit - Google Patents
Zero offset comparator circuit Download PDFInfo
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- CN209994356U CN209994356U CN201920939509.0U CN201920939509U CN209994356U CN 209994356 U CN209994356 U CN 209994356U CN 201920939509 U CN201920939509 U CN 201920939509U CN 209994356 U CN209994356 U CN 209994356U
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Abstract
The utility model relates to a zero offset comparator circuit, which comprises a comparator, a clock generating circuit and a phase inverter, the output end of the clock generating circuit is connected with the control ends of the first control switch and the third control switch, the output end of the clock generating circuit is connected with the input end of the phase inverter, the output end of the phase inverter is connected with the control ends of the second control switch and the fourth control switch, the first signal input end is connected with the positive phase input end of the comparator through the first control switch, the second signal input end is connected with the positive phase input end of the comparator through the second control switch, the reverse phase input end of the comparator is connected with the output end of the comparator through the third control switch, the signal output end is connected with the output end of the comparator through the fourth control switch, one end of the first capacitor and one end of the second capacitor are respectively connected with the reverse phase input end of the comparator and the fourth control switch, and the other ends of the first capacitor and. The circuit has simple structure and stable and reliable performance parameters, and can improve the voltage comparison precision to more than 20 times.
Description
Technical Field
The utility model relates to a comparator integrated circuit technical field especially relates to a zero offset comparator circuit, is applicable to the occasion that requires high to the offset voltage.
Background
In the field of integrated circuit design, comparators are widely used to compare voltages of two input signals. A typical Comparator (COMP) is shown in fig. 1, having two input terminals: a non-inverting Input (INP) and an inverting Input (INN), and an Output (OUT). Fig. 2 is a schematic diagram of an internal circuit of a conventional Comparator (COMP), wherein PMOS transistors P1 and P2 are differential input pairs for comparing input signals INP and INN; the PMOS pipe P4 and the NMOS pipe N3 form a rail-to-rail output stage; the resistor R1 and the capacitor C1 are used as Miller compensation, and stability of the comparator when the comparator is used for a closed loop is guaranteed.
Theoretically, when the voltage value of the input signal INN is greater than the voltage value of the input signal INP, the output OUT of the comparator COMP is at a low level; when the voltage value of the input signal INN is smaller than the voltage value of the input signal INP, the output OUT of the comparator COMP is at a high level.
However, in practice, due to the influence of circuit parameters, layout, process fluctuation and other factors, a certain offset voltage △ V (△ V may be a positive value or a negative value) exists between the input signal INN and the input signal INP of the comparator COMP, that is, when the voltage value of the input signal INN is greater than the voltage value of the input signal INP + △ V, the output OUT of the comparator COMP is at a low level, and when the voltage value of the input signal INN is less than the voltage value of the input signal INP + △ V, the output OUT of the comparator COMP is at a high level.
At present, offset voltage △ V is reduced by improving matching of device parameters in a circuit and layout of devices in a layout, but offset voltage △ V cannot be completely eliminated, △ V is about several mV to dozens of mV, and for some occasions of high-precision signal comparators requiring offset voltage △ V to be less than 1mV, the existing comparator circuit structure cannot meet the high-precision requirement.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a zero offset comparator circuit of simple structure, easily realization, this circuit have zero offset voltage's characteristics, and offset voltage in the circuit no longer receives the influence of factors such as circuit parameter, territory overall arrangement, technology fluctuation simultaneously.
In order to achieve the above object, the present invention adopts the technical solution that, a zero offset comparator circuit comprises a comparator, a clock generating circuit, a phase inverter, first to fourth control switches, and first to second capacitors, wherein an output end of the clock generating circuit is connected to control ends of the first and third control switches, an output end of the clock generating circuit is connected to an input end of the phase inverter, an output end of the phase inverter is connected to control ends of the second and fourth control switches, a first signal input end is connected to a positive input end of the comparator through the first control switch, a second signal input end is connected to a positive input end of the comparator through the second control switch, an inverting input end of the comparator is connected to an output end of the comparator through the third control switch, a signal output end is connected to an output end of the comparator through the fourth control switch, one end of the first capacitor is connected to an inverting input end of the comparator, the other end of the second capacitor is grounded, one end of the second capacitor is connected with the fourth control switch, and the other end of the second capacitor is grounded.
As an improvement of the present invention, the clock generation circuit outputs a square wave signal with a duty ratio of 50%.
As an improvement of the present invention, when the clock generating circuit outputs a high level, the first and third control switches are kept in an on state, and the second and fourth control switches are kept in an off state; when the clock generation circuit outputs a low level, the first and third control switches are kept in an off state, and the second and fourth control switches are kept in an on state.
As an improvement of the utility model, the clock generation circuit includes oscillating circuit and D trigger frequency division circuit, and the input of D trigger frequency division circuit is connected to oscillating circuit's output, and the output of D trigger frequency division circuit is as the output of clock generation circuit.
As an improvement of the utility model, first to fourth control switch adopts and to adopt single PMOS pipe or NMOS pipe to realize, also can adopt the form of the parallelly connected complementary CMOS transmission gate who constitutes of PMOS pipe and NMOS pipe to realize, uses the grid of MOS pipe as first to fourth control switch's control end.
As an improvement of the utility model, the capacity of first condenser is not less than 1pF, and the capacity of second condenser is not less than 10 pF.
Compared with the prior art, the comparator circuit provided by the utility model has the advantages of ingenious overall structure design, reasonable and simple structure and easy realization, the clock generating circuit is used for outputting square wave signals with the duty ratio of 50 percent to control the on and off of the first and the third control switches, the inverter is used for outputting reversed-phase square wave signals with the duty ratio of 50 percent to control the on and off of the second and the fourth control switches, so that the on and off states of the first and the third control switches and the on and off states of the second and the fourth control switches are always kept reverse, two voltage input signals needing to be compared are input by the first and the second signal input ends and are sent into the comparator in different time intervals, the comparator alternately works in a voltage sampling phase and a voltage comparison phase, and stores voltage through the first capacitor and the second capacitor, thereby the offset voltage of the comparator can be reduced to be within 0.1mV, compared with the existing comparator, the voltage comparison precision of the comparator is improved by more than 20 times, and the offset voltage of the comparator is effectively and theoretically offset.
Drawings
Fig. 1 is a schematic structural diagram of a conventional comparator.
Fig. 2 is a diagram showing an internal circuit configuration of a conventional comparator.
Fig. 3 is a circuit diagram of the zero offset comparator circuit according to the preferred embodiment of the present invention.
Fig. 4 is a block diagram of a clock generation circuit in the zero offset comparator circuit according to the preferred embodiment of the present invention.
Fig. 5 is a simulation result diagram of the zero offset comparator circuit according to the preferred embodiment of the present invention.
Detailed Description
For the purposes of promoting an understanding and appreciation of the invention, the invention will be further described and illustrated in connection with the accompanying drawings.
As shown in fig. 3, a zero offset comparator circuit according to a preferred embodiment of the present invention includes a comparator COMP, a clock generating circuit, an inverter, first to fourth control switches, and first to second capacitors, wherein an output terminal of the clock generating circuit is connected to control terminals of the first control switch SW1 and the third control switch SW3, an output terminal of the clock generating circuit is connected to an input terminal of the inverter, an output terminal of the inverter is connected to control terminals of the second control switch SW2 and the fourth control switch SW4, a positive input terminal INP of the comparator COMP is connected to a first signal input terminal VA through the first control switch SW1, a positive input terminal INP of the comparator COMP is connected to a second signal input terminal VB through the second control switch SW2, a negative input terminal INN of the comparator COMP is connected to an output terminal OUTA of the comparator COMP through the third control switch SW3, a signal output terminal OUT is connected to an output terminal OUTA of the comparator COMP through the fourth control switch SW4, one end of the first capacitor C1 is connected to the inverting input terminal INN of the comparator COMP, and the other end is grounded, and one end of the second capacitor C2 is connected to the fourth control switch SW4, and the other end is grounded. The first signal input end VA and the second signal input end VB are used for inputting two voltage input signals which are compared with each other with high precision in the comparator COMP, and the signal output end OUT is used for outputting a comparison result of the comparator COMP circuit.
Specifically, as shown in fig. 4, the clock generation circuit includes an oscillator circuit OSC and a D flip-flop frequency divider circuit, an output terminal of the oscillator circuit OSC is connected to an input terminal of the D flip-flop frequency divider circuit, and an output terminal of the D flip-flop frequency divider circuit serves as an output terminal of the clock generation circuit. The oscillator circuit OSC can generate a high-pulse square wave signal as a vibration source of the clock generating circuit, and then outputs a square wave signal with a certain duty ratio through the D flip-flop frequency dividing circuit. The D flip-flop frequency dividing circuit can output a square wave signal with a duty ratio of 50%, and therefore, high and low level signals with the same width in one clock cycle of the clock generation circuit. When the clock generation circuit output CLK is at a high level, the inverter output CLKB is at a low level, at which time the first control switch SW1 and the third control switch SW3 maintain an on state, and the second control switch SW2 and the fourth control switch SW4 maintain an off state; when the clock generation circuit output CLK is low and the inverter output CLKB is high, the first control switch SW1 and the third control switch SW3 maintain an off state, and the second control switch SW2 and the fourth control switch SW4 maintain an on state.
Further, the first to fourth control switches may be implemented by using a single PMOS transistor or NMOS transistor, where a gate of the PMOS transistor or NMOS transistor is used as a control end of the first to fourth control switches, and a source and a drain of the PMOS transistor or NMOS transistor are used as two ends of the first to fourth control switches. The first to fourth control switches can also be realized by adopting a CMOS transmission gate formed by connecting an NMOS tube and a PMOS tube in parallel, the input end and the output end of the CMOS transmission gate are used as the two ends of the first to fourth control switches, and the C end of the CMOS transmission gate is used as the control end of the first to fourth control switches, so that the complementary electrical characteristics of the NMOS tube and the PMOS tube are fully utilized, an input signal with a low value of the on-state resistance can be obtained no matter the control switch transmits a high level or a low level, and the signal can be effectively transmitted to the output end under various input levels.
Further, the capacity of the first capacitor C1 is not less than 1pF, and the capacity of the second capacitor C2 is not less than 10 pF. The first and second capacitors may be capacitors with small leakage current (such as gate capacitance of MOS transistor).
The operating principle of comparator COMP circuit as follows:
during one cycle of the clock generation circuit, the comparator COMP circuit goes through two phases, a voltage sampling phase and a voltage comparison phase, wherein,
(1) when the clock generating circuit outputs CLK at a high level, the first control switch SW1 and the third control switch SW3 are kept at an on state, the second control switch SW2 and the fourth control switch SW4 are kept at an off state, the voltage of the non-inverting input terminal INP of the comparator COMP is equal to the voltage of the input signal at the first signal input terminal VA, the output terminal OUTA and the inverting input terminal INN of the comparator COMP are shorted together, the comparator COMP works in a following working state at this time, the voltage of the input signal at the first signal input terminal VA and the offset voltage △ V of the comparator COMP are transmitted to the output terminal OUTA and the inverting input terminal INN of the comparator COMP, that is:
VINN=VOUTA=VINP+△V=VA+△V
(2) when the clock generating circuit outputs CLK at a low level, the first control switch SW1 and the third control switch SW3 are turned off and turned on, and the second control switch SW2 and the fourth control switch SW4 are kept on, after the third control switch SW3 is turned off, the voltage on the first capacitor C1 remains unchanged, so the voltage at the inverting input terminal INN of the comparator COMP remains equal to VA + △ V, and the voltage at the non-inverting input terminal INP of the comparator COMP remains equal to the voltage at the second signal input terminal VB, because the offset voltage △ V of the comparator COMP exists, the voltages of the two comparison signals input to the comparator COMP are VB + △ V and VA + △ V, respectively, the offset voltage △ V can cancel each other, so the final voltages of the two comparison signals of the comparator COMP are VB and VA, the offset voltage △ V of the comparator COMP is no longer included, and the fourth control switch SW4 remains on, the first control switch SW1 and the second control switch SW4 remain on, and the voltage at the output terminal of the comparison signal output terminal VA, so that the comparison signal output terminal OUT is equal to the voltage of the comparison signal output terminal outout:
VOUTA=VOUT
when the next period of the clock generation circuit comes, the clock generation circuit output CLK is at a high level, the fourth control switch SW4 keeps an off state, the voltage on the second capacitor C2 keeps unchanged, so the output voltage at the signal output terminal OUT keeps unchanged, and the comparator COMP circuit enters the next voltage sampling and voltage comparison process, and the specific simulation result is shown in fig. 5.
The utility model provides a zero offset comparator circuit's simple structure is reliable, easily realize, utilize first condenser C1 and second condenser C2 to store the comparative voltage signal of input respectively through the voltage sampling stage at comparator circuit and voltage comparison stage, comparator offset voltage signal and signal output part's voltage signal, thereby can eliminate comparator COMP's offset voltage △ V in theory, really realize two high accuracy comparisons of input comparative voltage signal, the parameter of actual device in the limited by circuit, can't really offset comparator COMP's offset voltage each other, but can reduce comparator COMP's offset voltage to within 0.1mV, compare with the comparative accuracy of current comparator, the utility model discloses a zero offset comparator circuit's comparative accuracy has improved more than 20 times.
The technical means disclosed by the scheme of the present invention is not limited to the technical means disclosed by the above embodiments, but also includes the technical scheme formed by the arbitrary combination of the above technical features. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications are also considered as the protection scope of the present invention.
Claims (7)
1. A zero offset comparator circuit, characterized by: comprises a comparator, a clock generating circuit and an inverter, the output end of the clock generating circuit is connected with the control ends of the first control switch and the third control switch, the output end of the clock generating circuit is connected with the input end of the phase inverter, the output end of the phase inverter is connected with the control ends of the second control switch and the fourth control switch, the first signal input end is connected with the positive phase input end of the comparator through the first control switch, the second signal input end is connected with the positive phase input end of the comparator through the second control switch, the reverse phase input end of the comparator is connected with the output end of the comparator through the third control switch, the signal output end is connected with the output end of the comparator through the fourth control switch, one end of the first capacitor is connected with the reverse phase input end of the comparator, the other end of the first capacitor is grounded, one end of the second capacitor is connected with the fourth control switch, and the.
2. The offset zero comparator circuit of claim 1, wherein the clock generation circuit outputs a square wave signal having a duty cycle of 50%.
3. The offset zero comparator circuit as claimed in claim 2, wherein when said clock generating circuit outputs a high level, said first and third control switches are kept at an on state, and said second and fourth control switches are kept at an off state; and when the clock generation circuit outputs a low level, the first and third control switches are kept in an off state, and the second and fourth control switches are kept in an on state.
4. The offset-nulling comparator circuit of claim 3, wherein the clock generation circuit comprises an oscillator circuit and a D-flip-flop divider circuit, an output of the oscillator circuit being coupled to an input of the D-flip-flop divider circuit, an output of the D-flip-flop divider circuit serving as an output of the clock generation circuit.
5. The offset-zero comparator circuit of claim 4, wherein the first capacitor has a capacitance not less than 1pF and the second capacitor has a capacitance not less than 10 pF.
6. A zero offset comparator circuit as claimed in any of claims 1-5 wherein said first through fourth control switches are implemented using CMOS transmission gates comprising an NMOS transistor in parallel with a PMOS transistor.
7. The zero offset comparator circuit as claimed in any of claims 1-5, wherein the first to fourth control switches are implemented by using a single PMOS transistor or NMOS transistor, and the gate of the PMOS transistor or NMOS transistor is used as the control terminal of the first to fourth control switches.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920939509.0U CN209994356U (en) | 2019-06-21 | 2019-06-21 | Zero offset comparator circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920939509.0U CN209994356U (en) | 2019-06-21 | 2019-06-21 | Zero offset comparator circuit |
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| CN209994356U true CN209994356U (en) | 2020-01-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190835A (en) * | 2019-06-21 | 2019-08-30 | 苏州锴威特半导体有限公司 | Zero imbalance comparator circuit of one kind |
| CN112859997A (en) * | 2021-02-03 | 2021-05-28 | 北京中电华大电子设计有限责任公司 | Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM |
-
2019
- 2019-06-21 CN CN201920939509.0U patent/CN209994356U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110190835A (en) * | 2019-06-21 | 2019-08-30 | 苏州锴威特半导体有限公司 | Zero imbalance comparator circuit of one kind |
| CN110190835B (en) * | 2019-06-21 | 2024-02-27 | 苏州锴威特半导体股份有限公司 | Zero offset comparator circuit |
| CN112859997A (en) * | 2021-02-03 | 2021-05-28 | 北京中电华大电子设计有限责任公司 | Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM |
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