CN112859997A

CN112859997A - Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM

Info

Publication number: CN112859997A
Application number: CN202110150549.9A
Authority: CN
Inventors: 柳雪晶; 刘明磊; 陈艳; 张洪涛; 陈永强
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2021-02-03
Filing date: 2021-02-03
Publication date: 2021-05-28
Anticipated expiration: 2041-02-03
Also published as: CN112859997B

Abstract

The invention relates to a self-calibrated bandgap reference voltage three-temperature TRIM circuit structure which is applied to a chip with higher requirement on the temperature coefficient of a reference voltage. As the chip manufacturing process enters the nanometer level, the power supply voltage cannot be reduced in the same proportion, and the leakage of the MOS device is more and more serious. However, the accurate establishment of the device leakage model is difficult for the process, and the device leakage models of many processes at present are not accurate enough. Since the magnitude of the leakage is affected by temperature, the leakage has a non-negligible effect on the temperature coefficient of the bandgap reference voltage. The leakage model is not accurate enough, and the design of the band-gap reference circuit has the problem that the temperature coefficient simulation result is greatly different from the actual chip test result. This requires that the temperature coefficient of the bandgap reference voltage be trim during the test. The design provides a low-cost scheme which has an offset self-calibration function and can realize temperature coefficient TRIM of band gap reference voltage at high temperature, normal temperature and low temperature.

Description

Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM

Technical Field

The invention relates to the field of analog circuit design, realizes the trim of the temperature coefficient of band-gap reference voltage with lower cost in mass production test, and is particularly suitable for products with higher requirements on the temperature coefficient of the band-gap reference voltage.

Background

As the chip manufacturing process enters the nanometer level, the power supply voltage cannot be reduced in the same proportion, and the leakage of the MOS device is more and more serious. However, the accurate establishment of the device leakage model is difficult for the process, and the device leakage models of many processes at present are not accurate enough. Since the magnitude of the leakage is affected by temperature, the leakage has a non-negligible effect on the temperature coefficient of the bandgap reference voltage. The leakage model is not accurate enough, and the design of the band-gap reference circuit has the problem that the temperature coefficient simulation result is greatly different from the actual chip test result. This requires that the temperature coefficient of the bandgap reference voltage be trim during the test.

Due to the increasingly developing electronic products, the product quality is improved and the price of the chip becomes one of the important concerns of consumers due to the intense competitive environment in the industry. In order to make the chip more competitive in the market, it is necessary to reduce the production cost of the chip, the test cost is an important component of the production cost, and the test cost is in positive correlation with the test time. Therefore, there is a strong need for circuit designers to devote some effort to research low-cost circuit testing schemes.

Disclosure of Invention

(1) Objects of the invention

The band gap reference voltage VREF is subjected to temperature coefficient TRIM at high temperature, normal temperature and low temperature, the VREF is measured by directly utilizing a sense line in a common method, when a plurality of chips are simultaneously measured by the method, each chip needs one sense line, the number of the used sense lines is large, more test resources are occupied, and the test cost is high. The invention aims to reduce the use of the sense line, avoid the need of one sense line for each test chip, and realize the temperature coefficient trim of VREF by only providing a force line when a plurality of chips are simultaneously tested.

Meanwhile, in order to solve the offset generated by the on-chip test solution, the design provides a low-cost scheme which can realize the offset self-calibration function and carry out temperature coefficient TRIM on the band-gap reference voltage at high temperature, normal temperature and low temperature.

(2) Technical scheme

As shown in fig. 1, a circuit structure of a bandgap reference voltage tri-temperature TRIM with self-calibration mainly includes: the bandgap reference circuit comprises a temperature coefficient regulator and a level regulator, a comparator, a binary voltage divider, a logic control unit, a switch S1, a switch S2, a switch S3 and a capacitor C1. Wherein the output V of the bandgap reference circuit_{REF_IN}One end of a switch S3 is connected, the other end of the switch S3 is connected with the positive input end of the comparator and one end of a switch S1, and the other end of the switch S1 is connected with the output V of the binary voltage divider_{REF_DIV}. One end of the capacitor C1 is connected to the GND, the other end of the capacitor C1 is connected to the negative input end of the comparator and one end of the switch S2, and the other end of the switch S2 is connected to the output end of the comparator and the input end of the logic control unit.

The logic control signal output by the logic control unit controls a temperature coefficient regulator and a level regulator of the bandgap reference circuit, a binary voltage divider, a switch S1, a switch S2 and a switch S3. The logic control unit has a clock input signal CLK.

The band-gap reference voltage circuit is provided with a temperature coefficient regulator and can output a reference voltage V_{REF_IN}The temperature coefficient can be adjusted by M control words, and M can be more than or equal to 2. The band-gap reference voltage circuit has a level regulator capable of outputting a reference voltage V_{REF_IN}The level adjustment can be performed by using an X-bit control word, and X can be more than or equal to 2.

The input signal of the binary voltage divider is a reference voltage V provided off-chip_{REF_EX}. The binary voltage divider may have an N-bit control word, and N may be greater than or equal to 2. The binary voltage divider may be paired with an off-chip reference voltage V_{REF_EX}Performing N-bit dichotomy voltage division to generate an output signal V_{REF_DIV}。

The working principle is as follows:

a schematic diagram of a circuit structure with a self-calibrated bandgap reference voltage three-temperature TRIM is shown in fig. 1. In the sampling mode, as shown in FIG. 2, switches S2 and S3 are closed, switch S1 is open, and the comparator is connectedbuffer form, will present V_{REF_IN}The level is sampled onto a capacitor C1. Then, in the successive comparison mode, as shown in FIG. 3, the logic control unit controls the switch S1 to be closed, S2 and S3 to be opened, and the logic control unit controls the binary divider control bit DIV<8:0>V sampled on the capacitor C1_{REF_IN}Value, with reference voltage V applied off-chip_{REF_EX}Comparing the values, and comparing V_{REF_IN}The values are quantized into digital codes. Controlling VOL _ TRIM<M:0>From low to high, VOL _ TRIM<M:0>Whenever a gear is changed, TC _ TRIM<X:0>Also varying from low to high, exhaustive VOL _ TRIM<M:0>And VOL _ TRIM<M:0>All the gears of (1) are changed according to V of the corresponding gear_{REF_IN}Performing digital quantization, DIV<8:0>To obtain 2^M*2^XAnd storing the quantization results.

When the chip mass production test is carried out, the test is carried out in a high-temperature environment, a normal-temperature environment and a low-temperature environment respectively, then data processing is carried out, and when VOL _ TRIM < M:0> and VOL _ TRIM < M:0> are in the same gear at three temperatures, the DIV <8:0> is the smallest in three temperature difference values. The VOL _ TRIM < M:0> and VOL _ TRIM < M:0> values are the values needed after the final test.

The circuit structure has the function of self calibration of the offset voltage of the comparator. In the sampling mode, as shown in fig. 4, the comparator holds a voltage value V on the capacitor C1_{REF_IN}-Vos. When entering the successive comparison mode, as shown in fig. 5, the positive terminal voltage of the comparator is the output voltage V of the N-bit binary voltage divider_{REF_DIV}-Vos. The voltage across the comparator is subtracted by Vos, so the influence of Vos is eliminated, and the function of self calibration is achieved.

Drawings

FIG. 1 is a schematic diagram of a circuit structure of a bandgap reference voltage three-temperature TRIM with self-calibration

FIG. 2 sampling pattern

FIG. 3 successive comparison mode

FIG. 4 offset Voltage in sampling mode

FIG. 5 offset voltage in comparison mode

Detailed Description

The circuit diagram of the invention as shown in fig. 1 comprises a bandgap reference circuit, a comparator, a binary voltage divider, a logic control unit, a switch S1, a switch S2, a switch S3 and a capacitor C1. Wherein the output V of the bandgap reference circuit_{REF_IN}One end of a switch S3 is connected, the other end of the switch S3 is connected with the positive input end of the comparator and one end of a switch S1, and the other end of the switch S1 is connected with the output V of the binary voltage divider_{REF_DIV}. One end of the capacitor C1 is connected to the GND, the other end of the capacitor C1 is connected to the negative input end of the comparator and one end of the switch S2, and the other end of the switch S2 is connected to the output end of the comparator and the input end of the logic control unit.

Assume that the TRIM regulator TRIM bit is 4 bits, the level regulator is 4 bits, and the binary divider is 9 bits. V_{REF_IN}The expected ideal value is 0.9V, V at the chip_{REF_EX}pad applied off-chip reference voltage V_{REF_EX}The value was 1V.

Step 1: the logic control unit controls VOL _ TRIM in the first clock period T1 of the input clock CLK<3:0>0000 and TC _ TRIM<3:0>0000, the sampling mode is first entered, as shown in fig. 2, switches S2 and S3 are closed, switch S1 is open, the comparator is connected in buffer form, V is connected_{REF_IN}The level is sampled onto a capacitor C1.

Step 2: in the second to 10 th clock cycles, as shown in fig. 3, the logic control unit controls the switch S1 to be closed, and S2 and S3 to be opened, and enters the successive comparison mode. In the second clock period T2, the logic control unit controls the binary divider control bit DIV<8:0>100000000 output V_{REF_DIV}＝V_{REF_OUT}/2, comparator pair V_{REF_DIV}And V_{REF_IN}Making a comparison, e.g. V_{REF_DIV}<V_{REF_IN}Then at the next missing period T3, DIV<8:0>Set to 110000000; such as V_{REF_DIV}>V_{REF_IN}Then at the next missing period T3, DIV<8:0>Set to 010000000. And so on until the 10 th clock cycle, DIV<8:0>All of the 9 bits of completion. At the 11 th clock cycle, the logic control unit records the value, i.e. VOL _ TRIM<3:0>0000 and TC _ TRIM<3:0>When 0000, the reference voltage VREF _ IN is digitally quantized.

And step 3: and continuing to control VOL _ TRIM <3:0> to be 0000, and TC _ TRIM <3:0> to change from 0001 to 1111, and repeating the sampling and successive comparison modes of the step 1 and the step 2 every time the gear is changed.

And 4, step 4: and continuously controlling VOL _ TRIM <3:0> to change from 0001 to 1111, and repeating the processes of the step 1, the step 2 and the step 3 every time the gear is changed.

And 5: after the 4 steps, the logic control unit stores DIV<8:0>Number of values of 2⁴*2⁴The time consumed is 2⁴*2⁴11 clock cycles.

Claims

1. A self-calibrated bandgap reference voltage three-temperature TRIM circuit structure is characterized by comprising: bandgap reference circuit with a temperature coefficient regulator and a level regulator, comparator, binary voltage divider, logic control unit, switch S1, switch S2, switch S3, capacitor C1, wherein the output V of the bandgap reference circuit_{REF_IN}One end of a switch S3 is connected, the other end of the switch S3 is connected with the positive input end of the comparator and one end of a switch S1, and the other end of the switch S1 is connected with the output V of the binary voltage divider_{REF_DIV}One end of the capacitor C1 is connected to the ground GND, the other end of the capacitor C1 is connected to the negative input end of the comparator and one end of the switch S2, and the other end of the switch S2 is connected to the output end of the comparator and the input end of the logic control unit.

2. The circuit structure of claim 1, wherein the logic control signal output by the logic control unit controls a temperature coefficient regulator and a level regulator of the bandgap reference circuit, a binary voltage divider, a switch S1, a switch S2, and a switch S3.

3. The circuit arrangement of claim 1, wherein said logic control unit has a clock input signal CLK.

4. The circuit structure of claim 1, wherein said bandgap referenceThe voltage circuit has a temperature coefficient regulator for outputting a reference voltage V_{REF_IN}The adjustment of the temperature coefficient is carried out by M bit control words, and M is more than or equal to 2.

5. The circuit structure of claim 1, wherein the bandgap reference voltage circuit comprises a level adjuster capable of outputting a reference voltage V_{REF_IN}The adjustment of the level is performed by an X control word, wherein X is more than or equal to 2.

6. The circuit arrangement of claim 1, wherein said binary voltage divider has an input signal of an off-chip reference voltage V_{REF_EX}(ii) a The binary voltage divider has N bit control words, N is more than or equal to 2; the binary voltage divider can be used for comparing an off-chip reference voltage V_{REF_EX}Performing N-bit dichotomy voltage division to generate an output signal V_{REF_DIV}。