CN202120153U - Band-gap reference voltage generation circuit - Google Patents
Band-gap reference voltage generation circuit Download PDFInfo
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- CN202120153U CN202120153U CN2011201799691U CN201120179969U CN202120153U CN 202120153 U CN202120153 U CN 202120153U CN 2011201799691 U CN2011201799691 U CN 2011201799691U CN 201120179969 U CN201120179969 U CN 201120179969U CN 202120153 U CN202120153 U CN 202120153U
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Abstract
The utility model discloses a band-gap reference voltage generation circuit which comprises a biasing circuit, a core circuit, a second decoder and a second trimming circuit, wherein the biasing circuit generates a biasing current under the action of an external power supply; the core circuit is connected with the biasing circuit and generates an output voltage under the action of the biasing current; the core circuit comprises a first decoder and a first trimming circuit; the first decoder is used for decoding according to a first preset value so as to obtain a first trimming control signal; the first trimming circuit is used for trimming the output voltage according to the first trimming control signal; the second decoder is used for decoding according to a second preset value so as to obtain a second trimming control signal; and the second trimming circuit is used for trimming a reference voltage according to the second trimming control signal. The first and second decoders are respectively used for decoding according to the first and second preset values; the first and second trimming control signals output via the decoding are respectively used for trimming the output voltage and the reference voltage; and through the two levels of trimming, the reference voltage with more stable absolute voltage value can be obtained.
Description
Technical field
The utility model relates to hybrid digital-analog integrated circuit, is specifically related to a kind of Bandgap Reference Voltage Generation Circuit.
Background technology
Accurate reference voltage source is crucial in A/D, D/A, comparer, power management chip and other mimic channels.For reference voltage source, require it can overcome technology, power supply, temperature and load variations and keep stable, and can under standard technology, make.Bandgap voltage reference because of have low-temperature coefficient, high PSRR, low reference voltage and long-time stability and with main stream of CMOS technology mutually advantage such as compatibility be widely adopted.
The main difficult point that designs accurate reference voltage is how to reduce the deviation and the temperature coefficient of reference voltage value.Under the prerequisite that does not adopt correction technique, these two indexs are generally 4% (benchmark for 1.2V is equivalent to ± 50 mV) and about 100ppm/ ℃.
Because technological fluctuation and operational amplifier are introduced the influence of offset voltage, actual produced band-gap reference reference voltage has bigger temperature coefficient usually, and the absolute value of while reference voltage also fluctuates bigger, needs the subsequent calibrations step usually for this reason.In design in the past, suppress the fluctuation that causes by technology through adopting pure simulation process or other special process, and adopt laser trimming or other method for repairing and regulating that output reference voltage is calibrated.In addition, in order to reduce the influence that offset voltage brings, adopt copped wave, technology such as zeroing is eliminated offset voltage certainly, or reduce offset voltage through increasing power consumption and chip area.No matter adopt above-mentioned which kind of method, all need raise the cost, increase circuit complexity or other performance of sacrifice circuit, and have certain limitation.
Therefore, how to utilize lower technology cost, circuit design simple in structure to go out the bandgap voltage reference that temperature coefficient is lower and the reference voltage absolute value is stable, become the problem that present these those skilled in the art press for solution.
The utility model content
The utility model has middle bandgap voltage reference absolute value problem of unstable now for solving, thereby provides a kind of absolute value stable Bandgap Reference Voltage Generation Circuit.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
A kind of Bandgap Reference Voltage Generation Circuit comprises: biasing circuit produces bias current under the effect of extraneous power supply; Core circuit; Connect above-mentioned biasing circuit; Under the effect of said bias current, produce output voltage; Said core circuit comprises that first code translator and first repaiies demodulation circuit, and said first code translator is deciphered according to first preset value and obtained first and repair regulation and control system signal, and said first repaiies regulation and control system signal controlling first repaiies demodulation circuit output voltage is repaiied accent; Second code translator deciphers to obtain second and repair regulation and control systems signal according to second preset value; Second repaiies demodulation circuit, repaiies regulation and control system signal according to second reference voltage is repaiied accent.
Preferably, said second repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, one of them master switch connects the two ends after the resistance series connection, and an end of other switches connects the node between the resistance in series respectively, and the other end all connects an end of said master switch.
Preferably, said second repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, a plurality of switches are all parallelly connected with corresponding resistance.
Preferably, said first repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said first repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, one of them master switch connects the two ends after the resistance series connection, and an end of other switches connects the node between the resistance in series respectively, and the other end all connects an end of said master switch.
Preferably, said first repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said first repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, a plurality of switches are all parallelly connected with corresponding resistance.
Further, said core circuit also comprises integrated operational amplifier, PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the first transistor, transistor seconds, the 3rd transistor, first resistance; The offset side of integrated operational amplifier connects the output terminal of biasing circuit; The source electrode of the source electrode of said PMOS pipe, the 2nd PMOS pipe all is connected power supply with the source electrode of the 3rd PMOS pipe, and the grid of the grid of PMOS pipe, the 2nd PMOS pipe all links together with the grid of the 3rd PMOS pipe and is connected with the output terminal of integrated operational amplifier; The grid of the grid of the first transistor and collector, transistor seconds all is connected with earth signal with collector with collector and the 3rd transistorized grid; The emitter of the first transistor all is connected with the first input end of integrated operational amplifier with the drain electrode of PMOS pipe; The emitter of transistor seconds is connected with second input end of integrated operational amplifier through first resistance, and second input end of integrated operational amplifier connects the drain electrode of the 2nd PMOS pipe; The 3rd transistorized emitter is repaiied demodulation circuit through first and is connected with the drain electrode of the 3rd PMOS pipe; First code translator is deciphered according to first preset value and is obtained first and repair regulation and control systems signal; First repaiies demodulation circuit, repaiies regulation and control system signal according to first the output voltage of the 3rd PMOS pipe drain electrode is repaiied accent.
Further, above-mentioned first input end is a negative input end, and second input end is a positive input terminal.
Preferably; Bandgap Reference Voltage Generation Circuit also comprises second amplifier and second resistance; The first input end of said second amplifier connects the output voltage of said core circuit; The output terminal of second amplifier is repaiied through second successively and is connected with earth signal after demodulation circuit is connected with second resistance, and the node of the demodulation circuit and second resistance is repaiied in second input end connection second of second amplifier.
Preferably, above-mentioned first input end is a positive input terminal, and second input end is a negative input end.
Preferably; Bandgap Reference Voltage Generation Circuit also comprises the 3rd amplifier, the 4th amplifier, second resistance, the 3rd resistance and the 4th resistance; The first input end of said the 3rd amplifier connects the output voltage of said core circuit; Second input end of the 3rd amplifier connects output terminal, and the output terminal of the 3rd amplifier is connected to earth signal after connecting through the 3rd resistance and the 4th resistance; The first input end of said the 4th amplifier connects the node of the 3rd resistance and the series connection of the 4th resistance; The output terminal of the 4th amplifier is repaiied through second successively and is connected with earth signal after demodulation circuit is connected with second resistance, and the node of the demodulation circuit and second resistance is repaiied in second input end connection second of the 4th amplifier.
Preferably, above-mentioned first input end is a positive input terminal, and second input end is a negative input end.
Compared with prior art; The utlity model has following beneficial effect: a kind of Bandgap Reference Voltage Generation Circuit that the utility model provides; First code translator and second code translator are deciphered respectively according to first preset value and second preset value; First of decoding output is repaiied regulation and control system signal and second and is repaiied regulation and control system signal and respectively output voltage and reference voltage are repaiied accent, repaiies accent through this secondary and can obtain absolute value of voltage than stable benchmark voltage.
Description of drawings
Fig. 1 is an embodiment of the invention Bandgap Reference Voltage Generation Circuit theory diagram.
Fig. 2 is an embodiment of the invention core circuit theory diagram.
Fig. 3 is that the second embodiment of the invention Bandgap Reference Voltage Generation Circuit is simplified theory diagram.
Fig. 4 is that the third embodiment of the invention Bandgap Reference Voltage Generation Circuit is simplified theory diagram.
Fig. 5 is that first embodiment of the invention first is repaiied demodulation circuit or second and repaiied the demodulation circuit schematic diagram.
Fig. 6 is that second embodiment of the invention first is repaiied demodulation circuit or second and repaiied the demodulation circuit schematic diagram.
Fig. 7 is an embodiment of the invention bandgap voltage reference output waveform figure.
Embodiment
Clearer for technical matters, technical scheme and beneficial effect that the utility model is solved, below in conjunction with accompanying drawing and embodiment, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 1 is an embodiment of the invention Bandgap Reference Voltage Generation Circuit theory diagram; Disclose a kind of Bandgap Reference Voltage Generation Circuit, having comprised: biasing circuit 1 produces bias current under the effect of extraneous power supply; Core circuit 2; Connect above-mentioned biasing circuit 1; Under the effect of said bias current, produce output voltage; Said core circuit 2 comprises that first code translator 22 and first repaiies demodulation circuit 23, and said first code translator 22 is deciphered according to first preset value and obtained first and repair regulation and control system signal, and said first repaiies regulation and control system signal controlling first repaiies 23 pairs of output voltages of demodulation circuit and repair accent; Second code translator 4 deciphers to obtain second and repair regulation and control systems signal according to second preset value; Second repaiies demodulation circuit 5, repaiies regulation and control system signal according to second reference voltage is repaiied accent.First code translator 22 and second code translator 4 are deciphered respectively according to first preset value and second preset value; First of decoding output is repaiied regulation and control system signal and second and is repaiied regulation and control system signal and respectively output voltage and reference voltage are repaiied accent, repaiies accent through this secondary and can obtain absolute value of voltage than stable benchmark voltage.
Fig. 2 is an embodiment of the invention core circuit theory diagram; This core circuit 2 comprises that integrated operational amplifier U1, PMOS pipe M1, the 2nd PMOS pipe M2, the 3rd PMOS pipe M3, the first transistor Q1, transistor seconds Q2, the 3rd transistor Q3, first resistance R 1, first code translator 22, first repair demodulation circuit 23; The offset side of integrated operational amplifier U1 connects the output terminal of biasing circuit 1; The source electrode of the source electrode of said PMOS pipe M1, the 2nd PMOS pipe M2 all is connected power supply with the source electrode of the 3rd PMOS pipe M3, and the grid of the grid of PMOS pipe M1, the 2nd PMOS pipe M2 all links together with the grid of the 3rd PMOS pipe M3 and is connected with the output terminal of integrated operational amplifier U1; The grid of the grid of the first transistor Q1 and collector, transistor seconds Q2 all is connected with earth signal with collector with the grid of collector and the 3rd transistor Q3; The emitter of the first transistor Q1 all is connected with the first input end of integrated operational amplifier U1 with the drain electrode of PMOS pipe M1; The emitter of transistor seconds Q2 is connected with second input end of integrated operational amplifier U1 through first resistance R 1, and second input end of integrated operational amplifier U1 connects the drain electrode of the 2nd PMOS pipe M2; The emitter of the 3rd transistor Q3 is repaiied demodulation circuit 23 through first and is connected with the drain electrode of the 3rd PMOS pipe M3; First code translator 22 is deciphered according to first preset value and is obtained first and repair regulation and control systems signal; First repaiies demodulation circuit 23, repaiies regulation and control system signal according to first the output voltage of the 3rd PMOS pipe M3 drain electrode is repaiied accent.First input end is a negative input end in the present embodiment, and second input end is a positive input terminal.
Fig. 3 is that the second embodiment of the invention Bandgap Reference Voltage Generation Circuit is simplified theory diagram; Present embodiment also comprises the second amplifier U2 and second resistance R 2 on the basis of Fig. 1; The first input end of the said second amplifier U2 connects the output voltage of said core circuit 2; The output terminal of the second amplifier U2 is repaiied through second successively and is connected with earth signal after demodulation circuit 5 is connected with second resistance R 3, and second input end of the second amplifier U2 connects second and repaiies the node of the demodulation circuit 5 and second resistance R 2.First input end in the present embodiment is a positive input terminal, and second input end is a negative input end.
Fig. 4 is that the third embodiment of the invention Bandgap Reference Voltage Generation Circuit is simplified theory diagram; Present embodiment also comprises the 3rd amplifier U3, the 4th amplifier U4, second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4 on the basis of Fig. 1; The first input end of said the 3rd amplifier U3 connects the output voltage of said core circuit 2; U3 second input end of the 3rd amplifier connects output terminal, and the output terminal of the 3rd amplifier U3 is connected to earth signal after connecting through the 3rd resistance R 3 and the 4th resistance R 4; The first input end of said the 4th amplifier U4 connects the node of the 3rd resistance R 3 and 4 series connection of the 4th resistance R; The output terminal of the 4th amplifier U4 is repaiied through second successively and is connected with earth signal after demodulation circuit 5 is connected with second resistance R 3, and second input end of the 4th amplifier U4 connects second and repaiies the node of the demodulation circuit 5 and second resistance R 2.First input end in the present embodiment is a positive input terminal, and second input end is a negative input end.
First repaiies demodulation circuit and second and repaiies demodulation circuit to adopt same circuits, Fig. 5 be that first embodiment of the invention first is repaiied demodulation circuit or second and repaiied the demodulation circuit schematic diagram in the present embodiment; Second repair demodulation circuit 5 and first repair demodulation circuit 23 include a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies regulation and control systems signal and first repaiies conducting and the disconnection that regulation and control system signal is all controlled a plurality of switches; Said a plurality of resistance series connection, one of them master switch connects the two ends after the resistance series connection, and an end of other switches connects the node between the resistance in series respectively, and the other end all connects an end of said master switch.Shown in figure, switch S 32 is a master switch, if this switch conduction, then all a plurality of resistance are all by short circuit, and the resistance in the place in circuit is 0.
Fig. 6 is that second embodiment of the invention first is repaiied demodulation circuit or second and repaiied the demodulation circuit schematic diagram; Second repair demodulation circuit and first repair demodulation circuit 23 include a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies regulation and control systems signal and first repaiies conducting and the disconnection that regulation and control system signal is all controlled a plurality of switches; Said a plurality of resistance series connection, a plurality of switches are all parallelly connected with corresponding resistance.
Below be example explanation Bandgap Reference Voltage Generation Circuit principle with Fig. 2, Fig. 4 and Fig. 5:
The one PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 constitute current-mirror structure, and in the present embodiment, PMOS pipe M1, the 2nd PMOS pipe M2 and the 3rd PMOS pipe M3 are identical metal-oxide-semiconductor, and the electric current that flows through three metal-oxide-semiconductors is identical.The electric current of the 3rd PMOS pipe M3 mirror image the 2nd PMOS pipe M2, this electric current flow through first to be repaiied demodulation circuit 23, the first to repair the circuit structure of demodulation circuit 23 is example with Fig. 6, and different according to the corresponding on off state of institute, the resistance of place in circuit also can be different.What the electric current that therefore flows through the 3rd PMOS pipe M3 flow through place in circuit repaiies accent resistance, repaiies demodulation circuit resistance two ends first and forms pressure drop, and this pressure drop can be expressed as R
23* (VBE1-VBE2)/R1, wherein R
23Be first to repair the resistance that demodulation circuit inserts, have positive temperature coefficient (PTC), the base-emitter voltage VBE3 addition with the 3rd transistor Q3 can get output voltage again:
VBGR=VBE3+R
23*?(VBE1-VBE2)/R1
Therefore output voltage values VBGR is exactly a reference voltage, because actual conditions can be different with ideal design, therefore can repair demodulation circuit 23 through first and carry out the first order and repair accent, guarantees that output voltage V BGR has lower temperature coefficient.The resistance number that demodulation circuit 23 places in circuit are repaiied in change first can change R
23Resistance, and then obtain good temperature coefficient.
Should be noted that in the present embodiment first code translator 22 is identical with second code translator 4, can be the 5-32 bit decoder; First repaiies demodulation circuit 23 and second, and to repair demodulation circuit 5 circuit also identical, shown in accompanying drawing 4, transfers the resistance series connection by repairing of equating of 32 resistances, and these 32 resistance are controlled by respective switch respectively.Through the value (REG1 among the design < 4:0>is 10000 with the default value of REG2 < 4:0 >) that changes the first preset value REG1 < 4:0>(the second preset value REG2 < 4:0 >); Can obtain 32 corresponding control signals through 5-32 bit decoder circuit; And then control first repair switch in the demodulation circuit 23 (second repaiies demodulation circuit 5) on off state, to change the resistance of place in circuit.
First repaiies demodulation circuit 23 for regulating the temperature coefficient of reference voltage; When the actual temperature coefficient that records output voltage V BGR departs from greatly; Can repair the number of transferring resistance access circuit through regulating the size of the first preset value REG1 < 4:0 >, changing, obtain lower temperature and float.For example: when temperature coefficient is shown as approximate positive temperature coefficient (PTC); REG1 < 4:0>value can be regulated in < 00000 ~ 10000>scope; The number of repairing this moment first in demodulation circuit 23 places in circuit reduces; Therefore positive temperature coefficient (PTC) voltage reduces, and the finishing temperature coefficient curve is about a certain temperature left-right symmetric; When temperature coefficient is similar to negative temperature coefficient; The value of REG1 < 4:0>can be regulated in < 10000 ~ 11111>scope; The number of repairing this moment first in demodulation circuit 23 places in circuit increases; Therefore positive temperature coefficient (PTC) voltage increases, and the finishing temperature coefficient curve first is repaiied the effect that demodulation circuit has been accomplished the temperature coefficient adjusting thus about a certain temperature left-right symmetric.
Second repaiies demodulation circuit 5 for regulating the absolute value precision of reference voltage; When the actual absolute value that records reference voltage and ideal design value deviation are big; Can be through regulating the size of the second preset value REG2 < 4:0 >; The number that the demodulation circuit place in circuit is repaiied in change second obtains the accurate reference voltage of absolute value (the design's value is 1.2V).For example: as the actual VREF that records>during 1.2V; The value of REG2 < 4:0>can be regulated in < 00000 ~ 10000>scope; According to the value that the accent precision can calculate REG2 < 4:0>of repairing that designs; Repairing in the present embodiment and transferring precision is 2mV, repair and transfer precision to repair the voltage drop of transferring the resistance two ends for each, therefore through change repair accent resistance then the number in the circuit can change final VREF value.Suppose the actual VREF=1.204V that records; Calculate the accent resistance number of repairing that needs to change and be (1.204-1.2)/0.002=2; Being converted into binary number with 2 is 00010; Use again default value 10000 deduct 00010 promptly obtain REG2 < 4:0>value be 01110, that promptly reduces by two places in circuit this moment repaiies accent resistance; < during 1.2V, the value of REG2 < 4:0>can be regulated in < 10000 ~ 11111>scope as the actual VREF that records.Suppose the actual VREF=1.196V that records; Calculate the accent resistance number of repairing that needs this moment to change and be (1.2-1.196)/0.002=2; Being converted into binary number with 2 is 00010; Use default value 10000 add 00010 promptly obtain REG2 < 4:0>value be 10010, what promptly increase by two places in circuit this moment repaiies accent resistance.
In an embodiment, final reference voltage V REF output waveform is the bandgap voltage reference output waveform figure shown in accompanying drawing 5.Can see that the reference voltage that obtains has quite high precision, temperature coefficient is merely 10
6* size is about 1.2V about (1.2-1.198)/(1.2*195)=8ppm/ ℃, and under the room temperature, and the desirable output of this circuit is decided to be 1.2V.Can see that repair secondary that demodulation circuit 23 and second repaiies demodulation circuit 5 through first and repair and transfer the reference voltage that obtains, not only temperature coefficient is lower, and the absolute value deviation is also less, has very high precision.
The above is merely the preferred embodiment of the utility model; Not in order to restriction the utility model; Any modification of being done within all spirit and principles at the utility model, be equal to replacement and improvement etc., all should be included within the protection domain of the utility model.
Claims (11)
1. a Bandgap Reference Voltage Generation Circuit is characterized in that, comprising:
Biasing circuit produces bias current under the effect of extraneous power supply;
Core circuit; Connect above-mentioned biasing circuit; Under the effect of said bias current, produce output voltage; Said core circuit comprises that first code translator and first repaiies demodulation circuit, and said first code translator is deciphered according to first preset value and obtained first and repair regulation and control system signal, and said first repaiies regulation and control system signal controlling first repaiies demodulation circuit output voltage is repaiied accent;
Second code translator deciphers to obtain second and repair regulation and control systems signal according to second preset value;
Second repaiies demodulation circuit, repaiies regulation and control system signal according to second reference voltage is repaiied accent.
2. Bandgap Reference Voltage Generation Circuit according to claim 1; It is characterized in that; Said second repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, one of them master switch connects the two ends after the resistance series connection, and an end of other switches connects the node between the resistance in series respectively, and the other end all connects an end of said master switch.
3. Bandgap Reference Voltage Generation Circuit according to claim 1; It is characterized in that; Said second repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said second repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, a plurality of switches are all parallelly connected with corresponding resistance.
4. Bandgap Reference Voltage Generation Circuit according to claim 1, said first repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said first repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, one of them master switch connects the two ends after the resistance series connection, and an end of other switches connects the node between the resistance in series respectively, and the other end all connects an end of said master switch.
5. Bandgap Reference Voltage Generation Circuit according to claim 1; It is characterized in that; Said first repair demodulation circuit comprise a plurality of resistance and with a plurality of one to one switches of resistance, said first repaiies the conducting and the disconnection of a plurality of switches of regulation and control systems signal controlling; Said a plurality of resistance series connection, a plurality of switches are all parallelly connected with corresponding resistance.
6. according to each described Bandgap Reference Voltage Generation Circuit of claim 1 to 5; It is characterized in that said core circuit comprises that also integrated operational amplifier, PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the first transistor, transistor seconds, the 3rd transistor, first resistance, first code translator, first repair demodulation circuit; The offset side of integrated operational amplifier connects the output terminal of biasing circuit; The source electrode of the source electrode of said PMOS pipe, the 2nd PMOS pipe all is connected power supply with the source electrode of the 3rd PMOS pipe, and the grid of the grid of PMOS pipe, the 2nd PMOS pipe all links together with the grid of the 3rd PMOS pipe and is connected with the output terminal of integrated operational amplifier; The grid of the grid of the first transistor and collector, transistor seconds all is connected with earth signal with collector with collector and the 3rd transistorized grid; The emitter of the first transistor all is connected with the first input end of integrated operational amplifier with the drain electrode of PMOS pipe; The emitter of transistor seconds is connected with second input end of integrated operational amplifier through first resistance, and second input end of integrated operational amplifier connects the drain electrode of the 2nd PMOS pipe; The 3rd transistorized emitter is repaiied demodulation circuit through first and is connected with the drain electrode of the 3rd PMOS pipe; First code translator is deciphered according to first preset value and is obtained first and repair regulation and control systems signal; First repaiies demodulation circuit, repaiies regulation and control system signal according to first the output voltage of the 3rd PMOS pipe drain electrode is repaiied accent.
7. Bandgap Reference Voltage Generation Circuit according to claim 6 is characterized in that, said first input end is a negative input end, and second input end is a positive input terminal.
8. Bandgap Reference Voltage Generation Circuit according to claim 1; It is characterized in that; Also comprise second amplifier and second resistance; The first input end of said second amplifier connects the output voltage of said core circuit, and the output terminal of second amplifier is repaiied through second successively and is connected with earth signal after demodulation circuit is connected with second resistance, and the node of the demodulation circuit and second resistance is repaiied in second input end connection second of second amplifier.
9. Bandgap Reference Voltage Generation Circuit according to claim 8 is characterized in that, said first input end is a positive input terminal, and second input end is a negative input end.
10. Bandgap Reference Voltage Generation Circuit according to claim 1; It is characterized in that; Also comprise the 3rd amplifier, the 4th amplifier, second resistance, the 3rd resistance and the 4th resistance; The first input end of said the 3rd amplifier connects the output voltage of said core circuit, and second input end of the 3rd amplifier connects output terminal, and the output terminal of the 3rd amplifier is connected to earth signal after connecting through the 3rd resistance and the 4th resistance; The first input end of said the 4th amplifier connects the node of the 3rd resistance and the series connection of the 4th resistance; The output terminal of the 4th amplifier is repaiied through second successively and is connected with earth signal after demodulation circuit is connected with second resistance, and the node of the demodulation circuit and second resistance is repaiied in second input end connection second of the 4th amplifier.
11. Bandgap Reference Voltage Generation Circuit according to claim 10 is characterized in that, said first input end is a positive input terminal, and second input end is a negative input end.
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- 2011-05-31 CN CN2011201799691U patent/CN202120153U/en not_active Expired - Fee Related
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| CN109799865A (en) * | 2017-11-17 | 2019-05-24 | 三星电子株式会社 | Generating circuit from reference voltage and integrated circuit including it |
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| CN110277966A (en) * | 2019-05-09 | 2019-09-24 | 上海类比半导体技术有限公司 | A kind of self-calibration circuit and calibration method |
| CN110277966B (en) * | 2019-05-09 | 2023-03-14 | 上海类比半导体技术有限公司 | Self-calibration circuit and calibration method |
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| CN113625822B (en) * | 2020-05-07 | 2022-07-12 | 圣邦微电子（北京）股份有限公司 | Circuit for improving electric parameter trimming precision in wide range |
| CN113625822A (en) * | 2020-05-07 | 2021-11-09 | 圣邦微电子（北京）股份有限公司 | Circuit for improving electric parameter trimming precision in wide range |
| CN113848415A (en) * | 2021-01-28 | 2021-12-28 | 江西理工大学 | IRF generator, fault resistance generation method and IRF injection method |
| CN112859997A (en) * | 2021-02-03 | 2021-05-28 | 北京中电华大电子设计有限责任公司 | Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM |
| CN113220064A (en) * | 2021-05-27 | 2021-08-06 | 苏州华太电子技术有限公司 | Quick-start linear voltage stabilizer and electronic circuit |
| WO2023125047A1 (en) * | 2021-12-31 | 2023-07-06 | 思瑞浦微电子科技(上海)有限责任公司 | Bandgap reference voltage calibration method |
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