JP7316116B2 - semiconductor equipment - Google Patents

Description

The present invention relates to reference current sources.

Generally, a semiconductor integrated circuit has a reference current source that generates a constant reference current that does not depend on the power supply voltage, etc. This reference current is copied and distributed as a bias current to various circuit blocks within the semiconductor integrated circuit. be.

FIG. 1 is a circuit diagram of a conventional reference current source 100R. Reference current source 100R includes transistors M1-M4 and resistor R. FIG. M1 and M2 are NMOS transistors, and M3 and M4 are PMOS transistors.

Transistors M1 and M2 have a size ratio of 1:n. The transistors M3 and M4 are current mirror circuits with a mirror ratio of one.

Let I _ref be the current flowing through the transistors M1 to M4. When the gate-source voltages of the transistors M1 and M2 are respectively V _gs1 and V _gs2 , Equation (1) holds.
I _ref =(V _gs1 -V _gs2 )/R

Transistors M1 and M2 operate in the saturation region. Equation (2) holds for transistor M1, and equation (3) holds for transistor M2.
I _ref =1/2×μ _n C _ox ·(W/L)(V _gs1 −V _TH ) ² (2)
I _ref =1/2×μ _n C _ox ·(n·W/L)(V _gs2 −V _TH ) ² (3)
μ _n : Mobility of NMOS transistor C _ox : Capacity per unit area W/L : Ratio of gate width to gate length V _TH : Threshold voltage

Let K=W/L. Equations (2) and (3) can be transformed into equations (4) and (5).
√(2I _ref /μ _n C _ox K)=V _gs1 −V _TH (4)
√(2I _ref /μ _n C _ox ·nK)=V _gs2 −V _TH (5)

Substitute the equations (4) and (5) into the equation (1) and rearrange them.

From the above, the reference current is represented by Equation (6).

Japanese Patent Application Laid-Open No. 2001-344028 JP 2006-133869 A

From equation (6), the reference current I _ref does not depend on the threshold voltage V _TH . Therefore, variations in resistance R, element size (that is, n and K), oxide film thickness (that is, C _ox ), mobility μ _n , and the like are factors of variation. Also, the mobility μ _n , the resistance R, etc. have temperature dependence, but since the only variable is the element size (n and K), it is difficult to adjust the temperature dependence (temperature characteristic) of the reference current I _ref .

The present invention has been made in view of these problems, and one exemplary object of certain aspects thereof is to provide a reference current source with a circuit type different from the conventional one.

One aspect of the invention relates to a reference current source. The reference current source supplies a first transistor and a second transistor whose control terminals are connected to each other and a second path including the first transistor with the same amount of current as a current flowing in the first path including the second transistor, A current mirror circuit is provided on the third path and has a source connected to one end of the first transistor. a fourth transistor provided on the third path on the lower potential side than the third transistor and having a gate commonly connected to the gate of the third transistor; and a resistor provided between one end.

The third transistor and the fourth transistor may operate in the subthreshold region.

The reference current source may further include a fifth transistor provided on the lower potential side than the fourth transistor on the third path. The voltage at the control terminal of the fifth transistor may be supplied to the gates of the third and fourth transistors.

The current mirror circuit may include a sixth transistor connected to the first transistor, a seventh transistor connected to the second transistor, and an eighth transistor connected to the third path.

Another aspect of the invention is also a reference current source. The reference current source supplies a first transistor and a second transistor whose control terminals are connected to each other, a second path including the first transistor, and the same amount of current as a current flowing in the first path including the second transistor. , and a current mirror circuit for supplying a current of a predetermined several times as much as the current of the first path to a third path separate from it, and a current mirror circuit provided in series on the third path, with their respective gates connected in common. and a plurality of MOS transistors. One end of the first transistor is connected to one end of one of the plurality of MOS transistors, and one end of the second transistor is connected to another one end of the plurality of MOS transistors via a resistor.

The sizes of the first transistor and the second transistor may be equal. Also, the first transistor and the second transistor may be FETs (Field Effect Transistors). The first transistor and the second transistor may be bipolar transistors.

It should be noted that arbitrary combinations of the above-described constituent elements and mutually replacing the constituent elements and expressions of the present invention in methods, devices, systems, etc. are also effective as embodiments of the present invention.

According to one aspect of the present invention, a non-conventional reference current source can be provided.

1 is a circuit diagram of a conventional reference current source; FIG. 2 is a circuit diagram of a reference current source according to Embodiment 1; FIG. FIG. 4 is a circuit diagram of a reference current source according to Example 1.1; 4 is a diagram showing temperature characteristics of the reference current source of FIG. 3; FIG. 5(a) and 5(b) are diagrams showing simulation results of variations in the reference current source of FIG. 2 and a conventional reference current source. FIG. 10 is a circuit diagram of a reference current source according to Example 1.2; 1 is a circuit diagram of a semiconductor integrated circuit provided with a startup circuit studied by the inventors; FIG. FIG. 10 is a circuit diagram of a semiconductor integrated circuit including a startup circuit according to a second embodiment; FIG. 3 is a circuit diagram showing a specific configuration example of a startup circuit; 4 is an operation waveform diagram of the startup circuit; FIG. FIG. 10 is a waveform diagram of total current consumption of the startup circuit according to the second embodiment; FIG. 10 is a waveform diagram of the capacitor voltage _VC1 when the size of the transistor M11 is used as a parameter; 1 is a circuit diagram of a Rail-To-Rail folded cascode operational amplifier; FIG. FIG. 4 is a diagram showing the relationship between the common-mode input voltage and the internal current of the operational amplifier; 15A and 15B are diagrams showing temperature characteristics of the operational amplifier of FIG. 13. FIG. 14 is a diagram showing the relationship between the input offset voltage and the common-mode input voltage of the operational amplifier of FIG. 13; FIG. 10 is a circuit diagram of an operational amplifier according to Embodiment 3; FIG. FIG. 11 is a circuit diagram of a correction circuit according to Example 3.1; 19(a) and 19(b) are diagrams showing the characteristics of the operational amplifier of FIG. 17. FIG. 18 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage of the operational amplifier of FIG. 17; FIG. FIG. 13 is a circuit diagram of an operational amplifier according to Example 3.2; 14 is a diagram showing the relationship between the input offset voltage of the operational amplifier of FIG. 13 and the common-mode input voltage VCM; FIG. 10 is a circuit diagram of an operational amplifier according to Embodiment 3; FIG. 24 is a diagram for explaining the operation of the operational amplifier of FIG. 23; FIG. FIG. 11 is a circuit diagram of an operational amplifier according to Example 4.1; 26 is a circuit diagram showing a specific configuration example of the operational amplifier of FIG. 25; FIG. It is a circuit diagram which shows the structural example of a 1st correction|amendment part. 28A and 28B are circuit diagrams showing configuration examples of the second correction unit. 26 is a diagram for explaining the operation of the operational amplifier of FIG. 25; FIG. 26 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage in the operational amplifier of FIG. 25; FIG. FIG. 13 is a circuit diagram of an operational amplifier according to Modification 4.1; 4 is a circuit diagram of a first correction unit; FIG. FIG. 32 is a diagram for explaining the operation of the operational amplifier of FIG. 31; 32 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage in the operational amplifier of FIG. 31; FIG. FIG. 13 is a circuit diagram of an operational amplifier according to Modification 4.3; FIGS. 36A and 36B are circuit diagrams of the first correction section and the second correction section of FIG. 35. FIG. 4 is a circuit diagram of a switching circuit; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are given the same reference numerals for each embodiment, and duplication of description will be omitted as appropriate. In other words, different members may be given the same reference numerals in different embodiments. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In the present specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected. It also includes the case where it is indirectly connected via another member that does not affect the connection state.

Similarly, "the state in which the member C is provided between the member A and the member B" includes the case where the member A and the member C or the member B and the member C are directly connected, or the state where the member C is electrically connected. It also includes the case where it is indirectly connected via another member that does not affect the connection state.

(Embodiment 1)
FIG. 2 is a circuit diagram of reference current source 100 according to the first embodiment. The reference current source 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a current mirror circuit 110, and a resistor R.

The first transistor M1 and the second transistor M2 are NMOS transistors (FETs), and their control terminals (ie gates) are connected together. Also, the gate and drain of the first transistor M1 are connected.

The current mirror circuit 110 copies the current I _ref flowing in the first path 112 including the second transistor M2 and supplies the same amount of current to the second path 112 including the first transistor M1. Further, the current mirror circuit 110 supplies a current m×I _ref that is a predetermined coefficient times (m times) the current I ref of the first path 112 to the third path 114 .

A third transistor M3 is an NMOS transistor and is provided on the third path 116 . A bias voltage Vb is applied to the gate of the third transistor M3, and its source is connected to one end (source) of the first transistor M1.

The fourth transistor M4 is provided on the third path 116 and on the lower potential side than the third transistor M3. The same bias voltage Vb as that of the third transistor M3 is applied to the gate of the fourth transistor M4.

A resistor R is provided between the source of the fourth transistor M4 and one end (source) of the second transistor M2.

The above is the basic configuration of the reference current source 100 . Next, the operation will be explained.

Ｖ_Ｔ： 熱電圧 （＝ｋＴ／ｑ）
η： サブスレッショルド係数
ｋ： ボルツマン定数
ｑ： 電子電荷
Ｔ： 絶対温度
ρ： 抵抗温度係数 It is assumed that the third transistor M3 and the fourth transistor M4 operate in the subthreshold region. In the sub-thread region, the drain current I _D is expressed by Equation (7).

_VT : Thermal voltage (=kT/q)
η: subthreshold coefficient k: Boltzmann constant q: electron charge T: absolute temperature ρ: temperature coefficient of resistance

A voltage (voltage drop) across the resistor R is obtained. The following equation holds for the gate-to-source voltages of transistors M3 and M4.
V _b −V _gs3 =V _R1
V _b −V _gs4 =V _R2

In this embodiment, the sizes of the transistors M1 and M2 are equal. Therefore, the following equations hold for the transistors M1 and M2.
V _R1 +V _gs1 -V _gs2 =V _R2A
V _gs1 =V _gs2
Therefore, V _R1 =V _R2A

The reference current I _ref is expressed by Equation (8).

By transforming the equation (7), the equation (9) is obtained.

Focus on the third transistor M3. Since m×I _ref flows through the third transistor M3, the gate-source voltage V _gs3 is given by equation (10) by substituting I _D =m×I _ref into equation (9). _K3 is the W/L of the third transistor M3.

Also, pay attention to the fourth transistor M4. Since the total current (m+1)×I _{ref of the current m×I ref} flowing _through the third transistor M3 and the current I _ref flowing through the first transistor M1 flows through the fourth transistor M4, I _D = By substituting (m+1)×I _ref , the gate-source voltage V _gs4 is given by equation (11). _K4 is the W/L of the fourth transistor M4.

Substituting equations (10) and (11) into equation (8), the reference current I _ref is given by equation (12).

Rearranging the equation (12), the reference current I _ref can be expressed by the equation (13).

The temperature characteristic of resistor R is represented by equation (14).
R=R ₀ +ρT (14)
_R0 is the resistance value when T=0.

Substituting equation (14) into equation (13) yields equation (15).

That is, the reference current source 100 of FIG. 2 can generate the reference current I _ref according to the thermal voltage V _T , the subthreshold coefficient, and the resistance. By adjusting the sizes K ₃ and K ₄ of the third transistor M3 and the fourth transistor M4 or the mirror ratio m, the temperature characteristics of the reference current I _ref can be adjusted.

The present invention extends to various apparatus and methods grasped as the block diagram and circuit diagram of FIG. 2 or derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific configuration examples and embodiments will be described not for narrowing the scope of the present invention, but for helping to understand the essence and operation of the invention and clarifying them.

(Example 1.1)
FIG. 3 is a circuit diagram of the reference current source 100A according to Example 1.1. The reference current source 100A according to Example 1.1 includes a fifth transistor M5. The fifth transistor M5 is provided on the third path 116 on the lower potential side than the fourth transistor M4, and one end (source) thereof is connected to the ground line 104. FIG. The total current (m+2)×I _{ref of the current (m+1)×I ref} flowing _through the fourth transistor M4 and the current I _ref flowing through the second transistor M2 flows through the fifth transistor M5.

The voltage _Vgs5 at the control terminal (ie gate) of the fifth transistor M5 is applied to the gates of transistors M3 and M4 as the bias voltage _Vb in FIG.

The current mirror circuit 110 includes a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8, which are PMOS transistors. The gates of the sixth to eighth transistors M6 to M8 are connected in common, and their sources are connected to the power supply line 102. FIG. Also, the gate and drain of the sixth transistor M6 are connected.

In example 1.1, the mirror ratio of the current mirror circuit 110 is m=1 and the current flowing through the third path 116 is equal to the reference current I _ref .

At least one PMOS transistor may be inserted on the third path 116 and on the drain side of the third transistor M3. In FIG. 3, two PMOS transistors M9 and M10 are inserted, and a bias voltage _Vb is applied to their gates.

By inserting transistors M9 and M10 and connecting the drain of transistor M10 to the gate of transistor M5, transistors M3 and M4 can be operated in the subthreshold region.

The above is the configuration of the reference current source 100A according to the embodiment 1.1. Next, the operation will be explained.

In Example 1.1, m=1, so the reference current I _ref is given by equation (16).

That is, according to the reference current source 100A of FIG. 3, the reference current _Iref corresponding to the thermal voltage V _T , the subthreshold coefficient and the resistance R can be generated. The temperature characteristics of the reference current _Iref can be adjusted by adjusting the sizes _K3 and _K4 of the transistors M3 and M4.

FIG. 4 is a diagram showing temperature characteristics of the reference current source 100A of FIG. For comparison, the temperature characteristics of the reference current source 100R of FIG. 1 are also shown. Conventionally, the reference current I _ref monotonically decreases with temperature and fluctuates by 0.8 nA in the temperature range of -50°C to 100°C. In contrast, in this embodiment, the reference current I _ref can be arcuate with respect to temperature. If the peak is set near room temperature (30° C.), the fluctuation width in the temperature range of −50° C. to 100° C. can be suppressed to 0.2 A or less. Further, in the present embodiment, the maximum value of the temperature coefficient is 0.48 pA/deg, which can be suppressed to about 1/10 of the conventional one.

FIG. 5(a) is a diagram showing a simulation result of variations in the reference current source 100A of FIG. FIG. 5B shows simulation results of variations in the conventional reference current source 100R. Regarding the simulation, the threshold voltage V _TH , the mobility μ, and the oxide film thickness are considered.

As can be seen from the comparison between FIGS. 5A and 5B, according to the present embodiment, the variation can be suppressed to about 1/2 of the conventional one.

Furthermore, in the conventional circuit of FIG. 1, in order to reduce the power consumption, it is necessary to reduce the resistance value of the resistor R to several MΩ when the reference current I _ref is to be reduced to the order of nA. In contrast, in the present embodiment, the resistance value required to generate the same amount of current can be 1 MΩ or less. This is because the voltages _V.sub.R2A and _V.sub.R2 across the resistor R are produced by the difference between the current amounts of the transistors M6_2 and M6_3. For example, if a conventional circuit requires a resistor R of 5 MΩ, it can be reduced to 900 kΩ in this embodiment, and the element area can be reduced. Specifically, when 5 MΩ requires an area of 23040 μm ² , 900 kΩ can be shrunk to 4320 μm ² , which is about 1/5.

(Example 1.2)
FIG. 6 is a circuit diagram of a reference current source 100B according to Example 1.2. In embodiment 1.2, the transistor M5 in FIG. 3 is omitted and the source of the fourth transistor M4 is connected to the ground line 104. In FIG. That is, the gate-source voltage _Vgs4 of the fourth transistor M4 corresponds to the bias voltage _Vb .

Embodiment 1 is merely an example, and those skilled in the art will understand that various modifications can be made to the combination of each component and each treatment process, and that such modifications are within the scope of the present invention. be. Such modifications will be described below.

(Modification 1.1)
In the embodiment, the first transistor M1 and the second transistor M2 are composed of NMOS transistors, but they may be composed of bipolar transistors. In this case, if they are equal in size, the base-emitter voltages V _be1 and V _be2 are equal, so that equation (8) holds.

(Modification 1.2)
The configuration of the current mirror circuit 110 is not particularly limited. The current mirror circuit 110 may be composed of bipolar transistors. Also, other current mirror circuits such as a Widler current mirror and a Wilson current mirror may be employed.

(Modification 1.3)
In Examples 1.1 and 1.2, the case of m=1 was explained, but m is not limited to this and can be determined arbitrarily. Using m as a parameter, the reference current I _ref can be adjusted as shown in equation (15). For example, the size of the third transistor M3 and the fourth transistor M4 may be equal (K ₃ =K ₄ ) and the reference current I _ref may be optimized by m only, or based on both the size and m, the reference current I _ref may be optimized.

(Modification 1.4)
In the configuration of the embodiment, circuits in which the N-type and the P-type are replaced with each other and the top and bottom are reversed are also included in the scope of the present invention.

(Embodiment 2)
In the second embodiment, a startup circuit for a reference current source will be described. The startup circuit described in the second embodiment can be combined with the reference current source 100 described in the first embodiment, but may be combined with a reference current source different from the first embodiment.

Generally, a semiconductor integrated circuit has a reference current source that generates a constant reference current that does not depend on the power supply voltage, etc. This reference current is copied and distributed as a bias current to various circuit blocks within the semiconductor integrated circuit. be.

Since the reference current source cannot autonomously start when the power supply voltage is turned on, a starting circuit is required to give a trigger to the reference current source.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit 200R including a startup circuit 100R studied by the inventors. The semiconductor integrated circuit 200R includes a reference current source 210 and a startup circuit 100R that gives a startup trigger to the reference current source 210. FIG.

Reference current source 210 includes transistor M104. Transistor M104 forms a current mirror circuit with transistors M201, M202, . After the completion of startup of the reference current source 210, the reference current _IREF flowing through the transistor M104 is copied and supplied to various circuit blocks of the semiconductor integrated circuit 200R by the transistors M201, M202, .

The startup circuit 100R includes transistors M101 to M107. The startup circuit 100R gives a startup trigger to the reference current source 210 when the voltage _VDD of the power supply line 102 rises, and stops the operation when the startup of the reference current source 210 is completed.

Transistor M101 is a PMOS transistor with a grounded gate. When the power supply voltage _VDD of the power supply line 102 rises, the gate-source voltage of the transistor M101 exceeds the threshold value, the transistor M101 is turned on, and the current _I1 begins to flow.

Transistors M102 and M103 form a current mirror circuit 106 which copies current _I1 and sinks current from transistor M104 by its output current _I2 .

Transistors M105 and M104 form a current mirror circuit that copies current _I2 and produces current _I3 . In addition, transistors M106 and M107 form a current mirror circuit that copies current _I3 and produces current _I4 .

When the relationship I ₄ >I ₁ holds true, all the current flowing through the transistor M101 flows to the transistor M107 side, so the input current of the current mirror circuit 108 becomes zero, the current _I2 also becomes zero, and the starting circuit 100R becomes the reference current. source 210 is no longer affected.

The inventors have studied the activation of the activation circuit 100R of FIG. 7 and have come to recognize the following problems.

After the start-up circuit 100R of FIG. 7 completes the start-up of the reference current source 210, the current _I2 stops flowing, but the currents _I3 and _I4 continue to flow. If the current consumption of the integrated circuit including the startup circuit 100R is on the order of μA, the remaining currents I ₃ and I ₄ can be ignored. However, it may be required to reduce the current consumption of the integrated circuit to sub-μA (eg, 100 to 200 nA), and the currents I ₃ and I ₄ cannot be ignored.

Embodiment 2 describes a start-up circuit that reduces current consumption after completion of start-up.

FIG. 8 is a circuit diagram of a semiconductor integrated circuit 200 including a startup circuit 100 according to the second embodiment. A semiconductor integrated circuit 200 includes a startup circuit 100 and a reference current source 210 .

The startup circuit 100 gives a startup trigger to the reference current source 210 when the power supply voltage _VDD of the power supply line 102 rises, and stops the operation when the startup of the reference current source 210 is completed.

The start-up circuit 100 mainly comprises a first circuit 110, a second circuit 120, a capacitor C1 and several transistors.

The first circuit 110 is provided between the power supply line 102 and the ground line 104, is configured to allow a first current _I1 to flow from the power supply line 102 to the ground line 104 at startup, and further responds to the first current _I1 . A second current _I2 is provided to the reference current source 210 .

Reference current source 210 includes transistor M0. The gate and drain of the transistor M0 are connected. Transistor M0 forms a current mirror circuit with transistors M201, M202, . In normal operation, the reference current _IREF flowing through the transistor M0 flows through the transistors M201, M202, .

At the startup of the semiconductor integrated circuit 200, the second current _I2 flows through the transistor M0 and is copied by the transistors M5 and M9 to flow the third current _I3 and the fourth current _I4 .

The second circuit 120 acts on the first circuit 110 such that the second current _I2 becomes _zero when the third current _I3 corresponding to the second current I2 flows. This action is indicated by the dashed line in FIG.

A first end of capacitor C1 is grounded. A capacitor C1 is connected to be charged by a fourth current _I4 responsive to the second current _I2 . As the capacitor C1 is charged by the fourth current I4, the voltage _VC1 at the second end of the capacitor C1 increases.

The first circuit 110 is configured such that the first current _I1 flowing through the first circuit 110 is interrupted when the voltage V _C1 of the capacitor C1 rises. The second circuit 120 is also configured such that the third current _I3 flowing through the second circuit 120 is interrupted when the voltage _VC1 of the capacitor C1 rises.

The above is the basic configuration of the startup circuit 100 . FIG. 9 is a circuit diagram showing a specific configuration example of the activation circuit 100. As shown in FIG.

The first circuit 110 includes a first transistor M1 to a fourth transistor M4. The gate of the first transistor M1, which is a PMOS transistor, is grounded. The second transistor M2 is an NMOS transistor whose source is grounded and whose gate-drain is connected to the drain of the first transistor M1. The third transistor M3 is an NMOS transistor having a source grounded, a gate connected to the gate of the second transistor M2, and a drain connected to the gate and drain of the transistor M0 of the reference current source 210 .

The second transistor M2 and the third transistor M3 form a first current mirror circuit 112 that copies the first current _I1 flowing through the first transistor M1 to generate a second current _I2 .

The fourth transistor M4 has a source connected to the power supply line 102, a drain connected to the source of the first transistor M1, and a gate to which the voltage _VC1 of the second terminal of the capacitor C1 is applied. The fourth transistor M4 is a first cutoff transistor that is provided on the path of the first current _I1 and turned off according to the capacitor voltage VC1.

The fifth transistor M5 has a source connected to the power supply line 102 and a gate connected to the gate and drain of the transistor M0 of the reference current source 210 .

The ninth transistor M9 has a source connected to the power supply line 102, a gate connected to the gate and drain of the transistor M0 of the reference current source 210, and a drain connected to the second end of the capacitor C1.

The second circuit 120 includes transistors M6, M7, M10 and M11 which are NMOS transistors and a transistor M8 which is a PMOS transistor.

The sixth transistor M6 has a source grounded and a gate-drain connected. The seventh transistor M7 has a source grounded, a gate connected to the gate of the sixth transistor M6, and a drain connected to the drain of the second transistor M2. A sixth transistor M6 and a seventh transistor M7 form a second current mirror circuit 122 that copies the third current _I3 to produce a fifth current _I5 . The second current mirror circuit 122 sinks the fifth current _I5 from the gate of the first current mirror circuit 112 . As a result, the second current _I2 decreases, and when the third transistor M3 is turned off, the second current _I2 becomes zero. The fifth current _I5 corresponds to the dashed line in FIG.

The eighth transistor M8 has a source connected to the drain of the fifth transistor M5, a drain connected to the drain of the sixth transistor M6, and a gate to which the voltage _VC1 of the second terminal of the capacitor C1 is applied. The eighth transistor M8 is a second cutoff transistor which is provided on the path of the third current _I3 and whose gate is turned off in response to the capacitor voltage _VC1 .

The tenth transistor M10 has a source grounded, a drain connected to the gate of the sixth transistor M6, and a gate to which the voltage _VC1 of the second terminal of the capacitor C1 is applied. When the capacitor voltage _VC1 exceeds the threshold of the tenth transistor M10, the tenth transistor M10 turns on, the second current mirror circuit 122 including the transistors M6 and M7 stops, and the fifth current _I5 becomes zero. Become. The tenth transistor M10 is a third cutoff transistor that turns off the second current mirror circuit 122 according to the capacitor voltage _VC1 applied to its gate.

The eleventh transistor M11 has a source grounded, a drain connected to the second terminal of the capacitor C1, and a gate connected to the gate of the sixth transistor M6. That is, the eleventh transistor M11 is part of the second current mirror circuit 122 .

A sixth current _I6 corresponding to the third current _I3 flows through the eleventh transistor M11. A sixth current _I6 discharges the charge on the capacitor C1. That is, the capacitor C1 is charged by the difference I _CHG =I ₄ -I ₆ between the current I ₄ flowing through the ninth transistor M9 and the current I ₆ flowing through the eleventh transistor M11. When the voltage V _C1 on the capacitor C1 exceeds the gate-source threshold V _GS(th) of the tenth transistor M10, the current _I6 becomes zero. Therefore, from the start of charging the capacitor C1 until the capacitor voltage V _C1 reaches the threshold V _GS(th) , the charging current I _CHG is I ₄ -I ₆ , the charging capability is limited, and the capacitor voltage V When _C1 exceeds the threshold V _GS(th) , the charging current I _CHG becomes _I4 and the restriction on the charging capability is lifted.

The twelfth transistor M12 is a PMOS transistor having a drain grounded, a source connected to the second end of the capacitor C1, and a gate connected to the power supply line 102 . The twelfth transistor M12 can prevent the capacitor voltage _VC1 from going high in the initial state due to the leakage current of the transistor M9 at high temperatures.

The configuration of the startup circuit 100 is as described above. Next, the operation will be described with reference to simulation results. FIG. 10 is an operation waveform diagram of the startup circuit 100. FIG. At time t ₀ (100 ms), the power supply voltage V _DD begins to rise. When the power supply voltage V _DD reaches a certain voltage level at time _t1 , the first circuit 110 is activated and the second current _I2 begins to flow.

This second current _I2 is copied by a current mirror circuit including transistors M0 and M5, and a third current _I3 and a fourth current _I4 begin to flow at time _t2 . A third current I ₃ is copied by transistors M 6 and M 7 and a fifth current I ₅ is withdrawn from the gates of transistors M 2 and M 3 of the first current mirror circuit 112 . This reduces the second current _I2 flowing through the reference current source 210 .

A current obtained by subtracting the sixth current _I6 from the fourth current _I4 is supplied as the charging current I _CHG to the capacitor _C1 , and the capacitor voltage V _C1 rises. In the time interval τ, the charging current _ICHG is limited by the sixth current _I6 , so the voltage increases at a slow rate.

At time _t3 , when capacitor voltage V _C1 exceeds the threshold of transistor M10, transistor M10 turns on, transistor M11 turns off, and current _I6 becomes zero. As a result, the limiter of the charging current _ICHG is released, and the rising speed of the capacitor voltage _VC1 becomes faster. Also, by turning on the transistor M10, the gate and drain of the transistor M6 are grounded, so that the currents _I3 , _I5 , and _I6 become zero.

When the capacitor voltage _VC1 reaches the power supply voltage _VDD , it follows the power supply voltage _VDD and increases. Transistors M1 and M8 are then turned off, blocking the paths of currents _I1 and _I3 .

After that, when the power supply voltage V _DD becomes constant, the charging current I _CHG becomes zero. Eventually, the second current _I2 becomes zero and the currents of all paths become zero.

FIG. 11 is a waveform diagram of total current consumption of the startup circuit 100 according to the second embodiment. For comparison, the consumption current of the startup circuit 100R of FIG. 7 is also shown. In the comparative technique, a current of 150 nA continues to flow steadily even after the circuit has started up. In contrast, in the second embodiment, the circuit current flows only during the start-up period, and the current after completion of start-up (after 110 ns) is substantially zero.

Further, in the starting circuit 100 according to the second embodiment, the charging speed of the capacitor C1 can be limited by the current _I6 . Current _I6 can be set according to the size of transistor M11. FIG. 12 is a waveform diagram of the capacitor voltage _VC1 when the size of the transistor M11 is used as a parameter. x1.0 corresponds to M6:M11=1:2, x0.5 corresponds to M6:M11=1:1, and x0.25 corresponds to M6:M11=1:0.5. As the size of transistor M11 increases and the current _I6 increases, the delay time τ increases.

(Appendix 2)
The following technical idea is disclosed in the second embodiment.
(Item 2.1)
A starting circuit for a reference current source,
A first circuit provided between a power supply line and a ground line, wherein a first current flows from the power supply line to the ground line at startup and a second current corresponding to the first current is supplied to the reference current source. and,
a second circuit that acts on the first circuit such that the second current becomes zero when a third current corresponding to the second current flows;
a capacitor charged by a fourth current corresponding to the second current;
with
The first circuit is configured to interrupt the first current flowing through the first circuit when the voltage of the capacitor increases.
(Item 2.2)
The start-up circuit according to item 2.1, wherein the first circuit includes a first cut-off transistor provided on the path of the first current and having a gate to which the voltage of the capacitor is applied.
(Item 2.3)
Activation according to item 2.1 or 2.2, characterized in that the second circuit is arranged such that when the voltage of the capacitor increases, the third current flowing through the second circuit is interrupted. circuit.
(Item 2.4)
The start-up circuit according to item 2.3, wherein the second circuit includes a second cut-off transistor provided on the path of the third current and having a gate to which the voltage of the capacitor is applied.
(Item 2.5)
The first circuit is
a first transistor provided between a power supply line and a ground line and having a biased gate;
a first current mirror circuit that copies the first current flowing through the first transistor to generate the second current;
A start-up circuit according to any one of clauses 2.1 to 2.4, characterized in that it comprises:
(Item 2.6)
Item 2, wherein said second circuit includes a second current mirror circuit that copies said third current to produce a fifth current, said fifth current being sunk from said first current mirror circuit. .5 start-up circuit;
(Item 2.7)
Start-up circuit according to item 2.6, characterized in that it further comprises a third blocking transistor having a gate to which the voltage of the capacitor is applied and which is connected to the gate of the second current mirror circuit.
(Item 2.8)
Start-up circuit according to item 2.6 or 2.7, wherein the second current mirror circuit limits the charging of the capacitor by a sixth current proportional to the third current.
(Item 2.9)
A starting circuit for a reference current source,
a capacitor having a first end grounded;
a first transistor having a grounded gate;
a second transistor having a source grounded and a gate-drain connected to the drain of the first transistor;
a third transistor having a source grounded, a gate connected to the gate of the second transistor, and a drain connected to the gate and drain of the reference current source transistor;
a fourth transistor having a source connected to the power supply line, a drain connected to the source of the first transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a fifth transistor having a source connected to the power supply line and having a gate connected to the gate and the drain of the transistor of the reference current source;
a sixth transistor whose source is grounded and whose gate and drain are connected;
a seventh transistor having a source grounded, a gate connected to the gate of the sixth transistor, and a drain connected to the drain of the second transistor;
an eighth transistor having a source connected to the drain of the fifth transistor, a drain connected to the drain of the sixth transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a ninth transistor having a source connected to the power supply line, a gate connected to the gate and the drain of the transistor of the reference current source, and a drain connected to the second end of the capacitor;
A startup circuit comprising:
(Item 2.10)
10. The method of item 2.9, further comprising a tenth transistor having a source grounded, a drain connected to the gate of the sixth transistor, and a gate to which the voltage of the second end of the capacitor is applied. startup circuit.
(Item 2.11)
2.9 or 2.10, further comprising an eleventh transistor having a source grounded, a drain connected to the second end of the capacitor, and a gate connected to the gate of the sixth transistor. Startup circuit as described.
(Item 2.12)
2.10 according to any one of items 2.9 to 2.10, further comprising a twelfth transistor having a drain grounded, a source connected to the second end of the capacitor, and a gate connected to the power supply line. Startup circuit as described.
(Item 2.13)
a reference current source;
a startup circuit according to any one of items 2.1 to 2.12;
A semiconductor integrated circuit comprising:

(Embodiment 3)
Embodiment 3 describes an operational amplifier.

2. Description of the Related Art In recent years, due to the demand for lower power consumption of electronic devices, the power supply voltage supplied to operational amplifiers has been steadily decreasing. In low voltage applications, Rail-To-Rail operation is required to extend the input voltage range of the operational amplifier.

FIG. 13 is a circuit diagram of a Rail-To-Rail folded cascode operational amplifier 1R. The operational amplifier 1R amplifies the difference between the two voltages input to the differential input terminals INP and INN and outputs it from the output terminal OUT. The operational amplifier 1R mainly includes a first differential input pair 10, a second differential input pair 12, a first tail current source 14, a second tail current source 16, an output stage 20, and a switching circuit 30.

The first input differential pair 10 includes a first transistor M1 and a second transistor M2, which are PMOS transistors of a first polarity. Tail current source 14 includes appropriately biased PMOS transistors to provide tail current Itp to first differential input pair 10 .

The second input differential pair 12 includes a third transistor M3 and a fourth transistor M4, which are NMOS transistors of the second polarity. Tail current source 16 provides tail current Itn to second input differential pair 12 .

The output stage 20 converts the differential current flowing through the first differential input pair 10 and the differential current flowing through the second differential input pair 12 into an output voltage Vout. Output stage 20 includes lower circuit 21 , upper circuit 22 and bias circuit 23 .

The lower circuit 21 includes a constant current circuit 24 (M5, M6) that folds back the differential current of the first input differential pair 10, and a gate ground circuit 25 that is provided on the route of the folded differential current. The gate-grounded circuit 25 is a pair of gate-biased NMOS transistors M7 and M8. The upper circuit 22 includes a constant current circuit 26 (M9, M10) that folds back the differential current of the second input differential pair 12, and a gate ground circuit 27 provided on the route of the folded differential current. The gate common circuit 27 is a pair of PMOS transistors M11 and M12 with their gates biased.

The switching circuit 30 switches between the first differential input pair 10 and the second differential input pair 12 according to the common-mode component (common-mode input voltage VCM) of the input voltages Vp and Vn. The switching circuit 30 includes a transistor M21, which is a PMOS transistor. The source of the transistor M21 is connected in common with the sources of the first transistor M1 and the second transistor M2, and the output stage 20 supplies a bias voltage Vb to its gate.

The larger one of Vgs1 and Vgs2 is represented as Vgs. When the common-mode input voltage VCM is sufficiently lower than the bias voltage Vb (Vgs21<Vgs), the tail current Itp generated by the tail current source 14 all flows into the first input differential pair 10 (2×I1=Itp ), no current flows through the transistor M21 (I1_2=0).

When the common-mode input voltage VCM increases to about the bias voltage Vb, in other words, when Vgs21≈Vgs, the current I1_2 starts flowing through the transistor M21. Transistors M22 and M23 of switching circuit 30 form a current mirror with transistors M24 and M25 of tail current source 16, and current I1_2 is copied and supplied to second input differential pair 12 as tail current 2*I2. be. As the common-mode input voltage VCM approaches the power supply voltage VDD, in other words, as Vgs becomes smaller than Vgs21, the tail current 2×I1 supplied to the first input differential pair 10 decreases, and the second input differential pair The tail current 2*I2 supplied to 12 is increasing. Thereby, the first differential input pair 10 and the second differential input pair 12 are switched according to the common-mode input voltage VCM.

The mismatch between transistors M1 and M2, the mismatch between transistors M3 and M4, the mismatch between transistors M5 and M6, and the mismatch between transistors M9 and M10 contribute to the input offset voltage of operational amplifier 1R. In order to reduce the input offset voltage, a technique such as trimming the resistance values of the resistors R1 and R2 of the lower circuit 21 is adopted.

As a result of studying the operational amplifier 1R of FIG. 13, the inventors have come to recognize the following problems. The current (hereinafter referred to as cascode current) Io flowing through the gate ground circuits 25 and 27 of the output stage 20 will be focused on. In the following discussion, for the sake of simplification for easy understanding, only the in-phase component is focused and the differential component is assumed to be zero. FIG. 14 is a diagram showing the relationship between the common-mode input voltage and the internal current of the operational amplifier 1R.

Operation of the operational amplifier 1R is divided into a low voltage region where the operation of the first differential input pair 10 dominates, a high voltage region where the operation of the second differential input pair 12 dominates, and a transition region where both of them operate. can be considered separately. In the figure, the dashed line indicates the current in the low voltage region, and the solid line indicates the current in the high voltage region.

(Low voltage area)
The second constant current circuit 26 is biased by the bias circuit 23 so that the constant current I_p flows. The current of the second tail current source 16 is zero, and the currents of both the third transistor M3 and the fourth transistor M4 are zero. The cascode current Io is therefore equal to the constant current I_p.

(high voltage area)
In the high voltage region, second tail current source 16 provides tail current 2*I2 to second input differential pair 12 . A current I2 flows through each of the third transistor M3 and the fourth transistor M4. Therefore, the cascode current Io decreases from I_p by I2.

A decrease in the cascode current is not so problematic for an operational amplifier with a large current consumption, but it becomes a serious problem for an operational amplifier whose total current consumption is on the order of several hundred nA. 15(a) shows the temperature dependence of the cascode current, and FIG. 15(b) shows the temperature dependence of the leakage current of the first input differential pair 10. FIG.

As the temperature increases, the effect of transistor leakage current increases. As shown in FIG. 15(b), in the high voltage region, the current flowing through the second input differential pair 12 increases as the temperature rises. As a result, in the high voltage region, the higher the temperature, the smaller the cascode current Io, and at a high temperature (125° C.), the cascode current Io drops to near zero, and the operational amplifier 1R cannot operate normally.

FIG. 16 is a diagram showing the relationship between the input offset voltage and the common-mode input voltage of the operational amplifier 1R. From -50°C to 105°C, the input offset voltage remains near zero over the 0 to 5V common mode input range, but at 125°C the input offset voltage increases, especially between 4.8V and 5V. Range is inoperable.

Embodiment 3 describes an operational amplifier capable of normal operation over a wide voltage range.

FIG. 17 is a circuit diagram of operational amplifier 1 according to the third embodiment. The operational amplifier 1 is of the folded cascode type and comprises a first differential input pair 10, a second differential input pair 12, a first tail current source 14, a second tail current source 16, an output stage 20, and a correction circuit 90. .

A first input voltage Vp is input to the non-inverting input terminal INP, and a second input voltage Vn is input to the inverting input terminal INN. An upper power supply voltage is input to the upper power supply terminal VDD, and a lower power supply voltage (eg, ground voltage) is supplied to the lower power supply terminal (ground terminal) VSS. The operational amplifier 1 amplifies the difference between the first input voltage Vp and the second input voltage Vn and outputs the output voltage Vout from the output terminal OUT.

The first input differential pair 10 includes a first transistor M1 and a second transistor M2 which are PMOS transistors. The gate of the first transistor M1 is connected to the inverting input terminal INN, and the gate of the second transistor M2 is connected to the non-inverting input terminal INP.

The second input differential pair 12 includes a third transistor M3 and a fourth transistor M4 which are NMOS transistors. A gate of the third transistor M3 is connected to the non-inverting input terminal INP, and a gate of the fourth transistor M4 is connected to the inverting input terminal INN.

A first tail current source 14 supplies a first tail current Itp to the first input differential pair 10 . A second tail current source 16 supplies a second tail current Itn to the second input differential pair 12 .

Output stage 20 includes an upper circuit 22 and a lower circuit 21 stacked between power supply line VDD and ground line VSS. The lower circuit 21 is connected to the first differential input pair 10 and the upper circuit 22 is connected to the second differential input pair 12 . Output terminal OUT is tapped from a node internal to output stage 20 . In this example, the connection node between the upper circuit 22 and the lower circuit 21 is the OUT terminal.

Output stage 20 includes a lower circuit 21 and an upper circuit 22 . Lower circuit 21 includes a first constant current circuit 24 and a first gate ground circuit 25 . The first constant current circuit 24 includes transistors M5 and M6 and folds back the differential current of the first input differential pair 10. FIG. The first gate-grounded circuit 25 is provided on the path of the folded differential current (referred to as the first folded differential current). The first gate-grounded circuit 25 includes a pair of transistors M7 and M8 to the gates of which a bias voltage Vbn generated by a bias circuit (not shown) is applied. The lower circuit 21 is a cascode current mirror having an input on the M5 side and an output on the M6 side.

The upper circuit 22 acts as an active load for the first folded differential current and converts the first folded differential current to an output voltage Vout. Upper circuit 22 includes a second constant current circuit 26 and a second gate ground circuit 27 . A second constant current circuit 26 includes transistors M 9 and M 10 and folds back the differential current of the second input differential pair 12 . The second gate-grounded circuit 27 includes transistors M11 and M12 and is provided on the path of the folded differential current. The lower circuit 21 also acts as an active load for the second folded differential current and converts the second folded differential current to the output voltage Vout. A bias voltage Vbp generated by a bias circuit (not shown) is applied to the gates of the transistors M11, M12 and M14.

The transistors M9 to M12 of the upper circuit 22 form a cascode current mirror together with the transistors M13 and M14 of the bias circuit 23. FIG. Current I_p of transistors M9 and M10 is proportional to current Ip_0 flowing through transistor M13.

The switching circuit 30 dynamically changes the first tail current 2×I1 and the second tail current 2×I2 according to the first input voltage Vp and the second input voltage Vn. Specifically, the second tail current 2×I2 is substantially zero in the low voltage region, and the first tail current 2×I1 is substantially zero in the high voltage region. In the transition region, the switching circuit 30 continuously changes the first tail current 2×I1 and the second tail current 2×I2 according to the common-mode input voltage VCM to seamlessly connect the high voltage range and the low voltage region. It's okay.

A first tail current source 14 generates a first tail current Itp. The switching circuit 30 sinks a current amount I1_2 corresponding to the common-mode input voltage VCM of the first input voltage Vp and the second input voltage Vn. Therefore, the amount of tail current 2×I1 supplied to the first input differential pair 10 is Itp-I1_2.

The sink current I1_2 may be substantially zero in the low voltage range and equal to the tail current amount Itp in the high voltage range. Also, in the transition region, the sink current I1_2 may increase as the common-mode input voltage VCM increases.

The second tail current source 16 is connected to the switching circuit 30 and generates the second tail current 2×I2 in conjunction with the state of the switching circuit 30, in other words, the sink current I1_2. The second tail current 2*I2 is substantially zero in the low voltage range and a predetermined amount in the high voltage range. Also, in the transition region, the second tail current 2×I2 may increase as the common-mode input voltage VCM increases. The switching circuit 30 includes transistors M21 to M23 as in FIG.

The correction circuit 90 corrects the current I_p flowing through the second constant current circuit 26 according to the first input voltage Vp and the second input voltage Vn. In the present embodiment, correction circuit 90 corrects current I_p based on common-mode input voltage VCM of first input voltage Vp and second input voltage Vn. More specifically, in the high voltage range in which the second input differential pair 12 operates, the current I_p is increased more than in the low voltage range in which the first input differential pair 10 operates.

The correction circuit 90 is configured to change the bias current Ip_0 according to the first input voltage Vp and the second input voltage Vn. For example, bias current Ip_0 can be a combined current of predetermined reference current Iref and auxiliary current Iaux. The correction circuit 90 generates an auxiliary current Iaux according to the common-mode input voltage VCM of the first input voltage Vp and the second input voltage Vn.

The above is the basic configuration of the operational amplifier 1 . The present invention extends to various devices and methods grasped as the block diagram and circuit diagram of FIG. 17 or derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific configuration examples and embodiments will be described not for narrowing the scope of the present invention, but for helping to understand the essence and operation of the invention and clarifying them.

(Example 3.1)
FIG. 18 is a circuit diagram of the correction circuit 90 according to Example 3.1. The correction circuit 90 includes a constant current source 92 and transistors M201-M206. A constant current source 92 generates a constant current 2I1. The constant current source 92 may be constructed using the technique of the reference current source described in the first or second embodiment.

Sources of the first to third detection transistors M201 to M203 are commonly connected to the constant current source 92 . A first input voltage Vp is input to the gate of the first detection transistor M201, a second input voltage Vn is input to the gate of the second detection transistor M202, and a bias voltage Vb is applied to the gate of the third detection transistor M203. It is A transistor M204 is connected as a load to the drains of the transistors M201 and M202. The current flowing through the third detection transistor M203 is copied by current mirrors M205 and M206 and output as an auxiliary current Iaux. The operation of this correction circuit 90 is similar to that of the switching circuit 30. A current corresponding to the common-mode input voltage VCM flows through the transistor M203 and is copied to become the auxiliary current Iaux.

Next, the operation of the operational amplifier 1 according to Example 3.1 will be described. FIG. 19(a) is a diagram showing the relationship between the common-mode input voltage and the internal current of the operational amplifier 1. FIG. In the high voltage region, the current I_p flowing through the second constant current circuit 26 increases by the auxiliary current Iaux. Since the increase in the signal Lou current corresponding to the auxiliary current Iaux cancels out the current I2 of the second input differential pair 12, the cascode current Io is constant over the entire voltage range.

FIG. 19(b) is a diagram showing the relationship between the common-mode input voltage and the cascode current. It can be seen that the cascode current Io is maintained within a normal range over a wide temperature range in the common-mode input range of 0 to 5V.

FIG. 20 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage. According to Example 3.1, the input offset voltage is kept substantially constant in the common mode input range of 0 to 5V.

Thus, the operational amplifier 1 according to Example 3.1 can operate normally in a wide voltage range.

(Example 3.2)
FIG. 21 is a circuit diagram of an operational amplifier 1D according to Example 3.2. In this embodiment, the bias current I_p0 changes in conjunction with the state of the switching circuit 30. FIG.

The correction circuit 90 includes a transistor M91, and the current flowing through the transistor M91 is the auxiliary current Iaux. The gate of the transistor M91 is connected to the gate of the transistor M23 of the switching circuit 30, so the auxiliary current Iaux is proportional to the current I1_2 of the transistor M21 and thus varies according to the common mode input voltage VCM. In FIG. 21, the constant current source 92 is composed of a cascode current mirror.

19 and 20 can be obtained in the operational amplifier 1D of FIG. 21 as well, and normal operation is possible in a wide voltage range. Since the operational amplifier 1D of FIG. 21 has a very small number of additional transistor elements, it is possible to improve the characteristics of the operational amplifier 1D while suppressing increases in circuit area and power consumption.

(Modification 3.1)
In the third embodiment, the current I_p generated by the second constant current circuit 26 is changed by changing the bias current Ip_0 flowing through the bias circuit 23, but the present invention is not limited to this. For example, correction circuit 90 may be configured to source current Iaux to a connection node between transistors M9 and M11 and a connection node between transistors M10 and M12. However, in this case, there is a risk that an additional input offset voltage will be introduced if there is variation in the current Iaux of the two sources. The method of changing the bias current Ip_0 described in the third embodiment has the advantage that no additional input offset voltage is generated.

(Appendix 3)
The following technical idea is disclosed in the third embodiment.
(Item 3.1)
an inverting input terminal that receives a first input voltage and a non-inverting input terminal that receives a second input voltage;
a first polarity first input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a second polarity second input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a first tail current source that supplies a first tail current to the first input differential pair;
a second tail current source that supplies a second tail current to the second input differential pair;
An output stage that converts a differential current of the first differential input pair and a differential current of the second differential input pair into an output voltage, and a first differential current that folds back the differential current of the first differential input pair. a constant current circuit, a first gate-grounded circuit provided in a path of a first folded differential current folded back by the first constant current circuit, and a second constant current for folding back the differential current of the second input differential pair. an output stage including a circuit and a second gate-grounded circuit provided in a path of a second folded differential current folded by the second constant current circuit;
a correction circuit that corrects current flowing through at least one of the first constant current circuit and the second constant current circuit according to the first input voltage and the second input voltage;
An operational amplifier comprising:
(Item 3.2)
one of the first constant current circuit and the second constant current circuit is a constant current source that generates a current proportional to a bias current;
3. The operational amplifier according to item 3.1, wherein the correction circuit changes the bias current according to the first input voltage and the second input voltage.
(Item 3.3)
The operational amplifier according to Item 3.2, wherein the bias current is a combined current of a predetermined reference current and an auxiliary current corresponding to the first input voltage and the second input voltage.
(Item 3.4)
Item 3.2 or 3.3, further comprising a switching circuit that dynamically changes the first tail current and the second tail current in response to the first input voltage and the second input voltage. The operational amplifier according to .
(Item 3.5)
5. The operational amplifier of item 3.4, wherein the bias current is linked to the state of the switching circuit.
(Item 3.6)
The correction circuit is
a constant current source that generates a constant current;
a first detection transistor having a source connected to the constant current source and having a gate receiving the first input voltage;
a second detection transistor having a source connected to the constant current source and having a gate receiving the second input voltage;
a third detection transistor having a source connected to the constant current source and a gate biased;
and wherein said auxiliary current is responsive to the current flowing through said third sensing transistor.

(Embodiment 4)
In the third embodiment, as in the fourth embodiment, an operational amplifier will be described. Refer to FIG. 13 again. As a result of studying the operational amplifier 1R of FIG. 13, the inventors have come to recognize the following problems.

FIG. 22 is a diagram showing the relationship between the input offset voltage of the operational amplifier 1R of FIG. 13 and the common-mode input voltage VCM. Characteristic (i) shows the input offset voltage before correction. Characteristics (ii) and (iii) show the input offset voltage after trimming for offset correction. As shown in characteristic (ii), when trimming is performed to reduce the input offset voltage in the operating region of the first differential input pair 10, the input offset voltage increases in the operating region of the second differential input pair 12. . As shown in characteristic (iii), when trimming is performed to reduce the input offset voltage in the operating region of the second differential input pair 12, the input offset voltage in the operating region of the first differential input pair 10 increases. .

Embodiment 4 describes an operational amplifier capable of correcting an input offset voltage over a wide voltage range.

FIG. 23 is a circuit diagram of operational amplifier 1 according to the third embodiment. The operational amplifier 1 comprises a first differential input pair 10 , a second differential input pair 12 , a first tail current source 14 , a second tail current source 16 , an output stage 20 and a correction circuit 40 .

A first input voltage Vp is input to the non-inverting input terminal INP, and a second input voltage Vn is input to the inverting input terminal INN. An upper power supply voltage is input to the upper power supply terminal VDD, and a lower power supply voltage (eg, ground voltage) is supplied to the lower power supply terminal (ground terminal) VSS. The operational amplifier 1 amplifies the difference between the first input voltage Vp and the second input voltage Vn and outputs the output voltage Vout from the output terminal OUT.

The first input differential pair 10 includes a first transistor M1 and a second transistor M2 which are PMOS transistors. The gate of the first transistor M1 is connected to the inverting input terminal INN, and the gate of the second transistor M2 is connected to the non-inverting input terminal INP.

The second input differential pair 12 includes a third transistor M3 and a fourth transistor M4 which are NMOS transistors. A gate of the third transistor M3 is connected to the non-inverting input terminal INP, and a gate of the fourth transistor M4 is connected to the inverting input terminal INN.

A first tail current source 14 supplies a first tail current Itp to the first input differential pair 10 . A second tail current source 16 supplies a second tail current Itn to the second input differential pair 12 .

Output stage 20 includes an upper circuit 22 and a lower circuit 21 stacked between power supply line VDD and ground line VSS. The lower circuit 21 is connected to the first differential input pair 10 and the upper circuit 22 is connected to the second differential input pair 12 . Output terminal OUT is tapped from a node internal to output stage 20 . In this example, the connection node between the upper circuit 22 and the lower circuit 24 is the OUT terminal.

The correction circuit 40 dynamically changes the state of the output stage 20 in response to the first input voltage Vp and the second input voltage Vn. For example, correction circuit 40 changes the state of output stage 20 in response to common-mode input voltage VCM of first input voltage Vp and second input voltage Vn.

The correction circuit 40 adjusts the state of the lower circuit 21 and the state of the upper circuit 22 according to the first input voltage Vp and the second input voltage Vn. For example, the correction circuit 40 is configured so that the input offset voltage is canceled in the input voltage range (low voltage region) in which the operation of the first differential input pair 10 is dominant. (transistors M5 and M6, which will be described later). In the input voltage range (high voltage region) in which the operation of the second input differential pair 12 is dominant, the correction circuit 40 adjusts the pair of transistors included in the upper circuit 22 ( A mismatch is introduced into transistors M9 and M10, which will be described later.

In the input voltage range (referred to as the transition region) sandwiched between the low voltage region and the high voltage region where both the first differential input pair 10 and the second differential input pair 12 operate, the mismatch introduced into the lower circuit 21 is , the mismatch introduced into the upper circuit 22 may be varied continuously and complementary.

Correction circuit 40 introduces a mismatch in the transistor pair (M5, M6) of lower circuit 21 in the low voltage region. Although the method of introducing the mismatch is not particularly limited, for example, the first correction signal Sc1 may be supplied to one of the transistor pair M5 and M6. Which of the transistor pairs M5 and M6 should be supplied with the first correction signal Sc1 is selected according to the polarity of the input offset voltage. The first correction signal Sc1 varies between zero and a maximum amount MAX1. The maximum amount MAX1 is preferably optimized (trimmed) for each individual operational amplifier 1 so as to cancel the input offset voltage in the low voltage region.

Correction circuit 40 introduces a mismatch in the transistor pair (M9, M10) of upper circuit 22 in the high voltage region. For example, the correction circuit 40 may supply the second correction signal Sc2 to one of the transistor pair M9 and M10. Which of the transistor pairs M9 and M10 should be supplied with the second correction signal Sc2 is selected according to the polarity of the input offset voltage. The second correction signal Sc2 varies between zero and a maximum amount MAX2. The maximum amount MAX2 should be optimized (trimmed) for each individual operational amplifier 1 so as to cancel the input offset voltage in the high voltage region.

FIG. 24 is a diagram for explaining the operation of operational amplifier 1 of FIG. The horizontal axis indicates the common-mode input voltage VCM, and the vertical axis indicates the amount of mismatch (correction amount) introduced into each of the lower circuit 21 and the upper circuit 22 . In the low voltage region L where the first input differential pair 10 is dominant, the first correction signal Sc1 has the maximum amount MAX1 and the second correction signal Sc2 has the minimum value (for example, zero). Conversely, in the high voltage range H where the second input differential pair 12 dominates, the second correction signal Sc2 has the maximum amount MAX2 and the first correction signal Sc1 has the minimum value (eg, zero). In the transition region M, the low voltage region L and the high voltage region H can be seamlessly connected by continuously changing the first correction signal Sc1 and the second correction signal Sc2 according to the common-mode input voltage VCM. .

The above is the basic configuration of the operational amplifier 1 . The present invention extends to various devices and methods grasped as the block diagram and circuit diagram of FIG. 23 or derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific configuration examples and embodiments will be described not for narrowing the scope of the present invention, but for helping to understand the essence and operation of the invention and clarifying them.

(Example 4.1)
FIG. 25 is a circuit diagram of an operational amplifier 1A according to Example 4.1. The operational amplifier 1A has a switching circuit 30 . The switching circuit 30 dynamically changes the first tail current Itp and the second tail current Itn according to the first input voltage Vp and the second input voltage Vn. Specifically, the second tail current Itn is substantially zero in the low voltage region, and the first tail current Itp is substantially zero in the high voltage region. The switching circuit 30 may continuously change the first tail current Itp and the second tail current Itn according to the common-mode input voltage VCM in the transition region to seamlessly connect the high voltage range and the low voltage region.

A first tail current source 14 generates a first tail current Itp. The switching circuit 30 sinks a current amount I1_2 corresponding to the common-mode input voltage VCM of the first input voltage Vp and the second input voltage Vn. Therefore, the amount of tail current supplied to the first input differential pair 10 is Itp-I1_2.

The sink current I1_2 may be substantially zero in the low voltage range and equal to the tail current amount Itp in the high voltage range. Also, in the transition region, the sink current I1_2 may increase as the common-mode input voltage VCM increases.

The second tail current source 16 is connected to the switching circuit 30 and generates the second tail current Itn in conjunction with the state of the switching circuit 30, in other words, the sink current I1_2. The second tail current Itn is substantially zero in the low voltage range and has a predetermined amount in the high voltage range. Also, in the transition region, the second tail current Itn may increase as the common-mode input voltage VCM increases.

The correction circuit 40 includes a first correction section 42 and a second correction section 44 . The first correction unit 42 introduces a mismatch into the transistor pair (M5, M6) of the lower circuit 21. FIG. The first correction section 42 may receive the input voltages Vp and Vn and generate the first correction signal Sc1 based on their common-mode input voltage VCM.

The second corrector 44 introduces a mismatch in the transistor pair M9, M10 of the upper circuit 22. FIG. The second correction section 44 is connected to the switching circuit 30 and generates a second correction signal Sc2 according to the state of the switching circuit 30. FIG. The state of switching circuit 30 may be, for example, the amount of sink current I1_2 or the voltage of an internal node of switching circuit 30 .

FIG. 26 is a circuit diagram showing a specific configuration example of the operational amplifier 1A of FIG. The switching circuit 30 includes transistors M21, M22 and M23. Transistor M21 is a P-channel MOSFET whose source is connected to first tail current source 14 and whose gate is supplied with bias voltage Vb generated by output stage 20 . The sink current I1_2 flowing through the transistor M21 changes according to the common-mode input voltage VCM.

The second tail current source 16 includes transistors M24 and M25. Transistors M24 and M25 form a current mirror with transistors M22 and M23, and sink current I1_2 is copied and folded back and supplied to second input differential pair 12 as second tail current Itn.

The operational amplifier 1A in FIG. 26 is a folded cascode operational amplifier. Lower circuit 21 includes a first constant current circuit 24 and a first gate ground circuit 25 . The first constant current circuit 24 folds back the differential current of the first input differential pair 10 . The first gate-grounded circuit 25 is provided on the path of the folded differential current (referred to as the first folded differential current). The upper circuit 22 acts as an active load for the first folded differential current and converts the first folded differential current to an output voltage Vout.

Upper circuit 22 includes a second constant current circuit 26 and a second gate ground circuit 27 . A second constant current circuit 26 folds back the differential current of the second input differential pair 12 . The second gate-grounded circuit 27 is provided on the path of the folded differential current. The lower circuit 21 acts as an active load for the second folded differential current and converts the second folded differential current to the output voltage Vout.

The transistors M9 and M10 of the second constant current circuit 26 are biased by the bias circuit 23 and function as a constant current source. The transistors M5 and M6 of the first constant current circuit 24 are a current mirror having an input on the transistor M5 side and an output on the M6 side, and similarly function as a constant current source.

In FIG. 26, the first correction signal Sc1 and the second correction signal Sc2 are current signals. The first constant current circuit 24 includes a transistor pair M5, M6 and source resistors R1, R2 connected to their sources. The first correction unit 42 introduces a mismatch to the transistor pair M5, M6 by sourcing correction currents I_R1, I_R2 to one of the source resistors R1, R2. A resistor pair Ra1, Ra2 is inserted between the transistor pair M5, M6 and the resistor pair R1, R2. The correction amount of the input offset voltage can be adjusted by the three parameters of the resistance pair Ra1, Ra2, the amount of current signal, and the resistance pair R1, R2.

Similarly, the upper circuit 22 comprises a transistor pair M9, M10 and source resistors R3, R4 connected to their sources. The second corrector 44 introduces a mismatch to the transistor pair M9 and M10 by sinking the corrective currents I_R3 and I_R4 from one of the source resistors R3 and R4. A resistor pair Ra3, Ra4 is inserted between the transistor pair M9, M10 and the resistor pair R3, R4. The correction amount of the input offset voltage can be adjusted by the three parameters of the resistance pair Ra3, Ra4, the amount of current signal, and the resistance pair R3, R4.

FIG. 27 is a circuit diagram showing a configuration example of the first correction section 42. As shown in FIG. The first correction unit 42 mainly includes a first current source 50, a first detection transistor M31, a second detection transistor M32, a third detection transistor M33, a first switch SW1, and a second switch SW2. A first current source 50 generates a first current I1. The first current source 50 includes a trimmable current source 52 that generates a constant current Itrim1 and a current mirror circuit 54 that copies and folds the constant current Itrim1 to output a first current I1.

The current amount of the constant current Itrim1 generated by the current source 52 is determined in the inspection process of the operational amplifier 1A. Specifically, with VCM=Vp=Vn, the operational amplifier 1A is operated in the low voltage region, the input offset voltage at that time is measured, and the constant current Itrim1 is determined so that the input offset voltage approaches zero. . The constant current Itrim1 corresponds to the maximum amount MAX1 described above.

Sources of the first detection transistor M31 to the third detection transistor M33 are connected in common. Also, the drains of the first detection transistor M31 and the second detection transistor M32 are connected in common. A first input voltage Vp is input to the gate of the first detection transistor M31, and a second input voltage Vn is input to the gate of the second detection transistor M32. A proper bias voltage Vb is applied to the gate of the third detection transistor M33. As this bias voltage Vb, the bias voltage Vb generated by the upper circuit 22 of FIG. 26 can be used. A transistor M34 (or other load) is provided between the drain of the third detection transistor M33 and the ground terminal VSS.

The first switch SW1 is turned on when the control signal CNT1 is high, and the second switch SW2 is turned on when the control signal CNT2 is high. Let IR be the current flowing through the first detection transistor M31 and the second detection transistor M32. The current IR is supplied to the resistor R1 of the lower circuit 21 when the first switch SW1 is on and the second switch SW2 is off. Conversely, when the first switch SW1 is off and the second switch SW2 is on, the current IR is supplied to the resistor R2 of the lower circuit 21. FIG.

Vgs is the larger one of Vgs31 and Vgs32. When the common-mode input voltage VCM is sufficiently lower than the bias voltage Vb (Vgs33<Vgs), all of the first current I1 flows to the transistors M31 and M32, increasing the current IR. When the common-mode input voltage VCM increases to about the bias voltage Vb, in other words, when Vgs33≈Vgs, current begins to flow through the transistor M33 and current IR begins to decrease. When the common-mode input voltage VCM becomes higher than the bias voltage Vb, in other words, when Vgs33>Vgs, the current IR further decreases to zero.

According to the first correction unit 42 of FIG. 27, the first correction current Ic1 whose maximum amount is defined by the constant current Itrim1 and whose current amount dynamically changes according to the common-mode input voltage VCM can be generated.

28A and 28B are circuit diagrams showing configuration examples of the second correction unit 44. FIG. Referring to FIG. 28(a), the second correction section 44 includes a second current source 56, a third switch SW3, and a fourth switch SW4. The third switch SW3 and the fourth switch SW4 are complementarily turned on according to the control signals CNT1 and CNT2. The second current source 56 has a maximum amount that can be set according to trimming, and is configured to generate a correction current IR2 that varies between zero and a maximum amount according to the state of the switching circuit 30 .

See FIG. 28(b). The transistors M41 and M42 are connected to the transistors M22 and M23 of the switching circuit 30 to form a current mirror circuit. The current I2 flowing through the transistor M41 corresponds to the sink current I1_2 flowing through the switching circuit 30, and increases as the common-mode input voltage VCM rises.

Current mirror circuit 58 mirrors current I2 of transistor M41. The current mirror circuit 60 is configured such that the mirror ratio K can be changed, and sinks the second correction current Ic2=I2'×K from the OUT terminal. The sizes of the plurality of transistors M51, M52, . . . may be binary weighted.

The current mirror circuit 58 includes a plurality of fuses F1, F2, . . . and a plurality of transistors M61, M62, . The mirror ratio K can be changed depending on whether each of the fuses F1, F2, . . . is blown. Specifically, when the i-th fuse F1 is fused, the corresponding transistor M6i is turned off and the current path is cut off.

According to the second correction unit 44 of FIGS. 28A and 28B, by amplifying the current I2 whose current amount dynamically changes according to the phase voltage VCM with the mirror ratio K corresponding to the trimming, A suitable offset can be introduced in the transistor pair M5, M6 of the upper circuit 22. FIG.

FIG. 29 is a diagram for explaining the operation of the operational amplifier 1A of FIG. The horizontal axis represents the common mode input voltage. FIG. 29 shows the first tail current I1_1, the second tail current I1_2, the first correction currents I_R1 and R2, and the second correction currents I_R3 and R4.

FIG. 30 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage in operational amplifier 1A of FIG. FIG. 30 shows a plurality of characteristics using the mirror ratio K of the current mirror circuit 60 of FIG. 28(b) as a parameter. These characteristics show the characteristics before optimizing the first correction section 42, so the input offset voltage in the low voltage region is non-zero. As can be seen from FIG. 30, adjusting the input offset voltage in the high voltage range does not affect the input offset voltage in the low voltage range. Therefore, the input offset voltages of the high voltage region and the low voltage region can be optimized independently, and both of them can be close to zero.

(Modification 4.1)
FIG. 31 is a circuit diagram of an operational amplifier 1B according to modification 4.1. Regarding the configuration and operation of the operational amplifier 1B, differences from the operational amplifier 1A of FIG. 25 will be described. In the operational amplifier 1A of FIG. 25, the first correction signal Sc1 changes according to the common-mode input voltage VCM. In contrast, in the operational amplifier 1B of FIG. 31, the first correction signal Sc1 generated by the first correction section 42B of the correction circuit 40B is constant and does not depend on the common-mode input voltage VCM.

FIG. 32 is a circuit diagram of the first correction section 42B. The first correction unit 42B can be grasped as a configuration in which the transistors M31 to M34 are omitted from the first correction unit 42 of FIG. 27, and the output current I1 of the current mirror circuit 54 becomes the correction current IR.

33A and 33B are diagrams for explaining the operation of the operational amplifier 1B in FIG. The horizontal axis represents the common mode input voltage. FIG. 33 shows the first tail current I1_1, the second tail current I1_2, the first correction currents I_R1 and R2, and the second correction currents I_R3 and R4.

FIG. 34 is a diagram showing the relationship between the common-mode input voltage and the input offset voltage in operational amplifier 1B of FIG. FIG. 30 shows a plurality of characteristics using the mirror ratio K of the current mirror circuit 60 of FIG. 28(b) as a parameter. These characteristics show the characteristics before optimizing the first correction section 42, so the input offset voltage in the low voltage region is non-zero. Also in variant 4.1, adjusting the input offset voltage in the high voltage range does not affect the input offset voltage in the low voltage range. Therefore, the input offset voltages of the high voltage region and the low voltage region can be optimized independently, and both of them can be close to zero.

However, in Modification 4.1, as shown by the dashed line in FIG. 34, when the input offset voltage in the high voltage region is made equal to that in the low voltage region, a dip (or peak) that cannot be completely compensated in the transition region. may remain. Therefore, modification 4.1 can reduce the circuit area compared to embodiment 4.1 at the expense of compensating the input offset voltage. Conversely, according to Example 4.1, a flat zero input offset voltage can be realized in the common-mode input voltage range including the transition region.

(Modification 4.2)
In modification 4.1, the first correction current is constant and the second correction current is dynamically changed according to the common-mode input voltage, but this is not the only option. Conversely, the second correction current may be constant and the first correction current may be dynamically varied according to the common mode input voltage.

(Modification 4.3)
An operational amplifier 1C according to modification 4.3 will be described with reference to FIGS. FIG. 35 is a circuit diagram of an operational amplifier 1C according to modification 4.3. Differences between the operational amplifier 1C in FIG. 35 and the operational amplifier 1A in FIG. 26 will be described. The first correction unit 42C changes the drain voltages Vu and Vv of the transistors M6 and M5 of the lower circuit 21C. The second correction unit 44C changes the drain voltages Vx and Vy of the transistors M9 and M10 of the upper circuit 22C.

36(a) and (b) are circuit diagrams of the first correction section 42C and the second correction section 44C of FIG. The first correction section 42C includes transistors M11 to M14, a common mode feedback circuit 70, and a correction current generation section 72. FIG. A common mode feedback circuit 70 clamps the drains of transistors M11 and M12 to a common mode voltage to prevent saturation of transistors M13 and M14.

Correction current generator 72 sinks a trimmable current from one of nodes V3 and V4. The amount of sink current is adjusted so that the offset voltage approaches zero. For example, the correction current generating section 72 can be configured in the same manner as the second correction section 44 in FIG. 28(a). The drains of transistors M13 and M14 are connected to the drains of transistors M6 and M5 in FIG.

The second correction section 44C includes transistors M15 to M18, a common mode feedback circuit 74, and a correction current generation section . A common mode feedback circuit 74 clamps the drains of transistors M15 and M16 to a common mode voltage to prevent saturation of transistors M17 and M18.

Correction current generator 76 sources a trimmable current to one of nodes V1 and V2. The amount of source current is adjusted so that the offset voltage approaches zero. For example, the correction current generating section 76 can be configured similarly to the first correction section 42 in FIG. 27 or the first correction section 42B in FIG. The drains of transistors M17 and M18 are connected to the drains of transistors M9 and M10 in FIG.

FIG. 37 is a circuit diagram of the switching circuit 80. As shown in FIG. The switching circuit 80 switches the operation of the first correction section 42C in FIG. 36(a) and the operation of the second correction section 44C in FIG. 36(b). The switching circuit 80 includes transistors M71-M75. The basic configuration and operation of the switching circuit 80 are similar to those of the switching circuit 30 of FIG.

The source of transistor M71 is connected to node N1 in FIG. 36(a). When the common-mode input voltage VCM is low, the current flowing through the transistor M71 is zero, and the tail current IA1 flows through the transistors M11 and M12 in FIG. 36(a). When the common-mode input voltage VCM increases, the current flowing through the transistor M71 increases, the tail currents of the transistors M11 and M12 in FIG. 36(a) decrease, and the first correction section 42C turns off.

The transistor M73 corresponds to the tail current source 75 of the transistors M15 and M16 in FIG. 36(b). When the common mode input voltage VCM is low, the current through transistor M71 is zero and therefore the tail current IB1 is also zero. When the common-mode input voltage VCM increases, the current flowing through the transistor M71 increases, the tail current IB1 increases, the tail currents of the transistors M15 and M16 in FIG. 36(b) decrease, and the second correction section 44C turns on. .

(Appendix 4)
The following technical idea is disclosed in the fourth embodiment.

(Item 4.1)
an inverting input terminal that receives a first input voltage and a non-inverting input terminal that receives a second input voltage;
a first polarity first input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a second polarity second input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a first tail current source that supplies a first tail current to the first input differential pair;
a second tail current source that supplies a second tail current to the second input differential pair;
an output stage that converts the differential current flowing through the first differential input pair and the differential current flowing through the second differential input pair into an output voltage;
a correction circuit that dynamically changes the state of the output stage in response to the first input voltage and the second input voltage;
An operational amplifier comprising:
(Item 4.2)
the output stage includes an upper circuit and a lower circuit vertically stacked between a power supply line and a ground line;
The correction circuit adjusts the state of the lower circuit when the first differential input pair is active and adjusts the state of the upper circuit when the second differential input pair is active. An operational amplifier according to item 4.1, characterized in that
(Item 4.3)
The output stage is
a first constant current circuit that folds back the differential current of the first input differential pair;
a first gate grounding circuit provided on a path of the differential current folded back by the first constant current circuit;
a second constant current circuit that folds back the differential current of the second input differential pair;
a second gate grounding circuit provided on a path of the differential current folded back by the second constant current circuit;
including
Item 4.1 or 4., wherein the correction circuit adjusts states of the first constant current circuit and the second constant current circuit according to the first input voltage and the second input voltage. 2. The operational amplifier according to claim 2.
(Item 4.4)
The correction circuit is
a first correction unit that supplies a first correction current to the first constant current circuit;
a second correction unit that supplies a second correction current to the second constant current circuit;
An operational amplifier according to item 4.3, characterized in that it comprises:
(Item 4.5)
The first correction unit is
a first current source that generates a first reference current;
a first transistor having a gate to which the first input voltage is input;
a second transistor provided in parallel with the first transistor and having a gate to which the second input voltage is input;
5. The operational amplifier of clause 4.4, wherein said first correction current is responsive to currents flowing through said first transistor and said second transistor.
(Item 4.6)
Items 4.1 to 4.5, further comprising a switching circuit that dynamically changes the first tail current and the second tail current in response to the first input voltage and the second input voltage. An operational amplifier according to any one of the preceding claims.
(Item 4.7)
An operational amplifier according to item 4.6, characterized in that the correction circuit adjusts the state of the output stage in conjunction with the state of the switching circuit.
(Item 4.8)
an inverting input terminal that receives a first input voltage and a non-inverting input terminal that receives a second input voltage;
a first input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a second input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a first tail current source that supplies a first tail current to the first input differential pair;
a second tail current source that supplies a second tail current to the second input differential pair;
a switching circuit that dynamically changes the first tail current and the second tail current according to the first input voltage and the second input voltage;
an output stage including a lower circuit connected to the first differential input pair and an upper circuit connected to the second differential input pair;
a correction circuit that supplies a first correction current corresponding to the first input voltage and the second input voltage to the lower circuit and a second correction current corresponding to the state of the switching circuit to the upper circuit; ,
An operational amplifier comprising:
(Item 4.9)
an inverting input terminal that receives a first input voltage and a non-inverting input terminal that receives a second input voltage;
a first input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a second input differential pair connected to the inverting input terminal and the non-inverting input terminal;
a first tail current source that supplies a first tail current to the first input differential pair;
a second tail current source that supplies a second tail current to the second input differential pair;
a switching circuit that dynamically changes the first tail current and the second tail current according to the first input voltage and the second input voltage;
a first constant current circuit that folds back the differential current of the first input differential pair;
a first gate grounding circuit provided on a path of the differential current folded back by the first constant current circuit;
a second constant current circuit that folds back the differential current of the second input differential pair;
a second gate grounding circuit provided on a path of the differential current folded back by the second constant current circuit;
a correction circuit that supplies a first correction current and a second correction current to the first constant current circuit and the second constant current circuit in conjunction with the switching circuit;
An operational amplifier comprising:

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

100 reference current source 102 power supply line 104 ground line 110 current mirror circuit 112 first path 114 second path 116 third path C1 capacitor M1 first transistor M2 second transistor M3 third transistor M4 fourth transistor M5 fifth transistor M6 third 6 transistor R resistance

Claims (10)

a reference current source;
a starter circuit;
with
The reference current source is
a first transistor and a second transistor whose control terminals are connected to each other;
A second path including a first transistor is supplied with the same amount of current as the current flowing in the first path including the second transistor, and a current of a predetermined several times the current of the first path is supplied to a separate third path. a current mirror circuit that supplies a quantity of current;
a third transistor provided on the third path and having a source connected to one end of the first transistor;
a fourth transistor provided at a lower potential side than the third transistor on the third path and having a gate commonly connected to the gate of the third transistor;
a resistor provided between the source of the fourth transistor and one end of the second transistor;
with
The starting circuit is
A first circuit provided between a power supply line and a ground line, wherein a first current flows from the power supply line to the ground line at startup and a second current corresponding to the first current is supplied to the reference current source. and,
a second circuit that acts on the first circuit such that the second current becomes zero when a third current corresponding to the second current flows;
a capacitor charged by a fourth current corresponding to the second current;
including
The semiconductor device, wherein the first circuit is configured to cut off the first current flowing through the first circuit when the voltage of the capacitor rises. a reference current source;
a starter circuit;
with
The reference current source is
a first transistor and a second transistor whose control terminals are connected to each other;
A second path including a first transistor is supplied with the same amount of current as the current flowing in the first path including the second transistor, and a current of a predetermined several times the current of the first path is supplied to a separate third path. a current mirror circuit that supplies a quantity of current;
a third transistor provided on the third path and having a source connected to one end of the first transistor;
a fourth transistor provided at a lower potential side than the third transistor on the third path and having a gate commonly connected to the gate of the third transistor;
a resistor provided between the source of the fourth transistor and one end of the second transistor;
with
The starting circuit is
a capacitor having a first end grounded;
a first transistor having a grounded gate;
a second transistor having a source grounded and a gate-drain connected to the drain of the first transistor;
a third transistor having a source grounded, a gate connected to the gate of the second transistor, and a drain connected to the gate and drain of the reference current source transistor;
a fourth transistor having a source connected to the power supply line, a drain connected to the source of the first transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a fifth transistor having a source connected to the power supply line and having a gate connected to the gate and the drain of the transistor of the reference current source;
a sixth transistor whose source is grounded and whose gate and drain are connected;
a seventh transistor having a source grounded, a gate connected to the gate of the sixth transistor, and a drain connected to the drain of the second transistor;
an eighth transistor having a source connected to the drain of the fifth transistor, a drain connected to the drain of the sixth transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a ninth transistor having a source connected to the power supply line, a gate connected to the gate and the drain of the transistor of the reference current source, and a drain connected to the second end of the capacitor;
A semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein said third transistor and said fourth transistor of said reference current source operate in a subthreshold region . The reference current source further comprises a fifth transistor provided on the lower potential side than the fourth transistor on the third path,
4. The semiconductor device according to claim 1, wherein the voltage of the control terminal of said fifth transistor is supplied to the gates of said third transistor and said fourth transistor. The current mirror circuit of the reference current source comprises:
a sixth transistor connected to the first transistor;
a seventh transistor connected to the second transistor;
an eighth transistor connected to the third path;
5. The semiconductor device according to claim 1, comprising: a reference current source;
a starter circuit;
with
The reference current source is
a first transistor and a second transistor whose control terminals are connected to each other;
A second path including a first transistor is supplied with the same amount of current as the current flowing in the first path including the second transistor, and a current of a predetermined several times the current of the first path is supplied to a separate third path. a current mirror circuit that supplies a quantity of current;
a plurality of MOS transistors provided in series on the third path and having gates connected in common;
with
one end of the first transistor is connected to one end of one of the plurality of MOS transistors, one end of the second transistor is connected to another one end of the plurality of MOS transistors via a resistor,
The starting circuit is
A first circuit provided between a power supply line and a ground line, wherein a first current flows from the power supply line to the ground line at startup and a second current corresponding to the first current is supplied to the reference current source. and,
a second circuit that acts on the first circuit such that the second current becomes zero when a third current corresponding to the second current flows;
a capacitor charged by a fourth current corresponding to the second current;
including
The semiconductor device , wherein the first circuit is configured to cut off the first current flowing through the first circuit when the voltage of the capacitor rises. a reference current source;
a starter circuit;
with
The reference current source is
a first transistor and a second transistor whose control terminals are connected to each other;
A second path including a first transistor is supplied with the same amount of current as the current flowing in the first path including the second transistor, and a current of a predetermined several times the current of the first path is supplied to a separate third path. a current mirror circuit that supplies a quantity of current;
a plurality of MOS transistors provided in series on the third path and having gates connected in common;
with
one end of the first transistor is connected to one end of one of the plurality of MOS transistors, one end of the second transistor is connected to another one end of the plurality of MOS transistors via a resistor,
The starting circuit is
a capacitor having a first end grounded;
a first transistor having a grounded gate;
a second transistor having a source grounded and a gate-drain connected to the drain of the first transistor;
a third transistor having a source grounded, a gate connected to the gate of the second transistor, and a drain connected to the gate and drain of the reference current source transistor;
a fourth transistor having a source connected to the power supply line, a drain connected to the source of the first transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a fifth transistor having a source connected to the power supply line and having a gate connected to the gate and the drain of the transistor of the reference current source;
a sixth transistor whose source is grounded and whose gate and drain are connected;
a seventh transistor having a source grounded, a gate connected to the gate of the sixth transistor, and a drain connected to the drain of the second transistor;
an eighth transistor having a source connected to the drain of the fifth transistor, a drain connected to the drain of the sixth transistor, and a gate to which the voltage of the second end of the capacitor is applied;
a ninth transistor having a source connected to the power supply line, a gate connected to the gate and the drain of the transistor of the reference current source, and a drain connected to the second end of the capacitor;
A semiconductor device comprising: 8. The semiconductor device according to claim 1, wherein said first transistor and said second transistor of said reference current source have the same size . 9. The semiconductor device according to claim 1, wherein said first transistor and said second transistor of said reference current source are FETs (Field Effect Transistors) . 9. The semiconductor device according to claim 1, wherein said first transistor and said second transistor of said reference current source are bipolar transistors.

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