JP2017062616A - Reference current source circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a start time of a semiconductor integrated circuit including a reference current source circuit.SOLUTION: A reference current source circuit 100 supplies a reference current Ito an analog circuit 202. A constant current circuit 10 generates a reference current I. A start circuit 20 supplies, when the reference current source circuit 100 starts, a first start current Ito the constant current circuit 10 and supplies a second start current Ito the analog circuit 202.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a reference current source circuit.

  Generally, a semiconductor integrated circuit has a reference current source circuit that generates a constant reference current that does not depend on a power supply voltage, etc., and the reference current is copied and distributed as a bias current to various circuit blocks in the semiconductor integrated circuit. Is done.

FIG. 1 is a block diagram of a semiconductor integrated circuit 200r including a reference current source circuit 100r. The semiconductor integrated circuit 200r includes a reference current source circuit 100r and an analog circuit 202 that operates based on the reference current I _REF generated by the reference current source circuit 100r. The type of the analog circuit 202 is not particularly limited, and may include an operational amplifier, a differential amplifier, a comparator, a voltage regulator, a VCO (Voltage Controlled Oscillator), an analog timer circuit, and the like. The reference current source circuit 100r includes a constant current circuit 10r and a starting circuit 20r. The constant current circuit 10 r generates a reference current I _REF and supplies it to the analog circuit 202.

In general, the constant current circuit 10r has a plurality of stable operating points, one of which is in a state where the current is zero. Starting circuit 20r at the time of startup of the reference current source circuit 100r generates a starting current I _S, by supplying the constant current circuit 10r, the transition to the constant current circuit 10r, current normal operation point of the non-zero Let When the startup of the constant current circuit 10r is completed, the path of the activation current I _S is cut off in response to the activation completion signal S1.

Further, the semiconductor integrated circuit 200r may be used in a system that supports a shutdown mode (also referred to as a sleep mode or an energy saving mode). In such a system, in a non-operating state, the reference current source circuit 100r is stopped, and the supply of the reference current I _REF to the analog circuit 202 is stopped. Specifically, while the shutdown signal SHTDN is asserted (for example, high level), the current paths of the constant current circuit 10r and the starting circuit 20r are cut off, and the reference current I _REF becomes zero.

JP 2001-344028 A JP 2006-133869 A

  As a result of examining the activation of the semiconductor integrated circuit 200r of FIG. 1, the present inventors have recognized the following problems. FIG. 2 is an operation waveform diagram at the time of startup of the semiconductor integrated circuit 200r of FIG. Here, the return start from the shutdown state will be described.

Prior to time t0, the shutdown signal SHTDN is asserted, and the reference current source circuit 100r and the analog circuit 202 are stopped. When the shutdown signal SHTDN is negated at time t0, the shutdown state is released and the system starts to start. Specifically it is generated starting current I _S by the activation circuit 20r, then constant current circuit 10r to time t1 when transition to the normal operation point, the reference current I _REF reaches the design value. When the startup completion signal S1 at this time is asserted, it is cut off the current path of the starting circuit 20r is, the starting current I _S is stopped.

When the reference current I _REF starts to flow, the parasitic capacitance and the phase compensation capacitor in the analog circuit 202 are charged, and the voltage and current of the circuit elements in the analog circuit 202 approach those in the normal operation state, and the time t2 Then, the output of the analog circuit 202 reaches the design value.

Start time _{T C} of the entire semiconductor integrated circuit 200r is a start total time _{T B} of the starting time of the reference current source circuit 100r _{T A} and the analog circuit 202.

Many analog circuits 202 include a feedback configuration to stabilize them and take a long time to start. Therefore, even able to temporarily shorten the start time T _A of the reference current source circuit 100r, the longer the start time T _B of the analog circuit 202, the total startup time T _C are that are constrained by the activation time T _B Become.
Note that the above consideration should not be taken as a general recognition of those skilled in the art.

  The present invention has been made in view of these problems, and one of exemplary objects of an embodiment thereof is to provide a reference current source circuit capable of shortening the startup time of a semiconductor integrated circuit.

  One embodiment of the present invention relates to a reference current source circuit that supplies a reference current to an analog circuit. The reference current source circuit includes a constant current circuit that generates a reference current, and a startup circuit that supplies a first startup current to the constant current circuit and a second startup current to an analog circuit when the reference current source circuit is started up. .

  According to this aspect, the start-up time of the semiconductor integrated circuit can be shortened by starting the analog circuit in parallel with the start of the constant current circuit before the start of the constant current circuit is completed.

  The startup circuit may supply the second startup current to the analog circuit through the same path as the reference current.

The starting circuit may change the amount of the second starting current with time.
When the constant current circuit is activated and the reference current starts to flow, the analog circuit is supplied with the sum of the reference current and the second activation current, and the open loop gain of the analog circuit is increased. Therefore, the oscillation of the analog circuit can be suppressed by changing the amount of the second starting current.

  The startup circuit may use the second startup current as the first current amount immediately after startup, and then set the second startup current as the second current amount smaller than the first current amount.

  The starting circuit may switch the amount of the second starting current based on the comparison result between the voltage of one node inside the constant current circuit and the threshold voltage. For one node, a node that generates a voltage having a correlation with a reference current generated by the constant current circuit may be selected. In other words, a node that generates a voltage indicating the progress of activation of the constant current circuit may be selected.

  The constant current circuit may include a current source provided on the first line side that is one of the power supply line and the ground line, and a current mirror circuit provided on the second line side that is the other of the power supply line and the ground line. . The reference current source circuit may further include a phase compensation capacitor connected to the constant current circuit. The starting circuit may supply the first starting current to a connection node between the capacitor and the constant current circuit.

  Directly charge the capacitor by supplying the first starting current generated by the starting circuit to the connection node of the capacitor for phase compensation instead of or in addition to supplying the current mirror circuit or current source of the constant current circuit. Thus, the constant current circuit can be started up in a short time.

  The start-up circuit may switch the amount of the second start-up current based on the comparison result between the voltage at the connection node between the capacitor and the constant current circuit and the threshold voltage.

  The starting circuit includes a resistor and a first transistor provided in series between a power supply line and a ground line, a second transistor connected to form a current mirror with the first transistor, a first transistor and a current mirror. A third transistor connected so as to form, a current flowing through the second transistor is supplied to the capacitor as a first starting current, and a current flowing through the third transistor is supplied to the analog circuit as a second starting current May be.

  The start circuit includes a fourth transistor connected to form a current mirror with the first transistor, a switch provided in series with the fourth transistor, a voltage at a connection node between the capacitor and the constant current circuit, and a threshold voltage. And a control circuit for switching on and off of the switch based on the comparison result. The second starting current may be the sum of currents flowing through the third transistor and the fourth transistor.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the startup time of the semiconductor integrated circuit can be shortened.

It is a block diagram of a semiconductor integrated circuit provided with a reference current source circuit. FIG. 2 is an operation waveform diagram when the semiconductor integrated circuit of FIG. 1 is started. 1 is a block diagram of a semiconductor integrated circuit including a reference current source circuit according to a first embodiment. FIG. 4 is an operation waveform diagram when the reference current source circuit of FIG. 3 is started. 1 is a block diagram of a reference current source circuit according to a first embodiment. FIG. 1 is a circuit diagram of a reference current source circuit according to a first embodiment. FIG. 7A and 7B are operation waveform diagrams at the time of starting the reference current source circuit of FIG. FIG. 7 is a circuit diagram showing a modification of the reference current source circuit of FIG. 6. FIG. 6 is a block diagram of a semiconductor integrated circuit including a reference current source circuit according to a second embodiment. FIG. 10 is an operation waveform diagram when the reference current source circuit of FIG. 9 is activated. FIG. 6 is a circuit diagram of a reference current source circuit according to a second embodiment. FIG. 12 is a circuit diagram showing a modification of the reference current source circuit of FIG. 11. FIG. 13 is an operation waveform diagram of the reference current source circuit of FIG. 12. It is a circuit diagram of the reference current source circuit concerning the 1st modification. It is a circuit diagram of the reference current source circuit concerning the 2nd modification. It is a circuit diagram of a reference current source circuit according to a fifth modification. FIG. 17A is an operation waveform diagram of the reference current source circuit of FIG. 16, and FIG. 17B is an operation waveform diagram of the comparative technique in which the peak cut transistor is omitted. It is a circuit diagram of the reference current source circuit which concerns on a 6th modification. FIG. 19 is an operation waveform diagram of the reference current source circuit of FIG. 18.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

(First embodiment)
FIG. 3 is a block diagram of a semiconductor integrated circuit 200 including the reference current source circuit 100 according to the first embodiment. The semiconductor integrated circuitry 200 includes a reference current source circuit 100 for generating a reference current _{I REF,} an analog circuit 202 for the reference current _{I REF} is supplied, the. The analog circuit 202 is biased by one or more bias currents proportional to the reference current I _REF , and its operating point is defined. The type of the analog circuit 202 is not particularly limited, and may include an operational amplifier, a differential amplifier, a comparator, a voltage regulator, a VCO (Voltage Controlled Oscillator), an analog timer circuit, a switched capacitor circuit, and the like.

The reference current source circuit 100 includes a constant current circuit 10 and a starting circuit 20. The constant current circuit 10 generates a reference current I _REF . The startup circuit 20 supplies the first startup current I _S1 to the constant current circuit 10 and the second startup current I _S2 to the analog circuit 202 when the reference current source circuit 100 is started up.

Preferably, the startup circuit 20 may supply the second startup current I _S2 to the analog circuit 202 via the same path as the reference current I _REF .

The semiconductor integrated circuit 200 can be used in a system that supports a shutdown mode (also referred to as a sleep mode or an energy saving mode). The reference current source circuit 100 stops the constant current circuit 10 and stops the reference current I _REF while the shutdown signal SHTDN is asserted.

  The above is the basic configuration of the reference current source circuit 100 according to the first embodiment. Next, the operation will be described. FIG. 4 is an operation waveform diagram at the time of starting the reference current source circuit 100 of FIG.

Prior to time t0, the shutdown signal SHTDN is asserted, and the reference current source circuit 100 and the analog circuit 202 are stopped. When the shutdown signal SHTDN is negated at time t0, the shutdown state is released and recovery starts. Specifically, when the first startup current _IS is generated by the startup circuit 20, and then the constant current circuit 10 shifts to a normal stable operating point at time t1, the reference current _IREF reaches the design value. Then, based on the activation completion signal S1, the current path of the activation circuit 20 is interrupted, and the first activation current I _S1 is stopped.

Prior to the time t1 when the start-up of the constant current circuit 10 is completed, the second start-up current _IS2 is supplied to the analog circuit 202 from the time t0. The voltage and current of the circuit elements in the analog circuit 202 approach those in the normal operation state by the second starting current I _S2 . At time t3, the output of the analog circuit 202 is stabilized to the design value. At time t1, the second startup current I _S2 also stops based on the startup completion signal S1.

  The above is the operation of the reference current source circuit 100. According to the reference current source circuit 100, the start-up time of the analog circuit 202 can be significantly shortened by starting the constant-current circuit 10 and the analog circuit 202 simultaneously from the start-up (t0).

In the semiconductor integrated circuit 200r of FIG. 1, the parasitic elements and capacitors inside the analog circuit 202 are charged by the reference current _IREF and the bias current based on the reference current IREF. However, in the semiconductor integrated circuit 200 of FIG. It is charged by current _IS2 . Therefore a second activation current _{I S2,} by increasing than the design value of the reference current _{I REF (I S2> I REF} ), for quickened charging rate of the capacitor and the parasitic capacitance, the start time _{T B} itself of the analog circuit 202 It can be shortened.

Note that when the I _S2 ≦ I _REF, start time T _B of the analog circuit 202 may be comparable with that of Figure 1, but an analog circuit 202 Even in this case, wait for the activation completion of the constant current circuit 10 to begin to start without again starting time T _C of the entire semiconductor integrated circuit 200 is reduced.

  A certain aspect of the present invention is understood as the block diagram and circuit diagram of FIG. 2 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 5 is a block diagram of the reference current source circuit 100 according to the first embodiment.
The reference current source circuit 100 includes a constant current circuit 10, a capacitor C1, a starting circuit 20, and an output circuit 30. The constant current circuit 10 includes a current source 12 and a current mirror circuit 18. Current source 12 is provided on one of the power supply line 102 side and the ground line 104 side (in FIG. 2 ground line 104 side), to generate a first transistor 14 and second current _{I 2} generates the first current _{I 1} A second transistor 16 is included.

The current mirror circuit 18 is provided to the power supply line 102 side and the ground line 104 side of the other (in FIG. 2 supply line 102 side), the first current _{I 1} and the second current _{I 2} to a predetermined ratio (mirror ratio K) Stabilize.

  The basic configuration and principle of the constant current circuit 10 are described in, for example, Chapter 11 of “Design of Analog CMOS Integrated Circuits” by Behzad Razavi or Chapter 4.4 of “Analysis and Design of Analog Integrated Circuits” by PR Gray. Has been. Those skilled in the art will understand that there may be various configuration examples of the constant current circuit 10, and the application of the present invention is not limited to a specific circuit type with respect to the constant current circuit 10.

The output circuit 30 generates a reference current I _REF proportional to the currents I ₁ and I ₂ flowing through the current source 12 or the current mirror circuit 18 and supplies the reference current I _REF to an analog circuit 202 (not shown). For example, the output circuit 30 may include an output transistor M0a connected to copy the current flowing through the current source 12, or include an output transistor M0b connected to copy the current flowing through the current mirror circuit 18. But you can. Also regarding the configuration of the output circuit 30, the present invention is not particularly limited.

  The capacitor C1 is connected to the constant current circuit 10 for the purpose of phase compensation. The capacitor C1 may be connected to a location where the feedback of the constant current circuit 10 can be stabilized, and can be appropriately selected according to the circuit type of the constant current circuit 10. As will be described later, a plurality of phase compensation capacitors may be provided. In a circuit having a sufficiently large parasitic capacitance such as a gate capacitance, the parasitic capacitance can be used as a phase compensation capacitor, so that the capacitor C1 as a circuit element can be omitted.

Starting circuit 20, at the start of the reference current source circuit 100 supplies a first activation current _{I S1} to the connection node N1 between the constant current circuit 10 and a capacitor C1.

Capacitor C1 for phase compensation, with the configuration that is charged only by current I ₁ or I _2, since the charging time of the voltage V _C1 of the capacitor is increased, it takes time to start. In the reference current source circuit 100 of FIG. 3, by supplying the first starting current I _S1 to the connection node N1 between the capacitor C1 and a current source 12 for phase compensation, the capacitor C1 directly charged by the first starting current I _S1 Therefore, the constant current circuit 10 can be started up in a short time.

  In FIG. 3, the top and bottom may be reversed, that is, the constant current circuit 10 may be provided on the power supply line 102 side and the current mirror circuit 18 may be provided on the ground line 104 side.

The second starting current I _{S2 that} is sourced by the starting circuit 20 is added to the current I _REFa of the output transistor M0a. Alternatively, the starting circuit 20 may sink the second starting current I _S2 ′ and add it to the current I _REFb of the output transistor M0b.

  Hereinafter, the configuration of the reference current source circuit 100 will be described with reference to a more detailed circuit diagram.

  FIG. 6 is a circuit diagram of the reference current source circuit 100a according to the first embodiment. The current source 12a includes a first transistor M1 to a third transistor M3 and a first resistor R1. The first transistor M1 and the second transistor M2 are NPN-type bipolar transistors and correspond to the first transistor 14 and the second transistor 16 in FIG. The collector and base of the first transistor M1 are connected. The base of the second transistor M2 is connected to the base of the first transistor M1, and the emitter thereof is connected to the ground line 104.

  The first resistor R1 is inserted between the emitter of the first transistor M1 and the ground line 104. The first transistor M1, the second transistor M2, and the first resistor R1 are so-called reverse Wider current mirrors (reverse Wideler current sources).

The first resistor R1 may be inserted between the emitter of the second transistor M2 and the ground line 104. In this case, the first transistor M1, the second transistor M2, and the first resistor R1 are so-called Wideler current mirrors. Currents I ₁ and I ₂ corresponding to the size ratio and the resistance value of the first resistor R1 flow through the first transistor M1 and the second transistor M2.

The third transistor M3 is an N-channel MOSFET, its gate is connected to the collector of the second transistor M2, and its source is connected to the ground line 104. The third transistor M3 flows third current _{I 3.}

  The current mirror circuit 18a includes a fourth transistor M4 to a sixth transistor M6. The fourth transistor M4 to the sixth transistor M6 are P-channel MOSFETs, their sources are connected to the power supply line 102, and their gates are connected in common. The gate and drain of the sixth transistor M6 are connected.

The current mirror circuit 18a stabilizes the first current _{I 1} and the second current _{I 2} respectively into a current proportional to the third current _{I 3.} The size ratio of the transistors _{M4, M5, M6 K 4:} K 5: When _{K 6,} the first current _{I 1,} the second current _{I 2,} respectively, by feedback,
I ₁ = I ₃ × K ₄ / K ₆
I ₂ = I ₃ × K ₅ / K ₆
So that I ₁ : I ₂ is stabilized to K ₄ : K ₅ .

  The fourth transistor M4 to the sixth transistor M6 may be composed of PNP-type bipolar transistors.

  The capacitor C1 is provided between the gate of the third transistor M3 and the ground line 104. That is, in the reference current source circuit 100a of FIG. 3, the gate of the third transistor M3 (the collector of the second transistor M2) corresponds to the connection node N1 of FIG.

  The activation circuit 20a mainly includes a seventh transistor M7, two eighth transistors M8a and M8b, and a second resistor R2. The seventh transistor M7 and the second resistor R2 are provided in series between the power supply line 102 and the ground line 104. The eighth transistors M8a and M8b are connected to form the current mirror 22 together with the seventh transistor M7. The third resistor R3 is provided between the gate and drain of the seventh transistor M7.

The starting circuit 20a supplies the current flowing through the eighth transistor M8a to the capacitor C1 as the first starting current I _{S1 at the time} of starting. The current flowing through the eighth transistor M8b, supplied to the analog circuit 202 as a second activation current _{I S2.}

Assuming that the threshold voltage between the gate and source of the seventh transistor M7 is V _{GS (TH)} , the current I _M7 flows through the path including the seventh transistor M7 and the second resistor R2 when the reference current source circuit 100a is activated. .
I _M7 = (V _DD −V _{GS (TH)} ) / R2
At this time, currents I _S1 and I _S2 proportional to the current I _M7 flow through the eighth transistors M8a and M8b.

The activation circuit 20a further includes a ninth transistor M9 and a cutoff circuit 24. The ninth transistor M9 is connected to the current source 12 so that a current I _M9 proportional to the first current I ₁ and the second current I ₂ flows. Specifically, the ninth transistor M9 is an NPN-type bipolar transistor, its emitter is connected to the ground line 104, and its base is connected to the bases of the first transistor M1 and the second transistor M2.

The cutoff circuit 24 turns off the seventh transistor M7 when the current I _M9 flowing through the ninth transistor M9 increases. For example, the cutoff circuit 24 may include a tenth transistor M10 and an eleventh transistor M11 of a P-channel MOSFET. The tenth transistor M10 is provided between the ninth transistor M9 and the power supply line 102, and its control terminal (gate) and one end (drain) thereof are connected. The control terminal (gate) of the eleventh transistor M11 is connected to the gate of the tenth transistor M10, one end (drain) thereof is connected to the control terminal (gate) of the seventh transistor M7, and the other end (source) is connected to the power supply line 102. Connected.

The output circuit 30a includes an output transistor M0a. The output transistor M0a is to flow a reference current _{I REF} proportional to the first current _{I 1} ~ third current _{I 3} is connected to the current mirror circuit 18a. Specifically, the output transistor M0a is a transistor of the same type as the current mirror circuit 18a, that is, a P-channel MOSFET, and the source thereof is connected to the power supply line 102 similarly to the sources of the fourth transistor M4 to the sixth transistor M6. The gate is connected to the gates of the fourth transistor M4 to the sixth transistor M6.

The output circuit 30a may include an output transistor M0b of an N channel MOSFET. The output transistor M0b is to flow the third current current I _REF proportional to I _3, together with the third transistor M3 may be connected to form a current mirror.

FIGS. 7A and 7B are operation waveform diagrams (simulation results) when the reference current source circuit 100a of FIG. 6 is started. FIG. 7A shows the reference current I _REF , and FIG. _7B shows the voltage V _{C1 of the} capacitor C1. Each waveform (i) in FIGS. 7A and 7B shows the operation of the reference current source circuit 100a in FIG. For comparison, a waveform (ii) in the case where the first starting current I _S1 ′ is sunk from the sixth transistor M6 along the path indicated by the alternate long and short dash line in FIG. 6 is shown.

In order to clarify the advantages of the reference current source circuit 100a, the waveform (ii) is first referred to. The power is turned on at time t = 10 μs. When the first starting current _{I S1} 'flows through the sixth transistor M6, the current _{I 2} proportional to it flows through the fifth transistor M5, the capacitor C1 is charged. Since the current I2 is extremely small, the voltage V _{C1 of the} capacitor C1 rises slowly at a slow speed, and after the charging time of 75 μs has elapsed, the gate voltage V _C1 becomes the gate-source threshold voltage V _{GS (TH ) And} reach a stable point near 0.9V. Then, as shown in FIG. 7A, at time t = 87 μs, the reference current I _REF reaches the designed value of 450 nA. Therefore, the startup time of the reference current source circuit 100r is 77 μs.

Next, the operation of the reference current source circuit 100a in FIG. 6 will be described with reference to the waveform (i). When the power is turned on at time t = 10 μs, the current I _M7 starts to flow through the path including the seventh transistor M7 and the resistor R2, and the first starting current I _S1 copied by the eighth transistor M8 is directly applied to the capacitor C1. Supplied. As a result, as shown in FIG. 7B, the voltage V _C1 rises to a stable point near 0.9 V in a very short time of 3.6 μs. As shown in FIG. 7A, at time t = 13.9 μs, the reference current I _REF reaches the designed value of 450 nA. Accordingly, the startup time of the reference current source circuit 100 is 3.9 μs.

When the reference current I _REF reaches the design value, the current I _M9 of the ninth transistor M9 increases and the current I _M11 of the eleventh transistor M11 increases. This voltage drop across the second resistor R2 is increased, the gate voltage of the seventh transistor M7 is increased, the seventh transistor M7 is turned off, the starting current I _S is stopped. Thus, the startup time of the reference current source circuit 100a in FIG. 6 is very short.

  In FIG. 6, the transistors M1, M2, and M9 may be N-channel MOSFETs. Alternatively, the transistors M4 to M6 may be composed of PNP bipolar transistors.

  FIG. 8 is a circuit diagram showing a modification of the reference current source circuit 100a of FIG. The reference current source circuit 100b of FIG. 8 further includes a shutdown circuit 40 in addition to the reference current source circuit 100a of FIG. The shutdown circuit 40 receives the shutdown signal SHTDN and interrupts at least one current path of the reference current source circuit 100 during the shutdown state in which the shutdown signal SHTDN is asserted (high level).

For example, shutdown circuit 40 includes transistors M101 to M106 and an inverter 42. Inverter 42 inverts shutdown signal SHTDN. The transistor M101 is connected in parallel with the second transistor M2, and the shutdown signal SHTDN is input to the gate, and is turned on in the shutdown state. Transistor M102 is arranged on a path of third current _{I 3,} inverted shutdown signal #SHTDN is input to the gate in an off in a shutdown state. The transistor M103 is provided between the gates and sources of the transistors M4 and M5. The inverted shutdown signal #SHTDN is input to the gate of the transistor M103 and is turned on in the shutdown state. The transistor M104 is provided between the collector of the first transistor M1 and the ground line 104. A shutdown signal SHTDN is input to the gate of the transistor M104, and the transistor M104 is turned on in the shutdown state. The transistor M105 is provided on the paths of currents I _M7 and I _M8 , and the inverted shutdown signal #SHTDN is input to the gate, which is turned off in the shutdown state. The transistor M106 is provided between the gates and the sources of the transistors M10 and M11. The inverted shutdown signal #SHTDN is input to the gate of the transistor M106 and is turned on in the shutdown state.

According to this modification, it is possible to switch between the operation and non-operation of the reference current source circuit 100b according to the shutdown signal SHTDN after the power supply voltage V _DD is turned on. Therefore, in the standby state (or shutdown state) of the semiconductor integrated circuit using the reference current source circuit 100b, the reference current source circuit 100b is stopped by asserting the shutdown signal SHTDN, and the circuit to which the reference current I _REF is supplied. Can be stopped to reduce current consumption.

Then, when the shutdown signal SHTDN is negated and the normal state is restored from the shutdown state, the start-up circuit 20b can quickly charge the phase compensation capacitor C1, and the reference current source circuit 100b can be quickly charged. Can be returned to the operating state. Further, the second starting current _IS2 is supplied to the analog circuit 202, and the starting time of the analog circuit 202 can be shortened.

(Second Embodiment)
A problem to be solved by the second embodiment will be described. When the analog circuit 202 is a circuit having a feedback loop such as an operational amplifier, it is necessary to consider not to oscillate. The loop gain of the analog circuit 202 depends on the bias current, that is, the original reference current I _REF , and an excessively large bias current can cause the analog circuit 202 to oscillate. Referring to FIG. 4, there is a period (hatched) in which the reference current I _REF and the second starting current I _S2 are simultaneously supplied to the analog circuit 202, and the analog circuit 202 may oscillate during this period. is there.

  One approach to solve this problem is to perform phase compensation assuming a large bias current, but this degrades the responsiveness of the analog circuit 202 and is difficult to adopt in some applications. The reference current source circuit 100 according to the second embodiment solves this problem.

FIG. 9 is a block diagram of a semiconductor integrated circuit 200s including the reference current source circuit 100s according to the second embodiment. In this embodiment, the starting circuit 20s will change with the current amount of the second starting current I _S2 time. The amount of current of the second starting current I _S2 may be switchable in multiple stages, or may be continuously controllable.

The activation circuit 20 s has a current amount of the current I _S2 so that the current I _REF + I _S2 supplied to the analog circuit 202 does not exceed, for example, a predetermined threshold value I _MAX so as not to cause oscillation of the analog circuit 202. To change. That is, in the period in which the reference current I _REF immediately after the start of the constant current circuit 10 is small, the second start current I _S2 is increased, the start of the constant current circuit 10 proceeds, and in the period in which the reference current I _REF is large, the second The starting current I _S2 is decreased.

As an example, the startup circuit 20s sets the second startup current I _S2 as the first current quantity I _X immediately after startup, and then sets the second startup current I _S2 as the second current quantity I _Y smaller than the first current quantity I _X. Also good.

The starting circuit 20s refers to the voltage (signal V _{S in} FIG. 9) of one node inside the constant current circuit 10, and based on the comparison result between the voltage V _S and a predetermined threshold voltage V _TH . The amount of the second starting current I _S2 may be switched.

As shown in FIG. 5, when the phase compensation capacitor C1 is connected to the constant current circuit 10, the second starting current _IS2 may be controlled based on the voltage of the node N1 to which the capacitor C1 is connected. . One node is not limited to the node N1 in FIG. 5, and a node that generates a voltage (V _S ) having a correlation with the reference current I _REF generated by the constant current circuit 10 may be selected. What is necessary is just to select the node where the voltage which shows the progress of starting of the circuit 10 produces.

  The above is the basic configuration of the reference current source circuit 100s according to the second embodiment. Next, the operation will be described. FIG. 10 is an operation waveform diagram at the time of starting the reference current source circuit 100s of FIG.

  Prior to time t0, the shutdown signal SHTDN is asserted, and the reference current source circuit 100s and the analog circuit 202 are stopped. When the shutdown signal SHTDN is negated at time t0, the shutdown state is released and recovery starts.

Specifically first activation current I _S is generated by the activation circuit 20s, is supplied to the constant current circuit 10. In parallel with this, the analog circuit 202 is supplied with the second starting current I _S2 having a relatively large current amount I _X.

The voltage V _{S at} the internal node of the constant current circuit 10 increases with time. When the voltage V _S exceeds the threshold voltage V _TH at time t1, the second starting current I _S2 decreases to the current amount I _Y.

As the constant current circuit 10 starts up, the reference current _{IREF begins} to flow at time t2, and eventually reaches the design value. Then, based on the start completion signal S1, the current path of the start circuit 20 is interrupted, and the first start current I _S1 and the second start current I _S2 are stopped.

The above is the operation of the reference current source circuit 100s. According to the reference current source circuit 100s, the current supplied from the reference current source circuit 100 to the analog circuit 202, that is, the reference current I _REF and the second starting current I _S2 reach the oscillation threshold value I _MAX. By suppressing, oscillation of the analog circuit 202 can be prevented.

  FIG. 11 is a circuit diagram of the reference current source circuit 100t according to the second embodiment. For the sake of brevity, reference numerals are omitted for the shutdown circuit 40, and description thereof is omitted. In the constant current circuit 106, the transistors M1 and M2 are NPN bipolar transistors, and the rest are the same as the constant current circuit 10a of FIG.

  The startup circuit 20t includes a transistor M8c and a current control circuit 28 in addition to the startup circuit 20a of FIG. The transistor M8c is the same type as the transistor M7, and forms a current mirror. The current control circuit 28 includes a switch SWc provided on the path of the transistor M8c and a control circuit 29 for the switch SWc.

The control circuit 29 monitors the voltage V _S of the node N1 of the constant current circuit 10c, turns on the switch SWc when lower than a predetermined threshold voltage V _TH, and turns on the switch SWc when exceeding the threshold voltage V _TH. Turn off. The transistor M29, which is an N-channel MOSFET, is used as a voltage comparator that compares the gate voltage V _S with the threshold voltage V _{GS (TH)} of the MOSFET. When V _S > V _{GS (TH)} , the drain of the transistor M29 becomes low level, and a high level voltage is input to the gate of the switch (transistor) SWc by the inverter INV, and the switch SWc is turned off.

That is, the second starting current I _S2 is the sum of the currents flowing through the transistors M8b and M8c when V _S <V _TH , and is the current flowing through the transistor M8b when V _S > V _TH . According to the reference current source circuit 100t of FIG. 11, the second starting current _IS2 can be switched in two steps as shown in FIG.

FIG. 12 is a circuit diagram showing a modification of the reference current source circuit 100t of FIG. The starting circuit 20u includes a transistor M8d and a switch SWd in addition to the starting circuit 20t of FIG. The current control circuit 28u controls the switches SWc and SWd based on the voltage V _S at the node N1. The current control circuit 28u includes two systems of the control circuit 29 shown in FIG. The threshold voltages V _TH of the control circuits 29c and 29d can be made different according to the size of the transistor M29 or according to the size of the transistor M30.

FIG. 13 is an operation waveform diagram of the reference current source circuit 100t of FIG.
Immediately after startup, is on both the switch SWc, SWd the second starting current _{I S2} therefore is a transistor M8b, M8c, the amount of current _{I X} corresponding to the sum of the currents of M8d. The voltage V _{S at} the internal node of the constant current circuit 10u increases with time. When the voltage V _S exceeds the threshold voltage V _TH1 of the control circuit 29c at time t4, the switch SWc is turned off, and the second starting current I _S2 decreases to the current amount I _Y. When the voltage V _S further increases and the voltage V _S exceeds the threshold voltage V _TH2 of the control circuit 29d at the subsequent time t1, the switch SWd is turned off, and the second starting current I _S2 decreases to the current amount I _Z. .

As the constant current circuit 10 starts up, the reference current _{IREF begins} to flow at time t2, and eventually reaches the design value. Then, based on the start completion signal S1, the current path of the start circuit 20 is interrupted, and the first start current I _S1 and the second start current I _S2 are stopped.

The above is the operation of the reference current source circuit 100u. According to the reference current source circuit 100u, the second starting current I _S2 can be varied in three steps. It will be understood by those skilled in the art that the second startup current I _S2 can be switched in four or more stages by modifying the configuration of the startup circuit 20u.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
FIG. 14 is a circuit diagram of the reference current source circuit 100c according to the first modification. In this modification, the current source 12c is disposed on the power supply line 102 side, and the current mirror circuit 18c is disposed on the ground line 104 side.

The current source 12c includes a self-biased cascode-type first current mirror 13 including transistors M1 ₁ , M1 ₂ , M2 ₁ , M2 ₂ and a resistor Ra, and a fourth resistor R4. The combination of the first current mirror 13 and the fourth resistor R4 can be understood as a circuit in which the Wider current mirror (Widler current source) is changed to a cascode type. The transistors M1 ₁ and M1 ₂ correspond to the first transistor 14 in FIG. 5, and the transistors M2 ₁ and M2 ₂ correspond to the second transistor 16 in FIG. Current source 12c generates a first current _{I 1} and the second current _{I 2} corresponding to the ratio and the resistance Ra of the transistor _M1 2, M2 ₂ sizes.

The current mirror circuit 18 c includes a second current mirror 19 of a self-bias cascode type. The second current mirror 19 includes transistors M3 ₁ , M3 ₂ , M4 ₁ , M4 ₂ and a resistor Rb, and is configured to be symmetrical with the first current mirror 13.

The output circuit 30c includes output transistors M0 ₁ and M0 ₂ and a current mirror 32. The output transistors M0 ₁ and M0 ₂ are connected to the current mirror circuit 18c, and generate a current I ₀ proportional to the first current I ₁ and the second current I ₂ . The current mirror 32 returns the current I ₀ and supplies the reference current I _REF to the analog circuit 202.

Four capacitors C11 to C14 are connected to the constant current circuit 10c for phase compensation. Starting circuit 20c, of the capacitors C11 to C14, supplies a starting current _{I S1} to the capacitor C11 is connected to the gate of the output transistor M0 _2.

The basic configuration of the startup circuit 20c is the same as that of the startup circuit 20b of FIG. 8, and mainly includes a seventh transistor M7, an eighth transistor M8, a second resistor R2, and a third resistor R3. Current flowing through the transistor M8a as a first activation current _{I S1,} it is supplied to the connection node N1 between the capacitor C11 constant current circuit 10c. The ninth transistor M9 and the cutoff circuit 24 are the same as those in FIG.

The activation circuit 20c of FIG. 14 further includes a twelfth transistor M12 and a third current mirror 26. The twelfth transistor M12 is connected to form the current mirror 22 together with the seventh transistor M7 and the eighth transistor M8. The third current mirror 26 folds the current I _M12 of the twelfth transistor M12 to generate a third starting current I _S3 and supplies it to the first current mirror 13 (sink).

(Second modification)
FIG. 15 is a circuit diagram of the reference current source circuit 100d according to the second modification. In this modification, the current source 12d is disposed on the ground line 104 side, and the current mirror circuit 18d is disposed on the power supply line 102 side.

The current source 12d includes an N-channel MOSFET first transistor M1, a second transistor M2, and a fifth resistor R5. This current source 12d is known as a Nagata current mirror. The current source 12d generates currents I ₁ and I ₂ according to the size ratio of the first transistor M1 and the second transistor M2 and the resistance value of the fifth resistor R5.

The current mirror circuit 18d includes a thirteenth transistor M13 and a fourteenth transistor M14. The output circuit 30d is connected to the current mirror circuit 18 d, and an output transistor M0 to generate a first current _{I 1,} the reference current _{I REF} proportional to the second current _{I 2.} The configuration of the startup circuit 20d is the same as that of the startup circuit 20c in FIG.

The phase compensation capacitor C21 is connected to the gate of the first transistor M1. The starting circuit 20d supplies the first starting current I _S1 to the capacitor C21 and supplies the third starting current I _S3 to the current mirror circuit 18d (sink).

(Third Modification)
In the reference current source circuit 100a of FIG. 6, the current source 12a may be disposed on the power supply line 102 side, and the current mirror circuit 18a may be disposed on the ground line 104 side. In this case, the P channel SMOSFET may be replaced with an N channel MOSFET, and the NPN bipolar transistor may be replaced with a PNP bipolar transistor. In addition, the top and bottom of the activation circuit 20a may be reversed.

  In the reference current source circuit 100c of FIG. 14, the current source 12c may be disposed on the ground line 104 side and the current mirror circuit 18c may be disposed on the power supply line 102 side. In this case, the P-channel SMOSFET may be replaced with an N-channel MOSFET, and the N-channel MOSFET may be replaced with a P-channel MOSFET. In addition, the top and bottom of the activation circuit 20c may be reversed.

  In the reference current source circuit 100d of FIG. 15, the current source 12d may be disposed on the power supply line 102 side, and the current mirror circuit 18d may be disposed on the ground line 104 side. In this case, the P-channel SMOSFET may be replaced with an N-channel MOSFET, and the N-channel MOSFET may be replaced with a P-channel MOSFET. In addition, the top and bottom of the activation circuit 20d may be reversed.

(Fourth modification)
In the circuit described so far, the second starting current I _S2 is supplied to the analog circuit 202 through the same path as the reference current I _REF , but the present invention is not limited to this. The second start-up current I _S2 may be supplied to a node that can become a start-up bottleneck among the internal nodes of the analog circuit 202. For example, when the analog circuit 202 includes a large capacitor for phase compensation, the capacitor is charged with the second starting current I _S2 from the starting start time t0, and after the start of the constant current circuit 10, the reference current I _REF is used. Biasing of other circuit elements of the analog circuit 202 may be started.

(5th modification)
FIG. 16 is a circuit diagram of the reference current source circuit 100v according to the fifth modification. In the reference current source circuit 100b of FIG. 8, a peak occurs in the current I _REF + I _S2 supplied to the analog circuit 202 as shown in FIG. 4, and the oscillation threshold value may be exceeded. In the reference current source circuit 100v of FIG. 16, a modification for suppressing the peak of the current I _REF + I _S2 will be described.

The reference current source circuit 100v is different from the reference current source circuit 100b in FIG. 8 in the configuration of the activation circuit 20v. The startup circuit 20v includes a first current mirror circuit 34, a second current mirror circuit 36, and a peak cut transistor M15 in addition to the startup circuit 20b of FIG. The current I _{M8b of the} transistor M8b is turned back by the first current mirror circuit 34. The peak cut transistor M15 is the same type as the current mirror circuit 18b, that is, a P-channel MOSFET, and is connected to the transistor M6 so as to form a current mirror circuit. The transistor M15 generates a current I _M15 that is proportional to the reference current I _REF .

The input of the second current mirror circuit 36 is connected to the output of the first current mirror circuit 34. The transistor M15 is connected to the output of the first current mirror circuit 34. The input current _{I A} of the second current mirror circuit 36, the output current _{I B} of the first current mirror circuit 34, the difference between the current _{I C} of the transistor M15.
I _A = I _B -I _C
I _B is proportional to the current I _M8b of the transistor M8b, and the current I _{C of the} transistor M15 is proportional to the reference current I _REF . The second current mirror circuit 36 copies the current I _A and generates a second starting current I _S2 . The second starting current I _S2 is equal to the design value of the reference current I _REF .

The above is the configuration of the reference current source circuit 100v. FIG. 17A is an operation waveform diagram of the reference current source circuit 100v of FIG. 16, and FIG. 17B is an operation waveform diagram of a comparative technique in which the transistor M15 is omitted. This comparison technique is equivalent to the reference current source circuit 100b of FIG. First, the comparison technique will be described with reference to FIG. The power is turned on at time t = 10 μs, and the second starting current I _{S2 of} 450 nA is supplied to the analog circuit 202.

From around time t = 53 μs, the reference current I _REF starts to increase toward the design value (450 nA). When the reference current I _REF rises to near the design value, a current flows through the transistor M9, and the second starting current I _S2 becomes zero. In a section where the reference current I _REF increases, the current I _REF + I _S2 supplied to the analog circuit 202 has a peak, and the operation of the analog circuit 202 may become unstable.

Next, the operation of the reference current source circuit 100v of FIG. 16 will be described with reference to FIG. When the reference current I _REF starts to flow, a current I _C proportional thereto flows to the transistor M15. When the current _{I C} is increased, the input current _{I A} of the second current mirror circuit 36 is reduced, the second starting current _{I S2} decreases. That is, as the reference current I _REF increases, the second starting current I _S2 decreases, and the total I _REF + I _S2 is kept constant.

According to the reference current source circuit 100v of FIG. 16, the current I _REF + I _S2 supplied to the analog circuit 202 can be kept at the design value (450 nA) from the start to the steady state.

(Sixth Modification)
FIG. 18 is a circuit diagram of the reference current source circuit 100w according to the sixth modification. The reference current source circuit 100w can be understood as a combination of the constant current circuit 10d in FIG. 15 and the constant current circuit 10v in FIG. In FIG. 18, the first current mirror circuit 34 may be a bipolar transistor.

FIG. 19 is an operation waveform diagram of the reference current source circuit 100w of FIG. The design values of the reference current I _REF and the second starting current I _S2 are equal to 5.2 μA. The circuit starts at time t = 10 μs. The operation of the activation circuit 20v is the same as that of FIG. According to the reference current source circuit 100w of FIG. 18, the analog circuit 202 can be started up in a short time while suppressing the peak of the current I _REF + I _S2 supplied to the analog circuit 202.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 100 ... Reference current source circuit, 102 ... Power supply line, 104 ... Ground line, 200 ... Semiconductor integrated circuit, 202 ... Analog circuit, 10 ... Constant current circuit, 12 ... Current source, 13 ... First current mirror, 14 ... First Transistor 16... Second transistor 18... Current mirror circuit 19... Second current mirror 20... Start circuit 22... Current mirror 24. ... output circuit, 32 ... current mirror, 40 ... shutdown circuit, C1 ... capacitor, M0 ... output transistor, M1 ... first transistor, M2 ... second transistor, M3 ... third transistor, M4 ... fourth transistor, M5 ... first 5 transistors, M6 ... 6th transistor, M7 ... 7th transistor, M8 ... 8th transistor, 9 ... 9th transistor, M10 ... 10th transistor, M11 ... 11th transistor, M12 ... 12th transistor, M13 ... 13th transistor, R1 ... 1st resistor, R2 ... 2nd resistor, R3 ... 3rd resistor, R4 ... 4th resistance, R5 ... 5th resistance.

Claims (11)

A reference current source circuit for supplying a reference current to an analog circuit,
A constant current circuit for generating the reference current;
A start-up circuit that supplies a first start-up current to the constant current circuit and a second start-up current to the analog circuit at the time of start-up of the reference current source circuit;
A reference current source circuit comprising:   The reference current source circuit according to claim 1, wherein the startup circuit supplies the second startup current to the analog circuit through the same path as the reference current.   The reference current source circuit according to claim 2, wherein the startup circuit changes a current amount of the second startup current with time.   The startup circuit immediately after startup, wherein the second startup current is set to a first current amount, and thereafter, the second startup current is set to a second current amount smaller than the first current amount. The reference current source circuit described.   The said starting circuit switches the amount of the said 2nd starting current based on the comparison result of the voltage of one node inside the said constant current circuit, and a threshold voltage. Reference current source circuit. The constant current circuit is:
A current source provided on the first line side which is one of the power line and the ground line;
A current mirror circuit provided on the second line side which is the other of the power supply line and the ground line;
Including
The reference current source circuit further includes a phase compensation capacitor connected to the constant current circuit,
6. The reference current source circuit according to claim 1, wherein the starting circuit supplies the first starting current to a connection node between the capacitor and the constant current circuit.   The said starting circuit switches the amount of said 2nd starting current based on the comparison result of the voltage of the connection node of the said capacitor and the said constant current circuit, and a threshold voltage. Reference current source circuit. The starting circuit is
A resistor and a first transistor provided in series between the power supply line and the ground line;
A second transistor connected to form a current mirror with the first transistor;
A third transistor connected to form a current mirror with the first transistor;
A current flowing through the second transistor is supplied to the capacitor as the first starting current, and a current flowing through the third transistor is supplied to the analog circuit as the second starting current. The reference current source circuit according to claim 6 or 7. The starting circuit is
A fourth transistor connected to form a current mirror with the first transistor;
A switch provided in series with the fourth transistor;
A control circuit for switching on and off of the switch based on a comparison result between a voltage of a connection node between the capacitor and the constant current circuit and a threshold voltage;
Further including
9. The reference current source circuit according to claim 8, wherein the second starting current is a sum of currents flowing through the third transistor and the fourth transistor. The starting circuit is
A resistor and a first transistor provided in series between the power supply line and the ground line;
A second transistor connected to form a current mirror with the first transistor;
A third transistor connected to form a current mirror with the first transistor;
A first current mirror circuit for turning back a current flowing through the third transistor;
A fourth transistor that generates a current proportional to the reference current and supplies the current to the output of the first current mirror circuit;
A second current mirror circuit whose input is connected to the output of the first current mirror circuit;
A current flowing through the second transistor is supplied to the constant current circuit as the first starting current, and an output current of the second current mirror circuit is supplied to the analog circuit as the second starting current. The reference current source circuit according to claim 1. A reference current source circuit according to any one of claims 1 to 10,
An analog circuit to which a reference current generated by the reference current source circuit is supplied;
A semiconductor integrated circuit comprising:

Images