CN113220064A

CN113220064A - Quick-start linear voltage stabilizer and electronic circuit

Info

Publication number: CN113220064A
Application number: CN202110585599.XA
Authority: CN
Inventors: 杜睿; 朱从义
Original assignee: Suzhou Huatai Electronics Co Ltd
Current assignee: Suzhou Huatai Electronics Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2021-08-06
Anticipated expiration: 2041-05-27
Also published as: CN113220064B

Abstract

The invention discloses a quick-start linear voltage stabilizer and an electronic circuit, wherein the linear voltage stabilizer circuit comprises a trimming signal generator, a band gap reference circuit and a voltage stabilizer main body circuit, wherein the trimming signal generator is used for generating trimming signals; the band-gap reference circuit is connected with the trimming signal generator and used for receiving the trimming signal, calibrating the reference voltage according to the trimming signal and outputting the reference voltage; the main circuit of the voltage stabilizer is directly connected with the band-gap reference circuit and used for generating target output voltage according to the reference voltage and supplying the target output voltage to a load. According to the invention, the trimming function is integrated in the bandgap reference circuit, and a cascade trimming buffer stage is not required to be inserted, so that the whole power-on establishing time of the voltage stabilizer can be obviously shortened, and the power consumption of a system is reduced.

Description

Quick-start linear voltage stabilizer and electronic circuit

Technical Field

The invention belongs to the technical field of voltage stabilizer systems, and particularly relates to a quick-start linear voltage stabilizer and an electronic circuit.

Background

In the structure of a conventional linear regulator system with an output voltage Trimming function, as shown in fig. 1, in order to improve the accuracy of an output voltage, a Trimming Buffer (Trimming Buffer) needs to be inserted between a Bandgap reference (Bandgap) and a main circuit of the regulator, so as to form a cascade structure of three-stage functional modules. The Trim-Code Generation module, as a binary Trim Code Generation circuit, typically generates a binary Trim Code (Trim Code) through a Fuse and a corresponding readout circuit, which is used as an input control signal of a Trim Buffer (Trim Buffer) to change its output reference voltage, thereby adjusting the output voltage of a Regulator (Regulator).

The system needs to be started in a grading way, namely, a band gap reference (Bandgap) output is established firstly, a Trim Buffer (Trim Buffer) reference voltage output is established, and finally, the state of the voltage stabilizer is established. Therefore, the total system delay is the sum of the delays of circuits in all stages in the three-stage cascade system. In the scheme, for the band gap reference circuit, the series voltage type band gap reference with a conventional structure is shown in fig. 2, and the core part of the band gap circuit is realized by adopting two paths of substrate PNP tubes, so that the band gap circuit is compatible with a CMOS (complementary metal oxide semiconductor) process of a standard P-type substrate. The expression of the output voltage is as follows:

wherein

N is the ratio of the sizes of two PNP transistors, and usually 8 or 5 is taken to match the layout (PNP with small size is a unit transistor, and PNP with large size is composed of 8 or 5 repeated unit transistors). At this time due to V_BEIs a negative temperature coefficient, V_TThe voltage output of 0 temperature coefficient can be realized by adjusting the proportion of the resistors R and Rt for positive temperature coefficient. Series bandgap references suffer from problems, above all with difficulty in achieving reference voltages below 1V; in addition, due to the fact that the layout is usually considered to be matched, the zero temperature coefficient voltage output can only be realized by adjusting the ratio of R and Rt, which means that if the output voltage is adjusted by trimming R or Rt, the temperature coefficient of the output voltage is influenced at the same time. Therefore, in a linear regulator system using a series voltage type bandgap reference, the output voltage of the regulator is usually modified by modifying the output voltage of a Trim Buffer (Trim Buffer).

In a conventional Trimming Buffer (Trimming Buffer) unit structure, as shown in fig. 3, the output voltage is adjusted by a closed-loop operational amplifier. The specific implementation mode is as follows: the resistance value of the adjustable resistor Rv in fig. 3 is changed by the modification code, so as to adjust the output voltage V_OUT。

However, the large signal process of the buffer stage output voltage built up over time is accelerated mainly by increasing the Slew-rate of the dominant pole, which usually requires increasing the bias current of the corresponding branch, often contradict the requirement of low power consumption of the system. And the small signal process of the buffer stage output voltage built up over time is represented as follows:

where τ is a time constant, τ is 1/(2 π × GBW), and GBW is the loop unity gain bandwidth. The larger the loop unity gain bandwidth, the shorter the settling time of the buffer stage. Accordingly, increasing the bandwidth also generally means an increase in the quiescent current of the operational amplifier, which is also contradictory to the system requirements for low power consumption.

In summary, under the condition that the power consumption of the system is limited, the conventional scheme inserts the Trimming buffer in a mode which can significantly increase the starting time of the whole system.

Therefore, how to provide a linear regulator capable of being started quickly and having an output voltage trimming function is a problem to be solved urgently.

Disclosure of Invention

The present invention is directed to a fast start-up linear regulator and an electronic circuit thereof, so as to overcome the disadvantages of the prior art.

In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps: a fast start linear regulator, comprising:

a trimming signal generator for generating a trimming signal;

the band-gap reference circuit is connected with the trimming signal generator and used for directly receiving the trimming signal, calibrating the reference voltage according to the trimming signal and outputting the reference voltage to the main circuit of the voltage stabilizer;

and the voltage stabilizer main body circuit is connected with the band gap reference circuit and used for generating target output voltage according to the reference voltage and supplying the target output voltage to a load.

In a preferred embodiment, the trimming signal generator is a binary trimming code generating circuit including a fuse and a sensing circuit.

In a preferred embodiment, the bandgap reference circuit is a parallel current type bandgap reference circuit integrated with trimming function.

In a preferred embodiment, the bandgap reference circuit comprises:

the emitter of the first PNP tube is connected with a first resistor Rt in series, the first resistor Rt is connected with a second resistor Reb with the other end grounded, and the base electrode and the collector of the first PNP tube are grounded;

the emitter of the second PNP tube is connected in parallel with a third resistor Reb between the grounded emitter and the base, and the base and the collector of the second PNP tube are grounded; the first resistor Rt, the second resistor Reb and the third resistor Reb are resistors of the same type, the temperature coefficients of the resistors are the same, and high matching is achieved through a layout technique; the effective emitter area of the second PNP transistor is typically several times (typically 8 times or 5 times) that of the first PNP transistor;

the non-inverting input end of the operational amplifier circuit is connected with the first resistor Rt and forms a first node A, and the inverting input end of the operational amplifier circuit is connected with the emitter of the second PNP tube and forms a second node B;

one end of the adjustable resistor string is grounded, and the total resistance value of the adjustable resistor string is adjustable under the control of the adjusting signal;

starting a tube M0 connected with the operational amplifier circuit and used for inputting current to the second node B and a bias circuit of the operational amplifier circuit so as to enable the band gap to be separated from a stable state;

the grid electrodes of the at least four parallel current source field effect transistors are connected with the output end of the operational amplifier circuit, and the drain electrodes of the four field effect transistors are respectively connected with the second node B, the first node A, the other end of the adjustable resistor string and the base electrode of the starting tube M0;

and the degenerate point elimination circuit comprises a hysteresis comparator, wherein the output end of the hysteresis comparator is connected with the input end of the operational amplifier circuit and is used for inputting current to the second node B and the bias circuit of the operational amplifier circuit and pulling up the second node B and keeping away from a third degenerate point.

In a preferred embodiment, the reference voltage V generated by the bandgap reference circuit_REFThe calculation formula of (2) is as follows:

wherein M is R_TRIMThe relative size of a PMOS current source device of a branch where the resistor is located, N is the relative size of the PMOS current source device of the branch where the first PNP tube and the second PNP tube are located, Vbe refers to the voltage between the emitter and the base of the second PNP tube, delta Vbe is the difference value of the voltages between the emitter and the base of the second PNP tube and the first PNP tube respectively, and R is the voltage of the first PNP tube and the second PNP tube_TRIMThe total resistance value of the resistor string can be modified and adjusted for the output branch, Rt is the resistance value of the first resistor, R_ebIs the resistance of the second resistor or the third resistor, and R_TRIM、R_ebAnd R_tAll of the same type of resistors, have identical temperature characteristics and achieve high matching through integrated circuit layout techniques

In a preferred embodiment, the hysteresis comparator is composed of at least 5 fet units.

In a preferred embodiment, the trimmable resistor string comprises a first-stage resistor string, a second-stage resistor string, a third-stage resistor string and a fourth-stage resistor string which are connected in series, the first-stage resistor string is composed of 1 resistor with the resistance value of R, the second-stage resistor string is composed of 2 parallel resistors with the resistance value of R, the third-stage resistor string is composed of 4 parallel resistors with the resistance value of R, the fourth-stage resistor string is composed of 8 parallel resistors with the resistance value of R, and each stage of resistors is connected with a control switch in parallel.

In a preferred embodiment, the bandgap reference circuit accelerates the start-up process of the voltage regulator by inputting current to a bias circuit of the main circuit of the voltage regulator.

In a preferred embodiment, the voltage regulator uses Miller compensation to achieve a stable voltage output.

The embodiment of the invention provides an electronic circuit which comprises the quick-start linear voltage regulator.

Compared with the prior art, the invention has the beneficial effects that:

1. compared with the conventional output adjustable linear voltage stabilizer scheme, the structure does not need to insert a cascade type adjustment buffer stage, can obviously shorten the whole power-on establishing time of the voltage stabilizer, and simultaneously reduces the power consumption of a system.

2. The invention adopts the parallel current type band gap reference, and proposes to increase the starting speed of the band gap reference and the starting speed of the later-stage voltage stabilizer by adding the starting circuit and eliminate a third degeneracy point existing in the parallel band gap reference.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional linear regulator system with output voltage trimming function;

FIG. 2 is a schematic diagram of a prior art series voltage bandgap reference circuit;

FIG. 3 is a schematic diagram of a conventional trimming buffer;

FIG. 4 is a schematic diagram of a linear regulator according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a bandgap reference circuit in accordance with one embodiment of the present invention;

FIG. 6 is a schematic diagram of an operational amplifier circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a bandgap reference circuit in accordance with one embodiment of the present invention;

FIG. 8 is a schematic diagram of a trimmable resistor string according to one embodiment of the present invention;

fig. 9 is a schematic diagram of a voltage regulator according to an embodiment of the present invention.

Detailed Description

The present invention will be more fully understood from the following detailed description, which should be read in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which can be embodied in various forms. Therefore, specific functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed embodiment.

According to the quick-start linear voltage regulator and the electronic circuit disclosed by the invention, the trimming function is integrated in the bandgap reference circuit, compared with the conventional output trimming linear voltage regulator scheme, the structure does not need to insert a cascade trimming buffer stage, the whole power-on establishing time of the voltage regulator can be obviously shortened, and the system power consumption is reduced.

As shown in fig. 4, a fast-start linear regulator disclosed in the embodiment of the present invention includes a trimming signal generator, a bandgap reference circuit, and a regulator main circuit, wherein the trimming signal generator is configured to generate a trimming signal; the band-gap reference circuit is connected with the trimming signal generator and used for directly receiving the trimming signal and generating reference voltage to the main circuit of the voltage stabilizer according to the trimming signal; the main circuit of the voltage stabilizer is connected with the band-gap reference circuit and used for generating target output voltage according to the reference voltage and supplying the target output voltage to a load. The trimming target voltage can be a terminal output voltage of the main circuit of the linear voltage regulator, and the offset accumulated in the whole cascade system (namely the whole main circuit of the linear voltage regulator) can be eliminated through trimming.

Specifically, in the present embodiment, the trimming signal generator is a binary trimming Code generating circuit, and generates a binary trimming Code (Trim Code) through a Fuse (Fuse) and a corresponding readout circuit.

In this embodiment, as shown in fig. 5, the bandgap reference circuit is a parallel current type bandgap reference circuit with an integrated trimming function, and specifically includes: the PNP circuit comprises a first PNP tube, a second PNP tube, an operational amplifier circuit OPA _ BG, a trimmable resistor string, a starting tube M0, at least four field effect tubes connected in parallel and a degeneracy point elimination circuit, wherein an emitting electrode of the first PNP tube is connected with a first resistor Rt in series, the first resistor Rt is connected with a second resistor Reb of which the other end is grounded, and a base electrode and a collector electrode of the first PNP tube are grounded. The emitter of the second PNP tube is connected in parallel with a third resistor Reb between the grounded emitter and the grounded base, and the base and the collector of the second PNP tube are both grounded. The non-inverting input terminal INP of the operational amplifier circuit is connected with the first resistor Rt and forms a first node A, and the inverting input terminal INN is connected with the emitter of the second PNP tube and forms a second node B. In this embodiment, as shown in fig. 6, a specific circuit of the operational amplifier circuit is shown in the figure, wherein an input signal (Start) of an input end of the operational amplifier circuit is connected to an output end of the hysteresis comparator in the degeneracy point elimination circuit. When the input signal of the Start end is at a high level, current is injected into a bias circuit of the operational amplifier circuit through the magnetic field effect tube Mst, and the starting of the band gap reference circuit is achieved in an auxiliary mode.

Adjustable resistor string R_TRIMOne end of the resistor is grounded, and the on-off of a switch connected with each level of resistor in parallel is controlled through the binary trimming code, so that the short circuit and the access of each level of resistor are realized, and the R is changed_TRIMThe total resistance value of the band-gap reference circuit can realize that the output voltage (namely the reference voltage) of the band-gap reference circuit is adjustable. In this embodiment, as shown in FIG. 8, the resistor string R can be modified_TRIMIncluding the first level resistance string, the second level resistance string, the third level resistance string and the fourth level resistance string of establishing ties, wherein, the first level resistance string comprises 1 resistance that the resistance is R, and the second level resistance string comprises 2 resistances that are R's parallelly connected resistance, and the third level resistance string comprises 4 resistances that are R's parallelly connected resistance, and the fourth level resistance string comprises 8 resistances that are R's parallelly connected resistance, and the parallelly connected control switch of every level resistance. Regulating R by a set of switches connected in parallel with each stage of resistance_TRIMThe accurate adjustment of the target voltage of the voltage stabilizer can be realized.

The starting pipe M0 is connected with the operational amplifier circuit and used for inputting current to the second node B and the bias circuit of the operational amplifier circuit, so that the band gap is separated from the steady state. Specifically, when the bias circuit current is 0, the gate of the Start tube M0 is pulled low by the pull-down resistor, the drain of the Start tube M0 is pulled high (the drain is a Start-up0 signal, and the high level is active), and the Start tube M0 can be used to inject current into the bias circuit of the bandgap core (i.e., the second node B) and the operational amplifier circuit (OPA _ BG), so as to help the bandgap reference circuit to be out of the zero steady state; when the start-up process is over, the bias current pulls the gate of the start-up tube M0 high, turning off the start-up tube M0.

And the grid electrodes of the at least four parallel current source field effect transistors are connected with the output end OUT of the operational amplifier circuit, the source electrodes of the at least four parallel current source field effect transistors are connected in parallel, and the drain electrodes of the four field effect transistors are respectively connected with the second node B, the first node A, the other end of the adjustable resistor string and the base electrode of the starting transistor M0.

In this embodiment, referring to fig. 7, the degenerated point elimination circuit specifically includes a hysteresis comparator, an output end of the hysteresis comparator is connected to an input end of the operational amplifier circuit, and is configured to input a current to the second node B and the bias circuit of the operational amplifier circuit, so as to pull up the second node B and move away from the third degenerated point. Specifically, since the parallel current type bandgap reference circuit has a third degeneracy problem, that is, there is a stable interval, at this time, the bandgap reference circuit is in an abnormal operating state: when the PNP tube of the band-gap core has no current, the total current of the two branches of the band-gap core (namely the first node A and the second node B) only flows through two R_ebAnd (4) resistance. To help the circuit break away from the third degeneracy point, a degeneracy point elimination circuit is introduced, in which a hysteresis comparator is employed to avoid oscillations around the roll-over point. When the voltage of the first node a is lower than a PN junction voltage, the hysteresis comparator outputs a high level (the input Start-up signal of the operational amplifier circuit is active high) to continuously inject current into the bandgap core (i.e., the second node B) and the bias circuit in the operational amplifier circuit, so as to pull up the bandgap core and keep away from the third degeneracy point. In this embodiment, the hysteresis comparator main body is composed of 5-tube units, and the current mirror load is designed to adjust the mirror ratio through positive feedback to introduce unilateral imbalance, thereby implementing the hysteresis comparison function. The hysteretic comparator outputs a Start-up high signal when the bandgap core node voltage (the first node a) is below a BE junction voltage drop (Vbe _ ref)The series of operations, which simultaneously inject current into the operational amplifier bias circuit through the Start input end connected to the operational amplifier circuit (OPA _ BG), simultaneously inject current into the bandgap core (i.e. the second node B) through the field effect transistor Mst2 in fig. 7, and directly pull up the output voltage of the bandgap reference circuit through the field effect transistor Mst1, not only speed up the Start-up process of the bandgap reference circuit itself, but also quickly pull up the output voltage V of the bandgap reference circuit_REFAnd the establishment of the later-stage voltage stabilizer in the power-on process is accelerated. After the starting process is finished, the voltage of the first node a is higher than the Vbe _ ref voltage plus the hysteresis voltage of the hysteresis comparator, the Start-up signal at the input end of the operational amplifier circuit drops to a low level, and the corresponding starting tubes Mst1 and Mst2 are turned off.

In this embodiment, the output voltage (i.e., the output reference voltage) V of the bandgap reference voltage_REFThe calculation formula of (2) is as follows:

wherein M is R_TRIMThe relative size of the PMOS current source device of the branch where the resistor is located, and N is the relative size of the PMOS current source device of the branch where the first PNP tube and the second PNP tube are located. Vbe refers to the voltage between the emitter and the base of the second PNP transistor, and Δ Vbe is the difference between the voltages of the emitter and the base of the second PNP transistor and the first PNP transistor, respectively. R_TRIMThe total resistance value of the resistor string can be modified and adjusted for the output branch, Rt is the resistance value of the first resistor, R_ebIs the resistance of the second resistor or the third resistor, and R_TRIM、R_ebAnd R_tThe resistors are all of the same type, have the same temperature characteristic and are highly matched through integrated circuit layout skills.

When the output voltage has been adjusted by design to achieve an approximately zero temperature coefficient as above, then R is further adjusted at this point_TRIMThe resistor is used for accurately adjusting the output voltage value of the system, and the output temperature characteristic cannot be influenced. From the above analysis, it can be seen that the parallel Bandgap reference circuit (Bandgap) actually has one more resistance parameter variable than the series voltage Bandgap reference circuit (Bandgap)(the resistance parameter of the parallel band gap reference circuit is that the parallel band gap is R_TRIMRt, Reb, and the series bandgap is Rt, R) for adjusting temperature coefficient, and is very suitable for realizing direct trimming_TRIMVoltage trimming is achieved while maintaining the Temperature Coefficient (TC) constant.

In this embodiment, a specific implementation structure of the main circuit of the voltage regulator is shown in fig. 9, and the start transistor M0 and the degeneracy point elimination circuit of the bandgap reference circuit can both participate in the accelerated start-up process by pulling up the start transistor Mst in fig. 9 during the power-up process, and injecting current into the bias circuit of the main circuit of the voltage regulator. The circuit realizes stable voltage output through a conventional Miller compensation technology, and if other main circuit structures of the voltage stabilizer are adopted, the starting process can be accelerated by quickly injecting extra current into a bias circuit of the main circuit of the voltage stabilizer in the same way.

An electronic circuit disclosed in an embodiment of the present invention includes the above-mentioned fast-start linear regulator, and the structure of the linear regulator refers to the above description, which is not described herein again.

The aspects, embodiments, features and examples of the present invention should be considered as illustrative in all respects and not intended to be limiting of the invention, the scope of which is defined only by the claims. Other embodiments, modifications, and uses will be apparent to those skilled in the art without departing from the spirit and scope of the claimed invention.

The use of headings and chapters in this disclosure is not meant to limit the disclosure; each section may apply to any aspect, embodiment, or feature of the disclosure.

Claims

1. A fast start linear regulator, comprising:

a trimming signal generator for generating a trimming signal;

2. The fast start linear regulator of claim 1, wherein: the trimming signal generator is a binary trimming code generating circuit which comprises a fuse and a reading circuit.

3. The fast start linear regulator of claim 1, wherein: the band-gap reference circuit is a parallel current type band-gap reference circuit integrating the trimming function.

4. A fast start linear regulator according to claim 3, wherein: the bandgap reference circuit includes:

the emitter of the second PNP tube is connected in parallel with a third resistor Reb between the grounded emitter and the base, and the base and the collector of the second PNP tube are grounded;

5. The fast start linear regulator of claim 4, wherein: the reference voltage V generated by the band-gap reference circuit_REFThe calculation formula of (2) is as follows:

wherein M is R_TRIMThe relative size of a PMOS current source device of a branch where the resistor is located, N is the relative size of the PMOS current source device of the branch where the first PNP tube and the second PNP tube are located, Vbe refers to the voltage between the emitter and the base of the second PNP tube, delta Vbe is the difference value of the voltages between the emitter and the base of the second PNP tube and the first PNP tube respectively, and R is the voltage of the first PNP tube and the second PNP tube_TRIMThe total resistance value of the resistor string can be modified and adjusted for the output branch, Rt is the resistance value of the first resistor, R_ebIs the resistance of the second resistor or the third resistor, and R_TRIM、R_ebAnd R_tThe resistors are all of the same type, have the same temperature characteristic and are highly matched through integrated circuit layout skills.

6. The fast start linear regulator of claim 4, wherein: the hysteresis comparator is composed of at least 5 field effect tube units.

7. The fast start linear regulator of claim 4, wherein: the trimmable resistor string comprises a first-stage resistor string, a second-stage resistor string, a third-stage resistor string and a fourth-stage resistor string which are connected in series, wherein the first-stage resistor string is composed of 1 resistor with the resistance value of R, the second-stage resistor string is composed of 2 parallel resistors with the resistance value of R, the third-stage resistor string is composed of 4 parallel resistors with the resistance value of R, the fourth-stage resistor string is composed of 8 parallel resistors with the resistance value of R, and each stage of resistors are connected with a control switch in parallel.

8. The fast start linear regulator of claim 4, wherein: the band-gap reference circuit inputs current to a bias circuit of the main body circuit of the voltage stabilizer, so that the starting process of the main body circuit of the voltage stabilizer is accelerated.

9. The fast start linear regulator of claim 1, wherein: the main circuit of the voltage stabilizer adopts the Miller compensation technology to realize stable voltage output.

10. An electronic circuit, characterized by: a fast start linear regulator comprising a regulator according to any of claims 1 to 9.