CN114253337A - Band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions - Google Patents
Band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions Download PDFInfo
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- CN114253337A CN114253337A CN202111488303.9A CN202111488303A CN114253337A CN 114253337 A CN114253337 A CN 114253337A CN 202111488303 A CN202111488303 A CN 202111488303A CN 114253337 A CN114253337 A CN 114253337A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
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Abstract
The invention discloses a band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions. The main circuit converts the power supply voltage signal into stable band gap reference voltage and outputs the stable band gap reference voltage to the over-temperature protection circuit; the over-temperature protection circuit receives a band-gap reference voltage signal output by the main circuit, has hysteresis characteristics and can prevent the over-temperature protection circuit from being repeatedly turned on and off at a temperature critical point due to micro-disturbance; the resistance trimming protection circuit of the band-gap reference can prevent the circuit from being broken down by trimming high-voltage signals.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions.
Background
The most common way for circuitry to interact with the real analog world is to employ analog-to-digital converters (ADCs), sensors, or other Application Specific Integrated Circuits (ASICs). The premise for accurate measurement is that a reference voltage is required that does not fluctuate with the system and should not be affected by conditions such as input voltage or ambient temperature. The bandgap reference provides a stable voltage against which other circuit blocks measure and compare with the required accuracy.
The basic principle of the bandgap reference circuit is to add two voltages with opposite temperature coefficients by proper weight to obtain a reference voltage with zero temperature coefficient.
However, due to the influence of factors such as manufacturing process, when the temperature of the bandgap reference voltage circuit exceeds the tolerable range of the circuit, the characteristics of transistors in the circuit may change, thereby affecting the output and making the circuit not meet the precision requirement. Moreover, with the continuous increase of the scale of the integrated circuit and the integration of some high-power devices, the power consumption of the whole integrated circuit system is increased sharply, and an over-temperature protection function is generally required to be provided for thermal shutdown, so that the circuit system is prevented from being damaged due to over-high temperature when the load current exceeds the normal working range.
Compared with the traditional over-temperature protection circuit which needs to construct a complex high-precision reference voltage circuit and a comparator circuit, the over-temperature protection circuit has the advantages of simple structure, small occupied area and the like, and has the temperature hysteresis function to avoid the harm caused by adiabatic oscillation. The invention integrates the protection function of the trimming circuit and prevents the high-voltage trimming signal from damaging the device.
Disclosure of Invention
The invention aims to provide a band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions, which receives a band-gap reference voltage signal output by a main circuit, has temperature hysteresis characteristics and can prevent the over-temperature protection circuit from being repeatedly turned on and off at a temperature critical point due to micro disturbance; the resistance trimming protection circuit of the band-gap reference can prevent the circuit from being broken down by trimming high-voltage signals, has the advantages of simple structure, small occupied area and the like, and is convenient for system integration.
The invention adopts the following technical scheme:
the invention provides a band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions. The output end of the band-gap reference main circuit module is connected with the over-temperature protection circuit, and the band-gap reference output voltage and the power supply voltage jointly provide bias for the over-temperature circuit; the resistance trimming protection circuit is connected with the trimming circuit in series and is connected with the output of the band-gap reference.
The main circuit comprises a clamping operational amplifier module, a band-gap reference core circuit and a band-gap reference biasing module.
The clamping operational amplifier module comprises a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), a sixth transistor (Q6), a seventh transistor (Q7), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5) and a first capacitor (C1). The first transistor (Q1), the second transistor (Q2), the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5), the first resistor (R1), the second resistor (R2), the third resistor (R3) and the fourth resistor (R4) form a first stage of the clamping operational amplifier; the sixth transistor (Q6), the seventh transistor (Q7) and the fifth resistor (R5) form a second stage of the clamping operational amplifier. The specific device connection mode is as follows: the base of the first transistor (Q1) is connected with a bias Voltage (VBIAS), the emitter is connected with a power Voltage (VCC), and the collector is connected with the first ends of the first resistor (R1) and the second resistor (R2); the base electrode of the second transistor (Q2) is used as the inverting input end of the clamping operational amplifier, the emitter electrode is connected with the second end of the first resistor (R1), and the collector electrode is connected with the collector electrode of the fourth transistor (Q4); the base electrode of the third transistor (Q3) is the non-inverting input end of the clamping operational amplifier, the emitter electrode is connected with the second end of the second resistor (R2), and the collector electrode is connected with the collector electrode of the fifth transistor (Q5); the fourth transistor (Q4) is in a diode connection mode, the base electrode is connected with the base electrode of the fifth transistor (Q5), and the emitter electrode is connected with the first end of the third resistor (R3); the collector of the fifth transistor (Q5) is used as the output end of the first stage of the clamping operational amplifier and is connected with the base of the seventh transistor (Q7), and the emitter is connected with the first end of the fourth resistor (R4); the base electrode of the sixth transistor (Q6) is connected with the bias Voltage (VBIAS), the emitter electrode of the sixth transistor is connected with the power Voltage (VCC), and the collector electrode of the sixth transistor is connected with the collector electrode of the seventh transistor (Q7); the base electrode of the seventh transistor (Q7) is connected with the output end of the first stage of the clamping operational amplifier, the emitter electrode is connected with the first end of the fifth resistor (R5), and the collector electrode is used as the output of the clamping operational amplifier and is connected with the base electrode of the eighth transistor (Q8); second ends of the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) are all grounded.
The band-gap reference core circuit comprises a ninth transistor (Q9), a tenth transistor (Q10), a sixth resistor (R6), an eighth resistor (R8), a ninth resistor (R9), an eleventh resistor (R11), a twelfth resistor (R12) and a thirteenth resistor (R13). The specific device connection mode is as follows: the base electrode of the ninth transistor (Q9) is connected with the base electrode of the tenth transistor (Q10) and is used as a band gap reference output end (Vref), the collector electrode is connected with the non-inverting input end of the clamping operational amplifier module, and the emitter electrode is connected with the first end of the thirteenth resistor (R13); the collector of the tenth transistor (Q10) is connected with the inverting input end of the clamping operational amplifier module, and the emitter of the tenth transistor is connected with the first end of the ninth resistor (R9); the first end of the sixth resistor (R6) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the collector of the ninth transistor (Q9); the first end of the eighth resistor (R8) is connected with the first end of the sixth resistor (R6), and the second end is connected with the collector of the tenth transistor (Q10); the first end of the ninth resistor (R9) is connected with the emitter of the tenth transistor (Q10), and the second end is connected with the first end of the twelfth resistor (R12); the first end of the eleventh resistor (R11) is connected with the second end of the thirteenth resistor (R13), and the second end is grounded; the first end of the twelfth resistor (R12) is connected with the second end of the ninth resistor (R9), and the second end is connected with the first end of the thirteenth resistor (R13); the thirteenth resistor (R13) has a first terminal connected to the emitter of the ninth transistor (Q9) and a second terminal connected to a first terminal of the eleventh resistor (R11).
The band-gap reference bias module comprises an eighth transistor (Q8), a twelfth transistor (Q12), a seventh resistor (R7) and a tenth resistor (R10). The specific device connection mode is as follows: the base electrode of the eighth transistor (Q8) is connected with the output of the clamping operational amplifier, the collector electrode is connected with the power Voltage (VCC), and the emitter electrode is connected with the first end of the seventh resistor (R7); the first end of the seventh resistor (R7) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the bases of the ninth transistor (Q9) and the tenth transistor (Q10); the twelfth transistor (Q12) is in a diode connection mode, the base electrode and the collector electrode are connected with the second end of the seventh resistor (R7), and the emitter electrode is connected with the first end of the tenth resistor (R10); the tenth resistor (R10) has a first terminal connected to the emitter of the twelfth transistor (Q12) and a second terminal connected to ground.
The over-temperature protection circuit comprises a fourteenth transistor (Q14), a fifteenth transistor (Q15), a sixteenth transistor (Q16), a seventeenth transistor (Q17), an eighteenth transistor (Q18), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), an eighteenth resistor (R18), a nineteenth resistor (R19) and a twentieth resistor (R20). The specific device connection mode is as follows: the base electrode of the fourteenth transistor (Q14) is connected with the band gap reference output (Vref), the collector electrode is connected with the power Voltage (VCC), and the emitter electrode is connected with the first end of the fourteenth resistor (R14); the first end of the fourteenth resistor (R14) is connected with the emitter of the fourteenth transistor (Q14), and the second end of the fourteenth resistor (R16) is connected with the first end of the sixteenth resistor; the first end of the sixteenth resistor (R16) is connected with the second end of the fourteenth resistor (R14), and the second end is grounded; the fifteenth transistor (Q15) is in a diode connection mode, the base electrode and the collector electrode are connected with the collector electrode of the eighteenth transistor (Q18), and the emitter electrode is connected with the first end of the fifteenth resistor (R15); the first end of the fifteenth resistor (R15) is connected with the emitter of the fifteenth transistor (Q15), and the second end of the fifteenth resistor (R16) is connected with the first end of the sixteenth resistor (R16); the seventeenth resistor (R17) has a first terminal connected to the emitter of the eighth transistor (Q8) and a second terminal connected to the collector of the sixteenth transistor (Q16); the base of the sixteenth transistor (Q16) is connected with the second end of the fifteenth resistor (R15), the collector of the sixteenth transistor is connected with the second end of the seventeenth resistor (R17), and the emitter of the sixteenth transistor is grounded; the base electrode of the seventeenth transistor (Q17) is connected with the collector electrode of the sixteenth transistor (Q16), the collector electrode of the seventeenth transistor is connected with the collector electrode of the eighteenth transistor (Q18), and the emitter electrode of the seventeenth transistor is grounded; the first end of the eighteenth resistor (R18) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the collector of the eighteenth transistor (Q18); the eighteenth transistor (Q18) is in a diode connection mode, the base electrode and the collector electrode are connected with the second end of the eighteenth resistor (R18), and the emitter electrode is connected with the first end of the nineteenth resistor (R19); the first end of the nineteenth resistor (R19) is connected with the emitter of the eighteenth transistor (Q18), and the second end of the nineteenth resistor (R20) is connected with the first end of the twentieth resistor; the first end of the twentieth resistor (R20) is connected with the second end of the nineteenth resistor (R19), the second end is grounded, and the first end of the twentieth resistor (R20) is the output (V _ ot) of the over-temperature protection circuit.
The resistor trimming protection circuit comprises an eleventh transistor (Q11), a thirteenth transistor (Q13), a first trimming resistor (rfuse1) and a second trimming resistor (rfuse 2). The specific device connection mode is as follows: the eleventh transistor (Q11) is in a diode connection mode, the base electrode and the collector electrode are connected with the first end of the second trimming resistor (rfuse2), and the emitter electrode is connected with the base electrode of the ninth transistor (Q9); the thirteenth transistor (Q13) is in a diode connection mode, the base electrode and the collector electrode are connected with the first end of the first trimming resistor (rfuse1) and the first end of the twelfth resistor (Q12), and the emitter electrode is connected with the base electrode of the tenth transistor (Q10); the first end of the first trimming resistor (rfuse1) is connected with the collector of the thirteenth transistor (Q13), and the second end is connected with the first end of the second trimming resistor (rfuse 2); the first end of the second trimming resistor (rfuse2) is connected with the second end of the first trimming resistor (rfuse1) and the second end of the twelfth resistor (R12), and the second end is connected with the first end of the eleventh resistor (R11).
Drawings
Fig. 1 is an overall circuit diagram of a bandgap reference circuit integrated with over-temperature protection and resistance trimming protection functions according to the present invention;
FIG. 2 is a simulation result of the bandgap reference voltage versus temperature relationship of the bandgap reference circuit of the present invention;
FIG. 3 is a simulation result of the power supply rejection ratio of the bandgap reference circuit of the present invention;
FIG. 4 is a simulation result of over-temperature protection of the bandgap reference circuit of the present invention;
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The invention provides a band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions, and the whole circuit diagram is shown in figure 1 and comprises a band-gap reference main circuit, an over-temperature protection circuit and a resistance trimming protection circuit. The main circuit converts the power supply voltage signal into stable band gap reference voltage and outputs the stable band gap reference voltage to the over-temperature protection circuit; the over-temperature protection circuit receives a band-gap reference voltage signal output by the main circuit, has hysteresis characteristics and can prevent the over-temperature protection circuit from being repeatedly turned on and off at a temperature critical point due to micro-disturbance; the resistance trimming protection circuit of the band-gap reference can prevent the circuit from being broken down by trimming high-voltage signals.
Immediately after the circuit is powered on, the bias circuit provides proper bias potential for each part, namely bias Voltage (VBIAS) is enough to enable a Q6 tube to be conducted, E point potential is high after a Q6 tube is conducted, and F point is low potential when the circuit is powered on, so that a Q8 tube is conducted, current is injected into a branch where R6, R7 and R8 are located from the F point, the bandgap reference circuit is enabled to break away from degenerated bias points, and starting is completed.
Q8, R7, Q12 and R10 form a bias circuit of the bandgap reference core part, wherein a Q8 tube provides bias current required by normal operation for a branch where R6, R7 and R8 are located, and total voltage drop on R10 and Q12 provides base bias voltage for Q9 and Q10 tubes, so that the bandgap reference core part can normally operate.
Because rfuse1 and rfuse2 are trimming resistors, high voltage is connected at a point P or Q during trimming, and the emitter-base potential of the Q9 and Q10 tubes can be clamped at about 0.7V by utilizing the characteristic that the forward conduction voltage drop of the Q11 and Q13 tubes connected in a diode mode is very low, so that high voltage breakdown caused by trimming of the Q9 and Q10 tubes is prevented.
The clamping operational amplifier is mainly used for ensuring that voltage drops on the resistors R6 and R8 are equal, so that currents flowing through collectors of the transistors Q9 and Q10 are equal. The reason why the PNP transistors Q2 and Q3 are used as the differential input transistors is that the PNP transistors generate smaller noise than the NPN transistors, and the resistors R1 and R2 can increase the linear range of the input and output voltages. The two-stage operational amplifier has strong amplification capability enough to ensure that the fluctuation of the voltage of the clamping point is restrained. Assuming that the voltage at the point a is increased, the emitter voltage of the Q8 tube is increased, and the base voltages of the Q9 and Q10 tubes are increased according to the analysis of the instantaneous polarity method. If the point a resistance is RA and the point B resistance is RB, RA ≈ R6 and RB ≈ R8, and by selecting R6 ═ R8, RA ═ RB can be obtained.
The differential mode gain from the base of the Q9 tube to the point A is
Ad9=-gm6RA
The differential mode gain from the base of the Q10 tube to the point B is
The increase of the base voltages of the Q9 and Q10 tubes enables the reduction amount of the voltage at the point A to be far larger than that at the point B, and the reduction amount of the voltage at the point A is offset with the increase amount of the voltage at the point A, namely the negative feedback gain formed by the Q8, the Q9 and the R7 is larger than the positive feedback gain formed by the Q8, the Q10 and the R7, so that the voltage at the point A is stabilized, and the voltage at the point A is ensured to be equal to the voltage at the point B.
The differential input transistors Q2 and Q3, the current mirror loads Q4 and Q5 and the resistors R1, R2, R3 and R4 form a first stage of a clamping operational amplifier, the transistors Q7 and R5 form a second stage of the clamping operational amplifier, and the transistors Q1 and Q6 respectively provide bias current for the two stages of the operational amplifier. The clamping operational amplifier forces the voltage drops on R6 and R8 to be equal, thereby ensuring that the currents flowing through the collectors of the two transistors Q9 and Q10 are equal. A voltage which is proportional to the temperature is obtained on R9 through the difference between the base-emitter voltages of Q9 and Q10, the current which flows through R11 is twice of the current which flows through R9, therefore, the voltage drop on R11 is also proportional to the temperature, the base-emitter voltage of Q9 is a negative temperature coefficient, and the ratio of R11 to R9 is adjusted to obtain the reference voltage Vref with zero temperature coefficient. Setting the area ratio of Q9 to Q10 tubes to be 1:12 so as to ensure that
Ra=R9+(rfuse1||R12)
Rb=R11+(rfuse2||R13)
At this time, Δ VBECan be expressed as:
in the formula IC9、IC10、IS9、IS10Collector currents and saturation currents of Q9 and Q11, respectively, and therefore the voltage across resistor Ra:
since the current flowing through resistor Rb is twice the current flowing through resistor Ra, the voltage drop over Rb can be:
in the formulaWhich is the voltage drop over the resistor Ra,for the voltage drop across resistor Rb, the reference voltage Vref is thus obtained as:
the simulation result of the relation between the band-gap reference voltage and the temperature of the band-gap reference circuit of the invention is shown in figure 2, and the temperature coefficient TC value is as follows:
the simulation result of the power supply rejection ratio of the bandgap reference circuit of the invention is shown in fig. 3, the PSRR is 60dB at low frequency, and when the frequency is greater than 10kHz, the power supply voltage rejection ratio will also drop due to the gain drop of the negative feedback loop at high frequency, but the circuit has good input fluctuation rejection capability within the required working frequency bandwidth of the circuit.
The over-temperature protection circuit designed by the invention has the following functions: when the temperature of the chip is increased to 170 ℃ from low temperature, the over-temperature protection circuit outputs a control signal (V _ ot) to output a high level, so that the chip stops working; when the temperature of the chip is reduced to below 130 ℃ from high temperature, the output control signal (V _ ot) of the over-temperature protection circuit jumps to low level, and the chip recovers to work normally. The temperature hysteresis range of 40 ℃ is set, so that the over-temperature protection circuit is prevented from being repeatedly turned on and off at the temperature critical point due to micro disturbance.
The principle of over-temperature protection: the output control signal (V _ ot) of the protection circuit is changed by switching the circuit at the abrupt change point of the protection temperature by using the negative temperature coefficient characteristic of the base-emitter voltage of the transistors Q14 and Q16.
When the chip normally works, the voltage drop on the R16 is not enough to enable the Q16 tube to be conducted, the base current of the Q17 tube is small, the F point voltage provides base bias voltage for the Q17 tube through the resistor R17, the emitter area of the Q17 tube is large, the Q17 tube pulls down the N point voltage (close to the ground potential) after being conducted, the N point voltage is not enough to enable the Q15 and the R15 and two branches of the Q18, the R19 and the R20 to be opened, the overvoltage control signal (V _ ot) is at the low potential, and the chip normally works.
When the temperature is increased from low to 170 ℃, the ratio of R16 to R14 is set so that the emitter junction starting voltage V of the Q16 tubeBE16(ON)And the pressure drop V over R17R17Are equal.
At this time, the transistor Q16 is turned on, and the voltage at the point P is pulled down (close to the ground potential), so that the transistor Q17 is turned off, and the voltage at the point N is restored to the high potential, so that the over-temperature output control signal (V _ ot) is at the high level (650 mV).
When the temperature is reduced from high to 130 ℃, the values of R16 and R14 and R15 are set so that V isBE16(ON)And the pressure drop V over R17R17The phase of the two phases is equal to each other,
at this time, the transistor Q16 is turned off, and the transistor Q17 is turned on again, so that the voltage at the point N is pulled down again to be close to the ground potential, and the over-temperature output control signal (V _ ot) is restored to the low level (10 mV).
The simulation result of the over-temperature protection of the bandgap reference circuit of the present invention is shown in fig. 4. The reason why the hysteresis is generated is: when the temperature is increased from low to 170 ℃, only the current on the resistor R14 is generated due to the current flowing through the resistor R16; when the temperature is reduced from high temperature to 170 ℃, the current flowing through the resistor R16 is the current on the resistor R14 (equal to the previous temperature increased from low temperature to 170 ℃) and the current on the resistor R15. The voltage drops generated on the resistor R16 are not equal in the two cases, namely, when the temperature is reduced to 170 ℃ from high temperature, the voltage drop on the resistor R16 is larger, at the moment, the Q16 tube still keeps on, and the Q15 tube is required to be recovered to the off state when the temperature is continuously reduced to 130 ℃.
Claims (4)
1. The utility model provides an integrated excess temperature protection and resistance trimming protect function's band gap reference circuit which characterized in that: the band-gap reference circuit comprises a band-gap reference main body circuit, an over-temperature protection circuit and a resistance trimming protection circuit. The output end of the band-gap reference main circuit module is connected with the over-temperature protection circuit, and the band-gap reference output voltage and the power supply voltage jointly provide bias for the over-temperature circuit; the resistance trimming protection circuit is connected with the trimming circuit in series and is connected with the output of the band-gap reference.
2. The integrated over-temperature protection and resistance trimming protection bandgap reference circuit of claim 1, wherein: the main circuit comprises a clamping operational amplifier module, a band-gap reference core circuit and a band-gap reference biasing module.
The clamping operational amplifier module comprises a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), a sixth transistor (Q6), a seventh transistor (Q7), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5) and a first capacitor (C1). The first transistor (Q1), the second transistor (Q2), the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5), the first resistor (R1), the second resistor (R2), the third resistor (R3) and the fourth resistor (R4) form a first stage of the clamping operational amplifier; the sixth transistor (Q6), the seventh transistor (Q7) and the fifth resistor (R5) form a second stage of the clamping operational amplifier. The specific device connection mode is as follows: the base of the first transistor (Q1) is connected with a bias Voltage (VBIAS), the emitter is connected with a power Voltage (VCC), and the collector is connected with the first ends of the first resistor (R1) and the second resistor (R2); the base electrode of the second transistor (Q2) is used as the inverting input end of the clamping operational amplifier, the emitter electrode is connected with the second end of the first resistor (R1), and the collector electrode is connected with the collector electrode of the fourth transistor (Q4); the base electrode of the third transistor (Q3) is the non-inverting input end of the clamping operational amplifier, the emitter electrode is connected with the second end of the second resistor (R2), and the collector electrode is connected with the collector electrode of the fifth transistor (Q5); the fourth transistor (Q4) is in a diode connection mode, the base electrode is connected with the base electrode of the fifth transistor (Q5), and the emitter electrode is connected with the first end of the third resistor (R3); the collector of the fifth transistor (Q5) is used as the output end of the first stage of the clamping operational amplifier and is connected with the base of the seventh transistor (Q7), and the emitter is connected with the first end of the fourth resistor (R4); the base electrode of the sixth transistor (Q6) is connected with the bias Voltage (VBIAS), the emitter electrode of the sixth transistor is connected with the power Voltage (VCC), and the collector electrode of the sixth transistor is connected with the collector electrode of the seventh transistor (Q7); the base electrode of the seventh transistor (Q7) is connected with the output end of the first stage of the clamping operational amplifier, the emitter electrode is connected with the first end of the fifth resistor (R5), and the collector electrode is used as the output of the clamping operational amplifier and is connected with the base electrode of the eighth transistor (Q8); second ends of the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) are all grounded.
The band-gap reference core circuit comprises a ninth transistor (Q9), a tenth transistor (Q10), a sixth resistor (R6), an eighth resistor (R8), a ninth resistor (R9), an eleventh resistor (R11), a twelfth resistor (R12) and a thirteenth resistor (R13). The specific device connection mode is as follows: the base electrode of the ninth transistor (Q9) is connected with the base electrode of the tenth transistor (Q10) and is used as a band gap reference output end (Vref), the collector electrode is connected with the non-inverting input end of the clamping operational amplifier module, and the emitter electrode is connected with the first end of the thirteenth resistor (R13); the collector of the tenth transistor (Q10) is connected with the inverting input end of the clamping operational amplifier module, and the emitter of the tenth transistor is connected with the first end of the ninth resistor (R9); the first end of the sixth resistor (R6) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the collector of the ninth transistor (Q9); the first end of the eighth resistor (R8) is connected with the first end of the sixth resistor (R6), and the second end is connected with the collector of the tenth transistor (Q10); the first end of the ninth resistor (R9) is connected with the emitter of the tenth transistor (Q10), and the second end is connected with the first end of the twelfth resistor (R12); the first end of the eleventh resistor (R11) is connected with the second end of the thirteenth resistor (R13), and the second end is grounded; the first end of the twelfth resistor (R12) is connected with the second end of the ninth resistor (R9), and the second end is connected with the first end of the thirteenth resistor (R13); the thirteenth resistor (R13) has a first terminal connected to the emitter of the ninth transistor (Q9) and a second terminal connected to a first terminal of the eleventh resistor (R11).
The band-gap reference bias module comprises an eighth transistor (Q8), a twelfth transistor (Q12), a seventh resistor (R7) and a tenth resistor (R10). The specific device connection mode is as follows: the base electrode of the eighth transistor (Q8) is connected with the output of the clamping operational amplifier, the collector electrode is connected with the power Voltage (VCC), and the emitter electrode is connected with the first end of the seventh resistor (R7); the first end of the seventh resistor (R7) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the bases of the ninth transistor (Q9) and the tenth transistor (Q10); the twelfth transistor (Q12) is in a diode connection mode, the base electrode and the collector electrode are connected with the second end of the seventh resistor (R7), and the emitter electrode is connected with the first end of the tenth resistor (R10); the tenth resistor (R10) has a first terminal connected to the emitter of the twelfth transistor (Q12) and a second terminal connected to ground.
3. The integrated over-temperature protection and resistance trimming protection bandgap reference circuit of claim 1, wherein: the over-temperature protection circuit comprises a fourteenth transistor (Q14), a fifteenth transistor (Q15), a sixteenth transistor (Q16), a seventeenth transistor (Q17), an eighteenth transistor (Q18), a fourteenth resistor (R14), a fifteenth resistor (R15), a sixteenth resistor (R16), a seventeenth resistor (R17), an eighteenth resistor (R18), a nineteenth resistor (R19) and a twentieth resistor (R20). The specific device connection mode is as follows: the base electrode of the fourteenth transistor (Q14) is connected with the band gap reference output (Vref), the collector electrode is connected with the power Voltage (VCC), and the emitter electrode is connected with the first end of the fourteenth resistor (R14); the first end of the fourteenth resistor (R14) is connected with the emitter of the fourteenth transistor (Q14), and the second end of the fourteenth resistor (R16) is connected with the first end of the sixteenth resistor; the first end of the sixteenth resistor (R16) is connected with the second end of the fourteenth resistor (R14), and the second end is grounded; the fifteenth transistor (Q15) is in a diode connection mode, the base electrode and the collector electrode are connected with the collector electrode of the eighteenth transistor (Q18), and the emitter electrode is connected with the first end of the fifteenth resistor (R15); the first end of the fifteenth resistor (R15) is connected with the emitter of the fifteenth transistor (Q15), and the second end of the fifteenth resistor (R16) is connected with the first end of the sixteenth resistor (R16); the seventeenth resistor (R17) has a first terminal connected to the emitter of the eighth transistor (Q8) and a second terminal connected to the collector of the sixteenth transistor (Q16); the base of the sixteenth transistor (Q16) is connected with the second end of the fifteenth resistor (R15), the collector of the sixteenth transistor is connected with the second end of the seventeenth resistor (R17), and the emitter of the sixteenth transistor is grounded; the base electrode of the seventeenth transistor (Q17) is connected with the collector electrode of the sixteenth transistor (Q16), the collector electrode of the seventeenth transistor is connected with the collector electrode of the eighteenth transistor (Q18), and the emitter electrode of the seventeenth transistor is grounded; the first end of the eighteenth resistor (R18) is connected with the emitter of the eighth transistor (Q8), and the second end is connected with the collector of the eighteenth transistor (Q18); the eighteenth transistor (Q18) is in a diode connection mode, the base electrode and the collector electrode are connected with the second end of the eighteenth resistor (R18), and the emitter electrode is connected with the first end of the nineteenth resistor (R19); the first end of the nineteenth resistor (R19) is connected with the emitter of the eighteenth transistor (Q18), and the second end of the nineteenth resistor (R20) is connected with the first end of the twentieth resistor; the first end of the twentieth resistor (R20) is connected with the second end of the nineteenth resistor (R19), the second end is grounded, and the first end of the twentieth resistor (R20) is the output (V _ ot) of the over-temperature protection circuit.
4. The integrated over-temperature protection and resistance trimming protection bandgap reference circuit of claim 1, wherein: the resistor trimming protection circuit comprises an eleventh transistor (Q11), a thirteenth transistor (Q13), a first trimming resistor (rfuse1) and a second trimming resistor (rfuse 2). The specific device connection mode is as follows: the eleventh transistor (Q11) is in a diode connection mode, the base electrode and the collector electrode are connected with the first end of the second trimming resistor (rfuse2), and the emitter electrode is connected with the base electrode of the ninth transistor (Q9); the thirteenth transistor (Q13) is in a diode connection mode, the base electrode and the collector electrode are connected with the first end of the first trimming resistor (rfuse1) and the first end of the twelfth resistor (Q12), and the emitter electrode is connected with the base electrode of the tenth transistor (Q10); the first end of the first trimming resistor (rfuse1) is connected with the collector of the thirteenth transistor (Q13), and the second end is connected with the first end of the second trimming resistor (rfuse 2); the first end of the second trimming resistor (rfuse2) is connected with the second end of the first trimming resistor (rfuse1) and the second end of the twelfth resistor (R12), and the second end is connected with the first end of the eleventh resistor (R11).
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