CN117707272B - Gain-enhanced reference voltage source and application thereof - Google Patents
Gain-enhanced reference voltage source and application thereof Download PDFInfo
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- CN117707272B CN117707272B CN202410162829.5A CN202410162829A CN117707272B CN 117707272 B CN117707272 B CN 117707272B CN 202410162829 A CN202410162829 A CN 202410162829A CN 117707272 B CN117707272 B CN 117707272B
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Abstract
The invention discloses a gain-enhanced reference voltage source and application thereof, wherein the gain-enhanced reference voltage source comprises a starting circuit, a bias circuit and a reference voltage circuit, wherein the starting circuit is used for controlling the bias circuit to normally work when the bias circuit is electrified; the bias circuit is used for providing bias voltage; the reference voltage circuit is used for generating and outputting a reference voltage. According to the invention, the influence of power supply voltage change on current can be restrained by adding the common grid tube, the branch circuit generating the diode forward conduction voltage V BE is reduced, and the layout area is reduced.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and relates to a gain-enhanced reference voltage source and application thereof.
Background
In an analog circuit, in order to operate the circuit under a desired condition, an active device needs to satisfy an operation state using a bias circuit. The self-bias technique uses a feedback loop formed by a linear current mirror and a nonlinear current mirror to generate a current that is insensitive to the supply voltage. The self-bias technique can significantly reduce the sensitivity of the current to the supply voltage relative to the resistive bias technique. The current generated by the self-bias technique still produces a significant power supply dependence due to non-ideal factors such as MOS channel modulation effects and short channel effects.
In addition, analog circuits often require a reference voltage that is independent of voltage, temperature, and process. Bandgap references based on "bandgap" technology are commonly used. The bandgap reference band is derived from the bandgap of silicon and has a value of about 1.2V. The reference voltage is formed by compounding a diode forward conduction voltage drop V BE and a thermal voltage V T in a certain mode, the diode forward conduction voltage drop V BE has a negative temperature coefficient, the thermal voltage V T has a positive temperature coefficient, and if the compounding mode is proper, the reference voltage irrelevant to the temperature can be generated.
Fig. 2 is a conventional Δv BE/R-based reference voltage source structure, which includes a start-up circuit, a bias circuit and a reference voltage circuit, wherein PMOS transistors M30 and M40 form a linear current mirror of the bias circuit, NMOS transistors M10 and M20 form a nonlinear current mirror of the bias circuit, source voltages of M10 and M20 are equal, currents flowing through transistors Q10 and Q20 are equal, but since transistor Q10 is a transistor, transistor Q20 is actually formed by connecting n transistors Q200 (not shown) in parallel, the current flowing through each transistor Q200 is related to voltage V BE, then each time a current through Q200 is 1/n of the current through Q10, resulting in a difference between the emitter voltages of Q10 and Q20, the emitter voltage of Q10 being equal to the source voltage of M20, the emitter voltage of both transistors Q10, Q20 being at a voltage difference av BE, this voltage difference av BE being applied to resistor R10, resulting in a current av BE/R being copied to R20 by current mirror M50, a positive temperature coefficient voltage associated with av BE being generated at R20, the temperature coefficient of which can be adjusted by adjusting the ratio of R10 to R20; on the other hand, the emitter voltage V BE of the transistor Q30 is a negative temperature coefficient voltage, and the positive temperature coefficient voltage associated with Δv BE is added to the negative temperature coefficient voltage associated with V BE to generate a reference voltage independent of temperature. The starting circuit consists of PMOS tubes M60 and M70 and a capacitor C10, in the process of powering on the circuit, current is filled into the grid electrodes of the M10 and M20, the grid voltages of the M10 and M20 are raised to enable the nonlinear current mirror to work, the grid voltage of the M40 is pulled down after the grid voltage of the M20 is raised, the circuit is separated from a degenerate working point, the voltage of an upper polar plate of the C10 is raised after the circuit works normally, the M60 and M70 are turned off, and the starting circuit is turned off, so that the power consumption of the circuit is reduced.
However, due to non-ideal factors of the MOS tube, the sensitivity of the bias circuit to the power supply voltage is greatly improved, the output impedance of the MOS tube can be increased by a common-source common-gate current mirror, but the output voltage swing is sacrificed, and the scheme is generated.
Disclosure of Invention
The invention aims to provide a reference voltage source with enhanced gain and application thereof, wherein the influence of power supply voltage change on current can be restrained by adding a common grid tube, the branch circuit generating diode forward conduction voltage V BE is reduced, and the layout area is reduced.
In order to achieve the above object, the solution of the present invention is:
a gain enhanced reference voltage source comprising a start-up circuit, a bias circuit and a reference voltage circuit, wherein the start-up circuit is used for providing a start-up current; the bias circuit is used for providing bias voltage; the reference voltage circuit is used for generating and outputting a reference voltage.
The starting circuit comprises a seventh PMOS tube, an eighth PMOS tube and a first capacitor, wherein the source electrode of the seventh PMOS tube is connected with a power supply voltage, the drain electrode of the seventh PMOS tube is respectively connected with the grid electrode of the eighth PMOS tube and the positive electrode of the first capacitor, and the negative electrode of the first capacitor is grounded; the grid electrode of the seventh PMOS tube is respectively connected to the bias circuit and the reference voltage circuit so as to make the current proportional; the source electrode of the eighth PMOS tube is connected with the power supply voltage, and the drain electrode of the eighth PMOS tube is connected to the bias circuit to control the bias circuit to work normally when the power is on.
The bias circuit comprises a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a first resistor, a first triode and a second triode, wherein the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected with power supply voltages, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube and is connected to the starting circuit; the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the collector electrode of the first triode, and the source electrode of the second NMOS tube is connected with the collector electrode of the second triode through a first resistor; the base of the first triode is connected with the base of the second triode and grounded, and the collector of the first triode is connected with the collector of the second triode and grounded.
The first triode adopts a single triode, and the second triode comprises a plurality of triodes which are connected in parallel.
The reference voltage circuit comprises a sixth NMOS tube, a fifth PMOS tube and a second resistor, wherein the source electrode of the fifth PMOS tube is connected with a power supply voltage, and the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the sixth NMOS tube are connected and used for mirroring the output current of the bias circuit; the grid electrode of the sixth NMOS tube is connected with a starting circuit; the source electrode of the sixth NMOS tube is connected with one end of the second resistor and used for outputting reference voltage, and the other end of the second resistor is connected to the bias circuit.
A chip circuit comprising a gain enhanced reference voltage source as hereinbefore described.
By adopting the scheme, compared with the prior art, the invention increases the common-gate tube M6 to form a negative feedback loop, increases the output impedance of the current mirror, improves the gain of the current mirror, reduces the dependence of bias current on power supply voltage, reduces the dependence of a voltage reference source VREF on power supply voltage, reduces one triode Q30 in layout realization, and saves layout area.
Drawings
FIG. 1 is a circuit diagram of the present invention;
fig. 2 is a conventional circuit diagram.
Detailed Description
The technical scheme and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the invention provides a gain-enhanced reference voltage source, which comprises a starting circuit, a bias circuit and a reference voltage circuit, wherein the bias circuit comprises a linear current mirror, a nonlinear current mirror, a common base triode and a first resistor, the common base triode is used for generating negative temperature coefficient voltage, the first resistor is used for generating negative temperature coefficient current, the starting circuit is used for controlling the bias circuit to be separated from a degenerate working point when the circuit is powered on, and the starting circuit is turned off and does not work any more after the circuit works normally; the reference voltage circuit comprises a current mirror, a common grid tube and a second resistor.
The starting circuit comprises PMOS tubes M7 and M8 and a capacitor C1, when the power is on, the starting circuit works, and as the voltage at two ends of the capacitor C1 cannot be suddenly changed, at the moment, the grid electrode of the M8 is low voltage, the M8 is opened, so that the grid electrode of the M6 is lifted; after the circuit is stable, M7 is opened to charge the capacitor C1 to the power supply voltage, M8 is closed, and the starting circuit is closed.
The bias circuit comprises NMOS tubes M1 and M2, PMOS tubes M3 and M4, PNP triodes Q1 and Q2 and a resistor R1, and is used for generating bias current which is equal to |V1-V2|/R1, wherein V1 is VBE (voltage between a base electrode and an emitter electrode) of Q1, V2 is VBE of Q2, and R1 refers to the resistance value of the resistor R1; the linear current mirrors formed by M3 and M4 ensure that two paths of currents flowing through the triodes Q1 and Q2 are equal, the nonlinear current mirrors formed by M1 and M2 and the linear current mirrors formed by M3 and M4 form a feedback loop together, so that the bias circuit works at a stable bias point.
The reference voltage circuit comprises an NMOS tube M6, a PMOS tube M5 and a resistor R2, wherein M5 provides direct current bias points for linear current mirrors M3, M4 and M7, and the current flowing through M5 is equal to equal-proportion replication of the currents of M3 and M4; the negative feedback of the source electrode is introduced into the M6, so that the influence of the power supply voltage on the current is reduced, the current of the M5 flows through R2 and R1 to generate a voltage, and the generated voltage is irrelevant to the temperature by adjusting the proportion of R2 and R1.
When the invention works, the sources of the common grid tubes M6 and M6 are connected with R2, the grid electrode of the M6 is connected with the drain electrode of the M1, the current flowing through the M6 is the current of the linear current mirror M5, and the drain electrode of the M1 is fixed at the voltage R2 by the M6 and added with the grid source voltage V GS of the M6 from the direct current angle, so that the influence of channel modulation effect is reduced. From the perspective of small signals, when the gate voltages of the linear current mirrors M3, M4, M5 and M7 are affected by the unstable power supply voltage, the current flowing through M6 flows through R2 and R1, so that the voltages have opposite polarities, and the voltages are fed back to the gate of the linear current mirror M5 through the common gate tube M6, so that the change of the gate voltages is restrained, and the sensitivity of the current to the change of the power supply voltage is reduced. In addition, the current flowing through R1 and R2 produces a positive temperature coefficient voltage related to DeltaVBE, and the negative temperature coefficient voltage added to the Q2 emitter voltage produces a temperature independent voltage V REF which is also less affected by the change of the supply voltage due to the action of the common gate M6, and compared with the traditional reference circuit, the use of the triode Q3 is saved, and the area is saved.
The embodiment of the invention also provides a chip circuit, which comprises the gain-enhanced reference voltage source.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the invention can be realized by adopting various computer languages, such as object-oriented programming language Java, an transliteration script language JavaScript and the like.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (4)
1. A gain enhanced reference voltage source, characterized by: the power-on circuit comprises a starting circuit, a bias circuit and a reference voltage circuit, wherein the starting circuit is used for controlling the bias circuit to work normally when the power-on circuit is powered on; the bias circuit is used for providing bias voltage; the reference voltage circuit is used for generating and outputting a reference voltage;
The reference voltage circuit comprises a sixth NMOS tube, a fifth PMOS tube and a second resistor, wherein the source electrode of the fifth PMOS tube is connected with a power supply voltage, and the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube and the drain electrode of the sixth NMOS tube are connected and used for mirroring the output current of the bias circuit; the grid electrode of the sixth NMOS tube is connected with a starting circuit; the source electrode of the sixth NMOS tube is connected with one end of the second resistor and is used for outputting reference voltage, and the other end of the second resistor is connected to the bias circuit;
The bias circuit comprises a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a first resistor, a first triode and a second triode, wherein the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube are connected with power supply voltages, and the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube; the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube and is connected to the starting circuit; the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the second NMOS tube; the source electrode of the first NMOS tube is connected with the collector electrode of the first triode, and the source electrode of the second NMOS tube is connected with the collector electrode of the second triode through a first resistor; the base of the first triode is connected with the base of the second triode and grounded, and the collector of the first triode is connected with the collector of the second triode and grounded.
2. A gain enhanced reference voltage source as claimed in claim 1, wherein: the starting circuit comprises a seventh PMOS tube, an eighth PMOS tube and a first capacitor, wherein the source electrode of the seventh PMOS tube is connected with a power supply voltage, the drain electrode of the seventh PMOS tube is respectively connected with the grid electrode of the eighth PMOS tube and the positive electrode of the first capacitor, and the negative electrode of the first capacitor is grounded; the grid electrode of the seventh PMOS tube is respectively connected to the bias circuit and the reference voltage circuit so as to make the current proportional; the source electrode of the eighth PMOS tube is connected with the power supply voltage, and the drain electrode of the eighth PMOS tube is connected to the bias circuit to control the bias circuit to work normally when the power is on.
3. A gain enhanced reference voltage source as claimed in claim 1, wherein: the first triode adopts a single triode, and the second triode comprises a plurality of triodes which are connected in parallel.
4. A chip circuit, characterized in that: a gain enhanced reference voltage source as claimed in any one of claims 1-3 is included in the chip circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410162829.5A CN117707272B (en) | 2024-02-05 | 2024-02-05 | Gain-enhanced reference voltage source and application thereof |
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| CN202410162829.5A CN117707272B (en) | 2024-02-05 | 2024-02-05 | Gain-enhanced reference voltage source and application thereof |
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| CN117707272B true CN117707272B (en) | 2024-04-19 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980097A (en) * | 2010-09-30 | 2011-02-23 | 浙江大学 | Low-voltage reference source with low flicker noise and high power-supply suppression |
| CN103970169A (en) * | 2014-05-28 | 2014-08-06 | 电子科技大学 | High-precision current source circuit with high power supply rejection ratio |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN109491433A (en) * | 2018-11-19 | 2019-03-19 | 成都微光集电科技有限公司 | A kind of reference voltage source circuit structure suitable for imaging sensor |
| CN112987836A (en) * | 2021-02-09 | 2021-06-18 | 无锡英迪芯微电子科技股份有限公司 | High-performance band-gap reference circuit |
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- 2024-02-05 CN CN202410162829.5A patent/CN117707272B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980097A (en) * | 2010-09-30 | 2011-02-23 | 浙江大学 | Low-voltage reference source with low flicker noise and high power-supply suppression |
| CN103970169A (en) * | 2014-05-28 | 2014-08-06 | 电子科技大学 | High-precision current source circuit with high power supply rejection ratio |
| CN106959723A (en) * | 2017-05-18 | 2017-07-18 | 东南大学 | A kind of bandgap voltage reference of wide input range high PSRR |
| CN109491433A (en) * | 2018-11-19 | 2019-03-19 | 成都微光集电科技有限公司 | A kind of reference voltage source circuit structure suitable for imaging sensor |
| CN112987836A (en) * | 2021-02-09 | 2021-06-18 | 无锡英迪芯微电子科技股份有限公司 | High-performance band-gap reference circuit |
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