CN112987836A - High-performance band-gap reference circuit - Google Patents

High-performance band-gap reference circuit Download PDF

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Publication number
CN112987836A
CN112987836A CN202110177683.8A CN202110177683A CN112987836A CN 112987836 A CN112987836 A CN 112987836A CN 202110177683 A CN202110177683 A CN 202110177683A CN 112987836 A CN112987836 A CN 112987836A
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triode
resistor
branch
mirror image
nmos
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CN112987836B (en
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李响
董渊
蔡胜凯
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Wuxi Indie Microelectronics Technology Co Ltd
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Wuxi Indie Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Abstract

The invention discloses a high-performance band-gap reference circuit, which relates to the field of electronic circuits, wherein in the band-gap reference circuit, a collector of a first triode is connected with a working voltage through a mirror image branch circuit, an emitter is grounded through a first resistor and a fourth adjustable resistor, a collector of a second triode which shares a base with the first triode is connected with the working voltage through the mirror image branch circuit, the emitter is connected with a common end of the first resistor and the fourth adjustable resistor, one end of a third resistor is connected with the working voltage through the mirror image branch circuit, the other end of the third resistor is connected with the base of the first triode, a current mirror realized through the mirror image branch circuit enables currents flowing through the first triode, the second triode and the third resistor to be equal, a negative feedback branch circuit is connected with a high end of a compensation capacitor and provides base currents and a stable output point of the first triode and the second triode, and the circuit has, Better temperature drift performance, higher loop bandwidth and transient response, and better working performance.

Description

High-performance band-gap reference circuit
Technical Field
The invention relates to the field of electronic circuits, in particular to a high-performance band-gap reference circuit.
Background
In integrated circuit applications, a bandgap reference circuit is a common circuit for generating a reference voltage, which utilizes a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient to be superimposed to generate a reference voltage which hardly changes with temperature. The reference voltage is referred to as a bandgap reference because it is related to the bandgap voltage of silicon, and the reference voltage generated by the bandgap reference is further used in LDO, DC-DC, ADC, temperature sensor, etc. Because the reference circuit belongs to the performance module started firstly in the power management module, the working performance of the bandgap reference circuit, such as power supply ripple rejection ratio (PSRR), temperature drift, starting voltage and the like, is higher.
Disclosure of Invention
The inventor proposes a high-performance bandgap reference circuit aiming at the above problems and technical requirements, and the technical scheme of the invention is as follows:
a high performance bandgap reference circuit in which:
the collector of the first triode is connected with a working voltage through a third mirror image branch and a first mirror image branch in sequence, the emitter is grounded through a first resistor and a fourth adjustable resistor, the collector of the second triode is connected with the working voltage through the fourth mirror image branch and a second mirror image branch in sequence, the emitter is connected with the common end of the first resistor and the fourth adjustable resistor, and the base of the first triode is connected with the base of the second triode; a first bias voltage with positive temperature coefficient is input into a current mirror formed by a first mirror image branch and a second mirror image branch, a second bias voltage with negative temperature coefficient is input into a current mirror formed by a third mirror image branch and a fourth mirror image branch, the first triode is formed by connecting a plurality of triodes with the same specification as the second triode in parallel, and the current flowing through the first triode is equal to the current flowing through the second triode;
one end of the third resistor is connected with the working voltage through a fifth mirror image branch, the other end of the third resistor is connected with the base electrode of the first triode, and the common end of the fifth mirror image branch and the third resistor outputs a reference voltage; the fifth mirror image branch and the first mirror image branch form a current mirror, and the current flowing through the first triode is equal to the current flowing through the third resistor;
the common ends of the second mirror image branch and the fourth mirror image branch are grounded through a compensation capacitor, the input end of the negative feedback branch is connected with the common ends of the second mirror image branch and the fourth mirror image branch, and the output end of the negative feedback branch is connected with the base electrode of the first triode.
The fourth adjustable resistor comprises a plurality of resistor trimming groups, one end of a series circuit formed by the plurality of resistor trimming groups is connected with an emitting electrode of the second triode, the other end of the series circuit is grounded, each resistor trimming group is formed by connecting an MOS (metal oxide semiconductor) tube and a fixed resistor in parallel, and the grid electrodes of the MOS tubes in the resistor trimming groups are respectively controlled by respective control signals.
The number of MOS tubes in each resistor trimming group from the emitter electrode of the second triode to the ground terminal is exponentially increased, and the resistance value of a fixed resistor in each resistor trimming group from the emitter electrode of the second triode to the ground terminal is exponentially increased; wherein, a plurality of MOS tubes in the same resistor trimming group are connected in parallel.
The technical scheme is that the negative feedback branch comprises a second resistor, a fifth NMOS tube, a third triode and a fifth adjustable resistor, the drain electrode of the fifth NMOS tube is connected with the working voltage through the second resistor, the emitter electrode of the fifth NMOS tube is connected with the collector electrode and the base electrode of the third triode, the emitter electrode of the third triode is grounded through the fifth adjustable resistor, the emitter electrode of the fifth NMOS tube is connected with the base electrode of the first triode, and the grid electrode of the fifth NMOS tube is connected with the common ends of the second mirror image branch and the fourth mirror image branch.
The minimum value of the working voltage of the band-gap reference circuit is the sum of VBE, VGS and VOV, wherein VBE is the voltage between the base electrode and the emitter electrode of the second triode, VGS is the voltage between the grid electrode and the source electrode of the fifth NMOS tube, and VOV is the total overdrive voltage of the second mirror image branch.
The further technical scheme is that a third mirror image branch and a fourth mirror image branch are respectively constructed based on NMOS tubes, and the specification of a fifth NMOS tube is the same as that of the NMOS tubes in the third mirror image branch and the fourth mirror image branch; the third triode is formed by connecting two triodes with the second triode in parallel, the specification of the fifth adjustable resistor is the same as that of the fourth adjustable resistor, the current flowing through the third triode is twice as large as the current flowing through the second triode, the current flowing through the fifth adjustable resistor is equal to the current flowing through the fourth adjustable resistor, and the voltage of the collector of the first triode, the voltage of the collector of the second triode and the voltage of the collector of the third triode are equal.
The further technical scheme is that the drain electrode of a first PMOS tube is connected with the source electrode of a third PMOS tube to form a first mirror image branch, the drain electrode of a second PMOS tube is connected with the source electrode of a fourth PMOS tube to form a second mirror image branch, the source electrode of a third NMOS tube is connected with the drain electrode of a first NMOS tube to form a third mirror image branch, and the source electrode of a fourth NMOS tube is connected with the drain electrode of the second NMOS tube to form a fourth mirror image branch;
the source electrode of the first NMOS tube is connected with the collector electrode of the first triode, the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the first PMOS tube is connected with the working voltage; the source electrode of the second NMOS tube is connected with the collector electrode of the second triode, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the second PMOS tube is connected with the working voltage;
the grid electrodes of the first NMOS tube and the second NMOS tube are connected and connected with the drain electrode of the fourth NMOS tube, and the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected and connected with a second bias voltage; the grid electrodes of the first PMOS tube and the second PMOS tube are connected with the drain electrode of the third PMOS tube, and the grid electrodes of the third PMOS tube and the fourth PMOS tube are connected with the first bias voltage;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube to form a fifth mirror image branch, the source electrode of the fifth PMOS tube is connected with the working voltage, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the sixth PMOS tube is connected with the third resistor, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the third PMOS tube.
The band-gap reference circuit further comprises a starting circuit, in the starting circuit, a source electrode of a second starting NMOS tube is grounded, a drain electrode of the second starting NMOS tube is connected with a working voltage through a starting resistor, a grid electrode of the second starting NMOS tube is connected with the drain electrode of the second starting NMOS tube and is connected with a grid electrode of a third starting NMOS tube, and a source electrode of the third starting NMOS tube is grounded, and a drain electrode of the third starting NMOS tube is connected with a common end of a first mirror image branch and a common end of a third mirror image branch; the source electrode of the first start NMOS tube is grounded, the drain electrode of the first start NMOS tube is connected with the drain electrode of the second start NMOS tube, and the grid electrode of the first start NMOS tube is connected with the fifth mirror image branch and the common end of the third resistor to obtain reference voltage.
The beneficial technical effects of the invention are as follows:
the application discloses band-gap reference circuit of high performance, negative feedback branch among this band-gap reference circuit provides the base current and the stable output point of first triode and second triode, makes whole electric current temperature drift better through each device parameter setting, and required operating voltage is less moreover, and third resistance and fourth adjustable resistance among this circuit structure separate the setting, consequently can reduce the influence of fourth adjustable resistance to circuit PSRR. In addition, the negative feedback branch only has one main pole, the output capacitor mounted at the reference voltage hardly influences the loop, and other poles are all located at the extremely high frequency, so that the value of the compensation capacitor can be smaller, the loop bandwidth is higher, the transient response is realized, and the band gap reference circuit has better performance.
Drawings
Fig. 1 is a circuit configuration diagram of a bandgap reference circuit disclosed in the present application.
Fig. 2 is another circuit configuration diagram of the bandgap reference circuit disclosed in the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses high-performance bandgap reference circuit, please refer to fig. 1, in the bandgap reference circuit, a collector of a first triode Q1 is connected to a working voltage VDD sequentially through a third mirror image branch K3 and a first mirror image branch K1, and an emitter is grounded through a first resistor R1 and a fourth adjustable resistor R4. The collector of the second triode Q2 is connected with the working voltage VDD through the fourth mirror image branch K4 and the second mirror image branch K2 in sequence, and the emitter is connected with the common end of the first resistor R1 and the fourth adjustable resistor R4. The base of the first transistor Q1 is coupled to the base of the second transistor Q2. A first bias voltage VBP with positive temperature coefficient is input into the first mirror branch K1 and the second mirror branch K2, and a second bias voltage VBN with a negative temperature coefficient is input to the current mirror formed by the third mirror branch K3 and the fourth mirror branch K4. The first triode Q1 is formed by connecting a plurality of triodes with the same specification as the second triode Q2 in parallel, and four mirror image branches form two current mirrors, so that the current I flowing through the first triode Q1Q1Is equal to the current I flowing through the second triode Q2Q2。
One end of the third resistor R3 is connected to the operating voltage VDD through the fifth mirror branch K5, and the other end is connected to the base of the first triode Q1. The common terminal of the fifth mirror branch K5 and the third resistor R3 outputs a reference voltage VREF. The fifth mirror branch K5 and the first mirror branch K1 form a current mirror, so that the current I flowing through the first triode Q1Q1Equal to the current I flowing through the third resistor R3R3。
The common end of the second mirror image branch K2 and the fourth mirror image branch K4 is grounded through a compensation capacitor Cc, the input end of the negative feedback branch is connected with the common end of the second mirror image branch K2 and the fourth mirror image branch K4, and the output end of the negative feedback branch is connected with the base of the first triode Q1.
Specifically, in the present application, the drain of the first PMOS transistor P1 is connected to the source of the third PMOS transistor P3 to form a first mirror branch K1. The drain of the second PMOS transistor P2 is connected to the source of the fourth PMOS transistor P4 to form a second mirror branch K2. The source of the third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1 to form a third mirror branch K3. The source of the fourth NMOS transistor N4 is connected to the drain of the second NMOS transistor N2 to form a fourth mirror branch K4. The source electrode of the first NMOS transistor N1 is connected with the collector electrode of the first triode Q1, the drain electrode of the third NMOS transistor N3 is connected with the drain electrode of the third PMOS transistor P3, and the source electrode of the first PMOS transistor P1 is connected with the working voltage VDD. The source electrode of the second NMOS transistor N2 is connected with the collector electrode of the second triode Q2, the drain electrode of the fourth NMOS transistor N4 is connected with the drain electrode of the fourth PMOS transistor P4, and the source electrode of the second PMOS transistor P2 is connected with the working voltage VDD. The gates of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to the drain of the fourth NMOS transistor N4, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected to the second bias voltage VBN. The gates of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the drain of the third PMOS transistor P3, and the gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the first bias voltage VBP.
N1, N2, N3 and N4 form an NMOS cascode current mirror, and P1, P2, P3 and P4 form a PMOS cascode current mirror, so that currents flowing through Q1 and Q2 are equal, and the PSRR (power supply ripple rejection ratio) is improved. The first bias voltage VBP and the second bias voltage VBN may be generated by self-biasing, R1, Q1, and Q2 collectively forming a PTAT current IPTATThe method comprises the following steps:
Figure BDA0002941208230000051
wherein R1 is the resistance of the first resistor, m represents the number ratio between the first transistor Q1 and the second transistor Q2, i.e. the first transistor Q1 is formed by connecting m transistors in parallel with the second transistor Q2, k is the boltzmann constant, T represents the kelvin temperature, and Q is the amount of single electron charge.
The drain of the fifth PMOS transistor P5 is connected to the source of the sixth PMOS transistor P6 to form a fifth mirror image branch K5, the source of the fifth PMOS transistor P5 is connected to the operating voltage VDD, the gate is connected to the gate of the first PMOS transistor P1, the drain of the sixth PMOS transistor P6 is connected to the third resistor R3, and the gate is connected to the gate of the third PMOS transistor P3. P5 has the same specification as P1 and P6 and P3, so that the current I flowing through R3Q3Equal to the current through Q1 and Q2, due to the current I through Q4Q4Is the sum of the currents flowing through Q1 and Q2, i.e. is equivalent to the current I flowing through Q4Q4Is twice the current flowing through Q1 or Q2, and thus has IQ4＝2IQ1＝2IQ2＝2IQ3. So that the reference voltage is
Figure BDA0002941208230000052
Wherein, R4 is the resistance of the fourth adjustable resistor, and R3 is the resistance of the third resistor.
The negative feedback branch comprises a second resistor R2, a fifth NMOS tube N5, a third triode Q3 and a fifth adjustable resistor R5, the drain of the fifth NMOS tube N5 is connected with the working voltage VDD through the second resistor R2, the emitter of the fifth NMOS tube N5 is connected with the collector and the base of the third triode Q3, the emitter of the third triode Q3 is grounded through the fifth adjustable resistor R5, the emitter of the fifth NMOS tube N5 is connected with the base of the first triode Q1, the gate of the fifth NMOS tube N5 is connected with the common ends of the second mirror image branch K2 and the fourth mirror image branch K4, namely the common ends of the fourth PMOS tube P4 and the fourth NMOS tube N4.
In the negative feedback branch, the specification of the fifth NMOS transistor N5 is the same as the specification of the NMOS transistors in the third mirror branch K3 and the fourth mirror branch K4, and specifically, the specification of the first NMOS transistor N1 and the specification of the second NMOS transistor N2 are the same. The third triode Q3 is formed by connecting two triodes with the same specification as the second triode Q2 in parallel, that is, the ratio of the number of the third triodes Q3 to the number of the second triodes Q2 is 2: 1. The second resistor R2 is a protection resistor. The specification of the fifth adjustable resistor R5 is the same as the specification of the fourth adjustable resistor R4 and can be considered as a duplicate of the fourth adjustable resistor R4. The negative feedback branch formed by MN5, Q3, R2 and R5 has two functions: the first is to provide the base current of the first transistor Q1 and the second transistor Q2 through feedback, and the second is to keep the size of the fifth NMOS transistor N5 the same as the first NMOS transistor N1 and the second NMOS transistor N2, so that the current flowing through the fifth NMOS transistor N5 is equal to the current flowing through the first NMOS transistor N1, that is, the current flowing through the first PMOS transistor P1. Since the current flowing through the first PMOS transistor P1 is equal to the current flowing through the fifth PMOS transistor P5, the current flowing through the third transistor Q3 is equal to twice the current flowing through the second transistor Q2, the current flowing through the third transistor Q3 is equal to the current flowing through the fifth adjustable resistor R5, and the current flowing through the fourth adjustable resistor R4 is equal to twice the current flowing through the second transistor Q2, so the current flowing through the fifth adjustable resistor R5 is equal to the current flowing through the fourth adjustable resistor R4. Therefore, the source voltages of the fifth NMOS transistor N5, the first NMOS transistor N1, and the second NMOS transistor N2 are equal (or substantially equal within an error range), that is, the voltage of the collector of the first transistor Q1, the voltage of the collector of the second transistor Q2, and the voltage of the collector of the third transistor Q3 are equal, so as to ensure that the first transistor Q1 and the second transistor Q2 are in a normal operating state.
In addition, the negative feedback branch only has one main pole of the grid electrode of the fifth NMOS tube N5, the output capacitor hooked at the VREF hardly influences the loop, and other poles are all located at a very high frequency, so that the value of the compensation capacitor Cc can be small, the bandwidth of the loop is high, the intermediate frequency PSRR of the circuit is guaranteed, and meanwhile, when the power supply voltage jumps, the transient response is fast.
In the above circuit structure of the present application, the fourth adjustable resistor R4 is a small resistor with a small resistance value, and is mainly used for trimming a fine voltage error, and the voltage on this resistor is small, so that the source voltage of the fifth NMOS transistor N5 can be considered to be about VBE in the error range, and VBE is the voltage between the base and the emitter of the second transistor Q2, so that the minimum value of the working voltage VDD of the whole bandgap reference circuit is VDDminVge + VGS + VOV, where VGS is the voltage between the gate and the source of the fifth NMOS transistor N5, and VOV is the total overdrive voltage of the second mirror branch K2, i.e. VOV is the sum of the overdrive voltage of the second PMOS transistor P2 and the overdrive voltage of the fourth PMOS transistor P4. Therefore, the circuit can keep a higher PSRR and enable the working voltage required by the circuit to be lower.
The circuit structure of the fourth adjustable resistor R4 in this application is as shown in fig. 2, and the fourth adjustable resistor R4 includes a plurality of resistor trimming groups, one end of a series circuit formed by the plurality of resistor trimming groups is connected with the emitter of the second triode, and the other end is grounded, each resistor trimming group is formed by connecting an MOS transistor and a fixed resistor in parallel, and the gates of the MOS transistors in each resistor trimming group are controlled by respective control signals. In addition, in order to ensure high-precision trimming, the resistance of the fixed resistor in each resistor trimming group from the emitter of the second triode Q2 to the ground is exponentially increased, and in order to ensure that the on-resistance of the MOS transistor switch does not affect the resistance, the number of MOS transistors in each resistor trimming group from the emitter of the second triode Q2 to the ground is also exponentially increased, wherein a plurality of MOS transistors in the same resistor trimming group are connected in parallel. Therefore, the larger the size of the MOS transistor closer to the ground in the fourth adjustable resistor R4 is, a larger parasitic circuit may be generated, and in the present application, the fourth adjustable resistor R4 and the third resistor R3 are separately disposed, so that the PSRR is also prevented from being affected by the parasitic capacitance of the large MOS transistor in the fourth adjustable resistor R4.
Referring to fig. 2, the bandgap reference circuit includes, in addition to the reference core shown in fig. 1, a start-up circuit, in which a source of a second start-up NMOS transistor NS2 is grounded, a drain of the second start-up NMOS transistor NS2 is connected to an operating voltage VDD through a start-up resistor RS, and a gate and a drain of the second start-up NMOS transistor NS2 are connected to a gate of a third start-up NMOS transistor NS 3. The source electrode of the third start-up NMOS transistor NS3 is grounded, and the drain electrode is connected to the common terminal of the first mirror branch K1 and the third mirror branch K3, that is, the common terminal of the third PMOS transistor P3 and the third NMOS transistor N3. The source electrode of the first start-up NMOS transistor NS1 is grounded, the drain electrode of the first start-up NMOS transistor NS1 is connected with the drain electrode of the second start-up NMOS transistor NS2, and the gate electrode of the first start-up NMOS transistor NS1 is connected with the common end of the fifth mirror image branch K5 and the third resistor to obtain the reference voltage VREF. If the reference core portion shown in fig. 1 is in a degenerate state where the gate-source voltages of the NMOS transistor and the PMOS transistor are both 0, VREF is 0, so the first enable NMOS transistor NS1 in the enable circuit is turned off, the second enable NMOS transistor NS2 has current flowing through it and the current magnitude is (VDD-VGSMNS2)/RS, and VGSNS2 is the voltage between the gate and the source of NS2, and the first PMOS transistor P1 and the third PMOS transistor P3 in the reference core portion are pulled out of the degenerate state by NS3 mirroring. When VREF is normal, the first start-up NMOS transistor NS1 is turned on, the gate terminal of the second start-up NMOS transistor NS2 is pulled to 0, no current flows through the third start-up NMOS transistor NS3, and the start-up circuit is exited when the reference core portion operates normally.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (8)

1. A high performance bandgap reference circuit, wherein in said bandgap reference circuit:
a collector of the first triode is connected with a working voltage through a third mirror image branch and a first mirror image branch in sequence, an emitter of the first triode is grounded through a first resistor and a fourth adjustable resistor, a collector of the second triode is connected with the working voltage through the fourth mirror image branch and a second mirror image branch in sequence, the emitter of the second triode is connected with a common end of the first resistor and the fourth adjustable resistor, and a base of the first triode is connected with a base of the second triode; a first bias voltage with a positive temperature coefficient is input into a current mirror formed by the first mirror image branch and the second mirror image branch, a second bias voltage with a negative temperature coefficient is input into a current mirror formed by the third mirror image branch and the fourth mirror image branch, the first triode is formed by connecting a plurality of triodes with the same specification as the second triode in parallel, and the current flowing through the first triode is equal to the current flowing through the second triode;
one end of a third resistor is connected with the working voltage through a fifth mirror image branch, the other end of the third resistor is connected with the base electrode of the first triode, and the common end of the fifth mirror image branch and the third resistor outputs a reference voltage; the fifth mirror image branch and the first mirror image branch form a current mirror, and the current flowing through the first triode is equal to the current flowing through the third resistor;
the common ends of the second mirror image branch and the fourth mirror image branch are grounded through a compensation capacitor, the input end of a negative feedback branch is connected with the common ends of the second mirror image branch and the fourth mirror image branch, and the output end of the negative feedback branch is connected with the base electrode of the first triode.
2. The bandgap reference circuit according to claim 1, wherein the fourth adjustable resistor comprises a plurality of resistor trimming groups, one end of a series circuit formed by the plurality of resistor trimming groups is connected to the emitter of the second transistor, and the other end of the series circuit is grounded, each resistor trimming group is formed by connecting an MOS transistor and a fixed resistor in parallel, and gates of the MOS transistors in the resistor trimming groups are controlled by respective control signals.
3. The bandgap reference circuit as claimed in claim 2, wherein the number of MOS transistors in each resistor trimming group from the emitter of the second transistor to the ground is exponentially increased, and the resistance of the fixed resistor in each resistor trimming group from the emitter of the second transistor to the ground is exponentially increased; wherein, a plurality of MOS tubes in the same resistor trimming group are connected in parallel.
4. The bandgap reference circuit according to claim 1, wherein the negative feedback branch comprises a second resistor, a fifth NMOS transistor, a third triode, and a fifth adjustable resistor, a drain of the fifth NMOS transistor is connected to the operating voltage through the second resistor, an emitter of the fifth NMOS transistor is connected to a collector and a base of the third triode, an emitter of the third triode is grounded through the fifth adjustable resistor, an emitter of the fifth NMOS transistor is connected to the base of the first triode, and a gate of the fifth NMOS transistor is connected to a common terminal of the second mirror branch and the fourth mirror branch.
5. The bandgap reference circuit of claim 4, wherein the minimum value of the operating voltage of the bandgap reference circuit is a sum of VBE, VGS and VOV, where VBE is a voltage between a base and an emitter of the second transistor, VGS is a voltage between a gate and a source of the fifth NMOS transistor, and VOV is a total overdrive voltage of the second mirror branch.
6. The bandgap reference circuit according to claim 4, wherein the third mirror branch and the fourth mirror branch are respectively constructed based on NMOS transistors, and the specification of the fifth NMOS transistor is the same as that of the NMOS transistors in the third mirror branch and the fourth mirror branch; the third triode is formed by connecting two triodes with the same specification of the second triode in parallel, the specification of the fifth adjustable resistor is the same as the specification of the fourth adjustable resistor, the current flowing through the third triode is equal to the current flowing through twice the current of the second triode, the current flowing through the fifth adjustable resistor is equal to the current flowing through the fourth adjustable resistor, and the voltage of the collector of the first triode, the voltage of the collector of the second triode and the voltage of the collector of the third triode are equal.
7. The bandgap reference circuit of claim 1, wherein the drain of the first PMOS transistor is connected to the source of the third PMOS transistor to form a first mirror image branch, the drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor to form a second mirror image branch, the source of the third NMOS transistor is connected to the drain of the first NMOS transistor to form a third mirror image branch, and the source of the fourth NMOS transistor is connected to the drain of the second NMOS transistor to form a fourth mirror image branch;
the source electrode of the first NMOS tube is connected with the collector electrode of the first triode, the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, and the source electrode of the first PMOS tube is connected with the working voltage; the source electrode of the second NMOS tube is connected with the collector electrode of the second triode, the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the second PMOS tube is connected with the working voltage;
the grid electrodes of the first NMOS tube and the second NMOS tube are connected and connected with the drain electrode of the fourth NMOS tube, and the grid electrodes of the third NMOS tube and the fourth NMOS tube are connected and connected with the second bias voltage; the grid electrodes of the first PMOS tube and the second PMOS tube are connected with the drain electrode of the third PMOS tube, and the grid electrodes of the third PMOS tube and the fourth PMOS tube are connected with the first bias voltage;
the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube to form a fifth mirror image branch, the source electrode of the fifth PMOS tube is connected with the working voltage, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the third resistor, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the third PMOS tube.
8. The bandgap reference circuit according to claim 1, further comprising a start-up circuit, wherein in the start-up circuit, a source of a second start-up NMOS transistor is grounded, a drain of the second start-up NMOS transistor is connected to the operating voltage through a start-up resistor, a gate and a drain of the second start-up NMOS transistor are connected to a gate of a third start-up NMOS transistor, a source of the third start-up NMOS transistor is grounded, and a drain of the third start-up NMOS transistor is connected to the common terminals of the first mirror branch and the third mirror branch; the source electrode of the first start NMOS tube is grounded, the drain electrode of the first start NMOS tube is connected with the drain electrode of the second start NMOS tube, and the grid electrode of the first start NMOS tube is connected with the fifth mirror image branch and the common end of the third resistor to obtain reference voltage.
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CN113419591A (en) * 2021-07-23 2021-09-21 深圳英集芯科技股份有限公司 Leakage current compensation structure, method, device and equipment based on band gap collector
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CN115016581B (en) * 2022-05-31 2024-02-02 电子科技大学长三角研究院(湖州) Band-gap reference circuit structure with starting circuit
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CN116742106A (en) * 2022-10-11 2023-09-12 荣耀终端有限公司 Battery module, charging control method and electronic equipment
CN116736925A (en) * 2022-12-21 2023-09-12 无锡迈尔斯通集成电路有限公司 Zero-current high-precision enabling circuit
CN116736925B (en) * 2022-12-21 2024-03-12 无锡迈尔斯通集成电路有限公司 Zero-current high-precision enabling circuit
CN117707272A (en) * 2024-02-05 2024-03-15 江苏润石科技有限公司 Gain-enhanced reference voltage source and application thereof
CN117707272B (en) * 2024-02-05 2024-04-19 江苏润石科技有限公司 Gain-enhanced reference voltage source and application thereof

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