CN116742106A

CN116742106A - Battery module, charging control method and electronic equipment

Info

Publication number: CN116742106A
Application number: CN202211239736.5A
Authority: CN
Inventors: 林祚鹏; 卢轮; 申彬彬
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2022-10-11
Filing date: 2022-10-11
Publication date: 2023-09-12
Anticipated expiration: 2042-10-11
Also published as: CN116742106B

Abstract

The embodiment of the application relates to the technical field of charging, in particular to a battery module, a charging control method and electronic equipment. The impedance between different loops can be flexibly adjusted under different charging conditions, so that the damage of the excessive bias current to the battery is avoided. The battery module comprises an electric core, a protection board and the like. The electric core comprises an electric core body, a first electrode lug, a second electrode lug and a third electrode lug. The first electrode lug, the second electrode lug and the third electrode lug are respectively and electrically connected with the battery cell body. The first tab and the third tab have a first polarity and the second tab has a second polarity. The second tab corresponds to the first loop with the first tab. The third tab corresponds to the second loop with the first tab. The resistance of the first loop is less than the resistance of the second loop. The first loop is provided with a resistance adjusting module, and the resistance adjusting module is used for increasing the resistance of the first loop, and the resistance of the increased first loop is smaller than that of the second loop.

Description

Battery module, charging control method and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of charging, in particular to a battery module, a charging control method and electronic equipment.

Background

With the development of battery technology, multi-tab battery designs are increasingly being used. By adopting the battery design scheme of the multipolar lugs, when the battery is charged, at least two charging loops are formed among the lugs, so that the overall internal resistance of the battery cell is reduced, the charging speed is increased, and the temperature rise of the battery cell in the charging and discharging processes is reduced.

In the current multi-lug battery design scheme, the resistances of different loops are obviously different, so that after long-time charging, obvious bias current phenomena appear on different loops, and the battery performance is further influenced.

Disclosure of Invention

The embodiment of the application provides a battery module, a charging control method and electronic equipment, which can flexibly adjust the impedance between different loops under different charging conditions, so as to avoid damage of excessive bias current to a battery.

In order to achieve the above purpose, the embodiment of the application adopts the following technical scheme:

in a first aspect, a battery module is provided, the battery module including a battery cell. The battery cell comprises a battery cell body, a first tab, a second tab and a third tab. The first electrode lug, the second electrode lug and the third electrode lug are respectively and electrically connected with the battery cell body. The first tab and the third tab have a first polarity, and the second tab has a second polarity. The second tab and the first tab, and the corresponding first processing link correspond to a first loop capable of inputting or outputting voltage and current to or from the cell body. The third tab and the first tab, and the corresponding second processing link correspond to a second loop, the first loop being capable of inputting voltage and current to the cell body or outputting voltage and current from the cell body. The resistance of the first loop is less than the resistance of the second loop. The first loop is provided with a resistance adjusting module which is used for increasing the resistance of the first loop. In some implementations, the battery module may further include a protection plate for setting related circuits during operation of the battery module. It will be appreciated that based on the resistance adjustment of this scheme, the adjusted resistances of the first loop and the second loop may be the same or similar, e.g., less than a predetermined resistance threshold.

Therefore, the resistance adjusting module is additionally arranged on the loop with the smaller resistance, so that the resistance on the loop with the smaller resistance can be amplified and adjusted, the resistance difference on different loops is reduced, and the bias current condition of different loops is further reduced. It can be understood that in different implementations, the battery cells in the battery module can also have more tabs, so as to realize the design of multiple loops of the multiple tabs. Then, the resistance adjustment can be performed according to the scheme in the example above on at least one loop with smaller resistance in the multi-loop, so as to achieve the effect of reducing bias current. It will be appreciated that in this example, the resistance adjustment module has a variable resistance characteristic, so that the electronic device can adaptively and properly adjust the resistance on the small-resistance loop under different operating scenarios, thereby reducing the resistance difference on different loops and reducing the bias current caused by the resistance difference as much as possible.

Optionally, the resistance adjustment module is equivalent to a first resistance in a first charging state, and the resistance adjustment module is equivalent to a second resistance in a second charging state. The first charging state is smaller than the second charging state in charging time, and the first resistance is smaller than the second resistance. When the charging times are smaller, smaller resistors are connected in series; when the number of charging times is large, a large resistor is connected in series. Therefore, even if the resistance difference between different loops is increased due to multiple charging, the bias current condition caused by the gradually increased resistance difference can be prevented from developing to a more remarkable state by serially connecting larger resistors.

Optionally, the resistance adjusting module includes a resident resistor R1, and at least one switching unit, where a first switching unit is disposed in parallel with the resident resistor R1 on the first loop. The first switching unit is included in the at least one switching unit. The working states of the first switching unit comprise a first working state and a second working state, the equivalent resistance of the first switching unit in the first working state is a third resistance, the equivalent resistance of the first switching unit in the second working state is a fourth resistance, and the third resistance is smaller than the fourth resistance. This example provides a specific composition example of a resistance adjustment module. The switching unit has the characteristic of variable resistance through the parallel connection of the switching unit and the resident resistor R1.

Optionally, the first switching unit includes a first MOS transistor, the first operating state corresponds to an on state of the first MOS transistor, and the second operating state corresponds to an off state of the first MOS transistor. It can be understood that when the MOS transistor is turned on, the resistance of the corresponding switching unit is the on internal resistance r0. At this time, the equivalent resistance is close to 0 after being connected in parallel with the resistor R1. Correspondingly, when the MOS tube is cut off, the resistance of the corresponding switching unit is cut-off resistance and is near infinity. At this time, the equivalent resistance is close to the resistance R1 after being connected in parallel with the resistance R1.

Optionally, the resistance adjusting module further includes a second switching unit, where the second switching unit is in a parallel relationship with the first switching unit and the resident resistor R1. In this way, further switching units can be introduced. The effect of multistage adjustment is realized by controlling the working states of different switching units.

Optionally, the battery cell further includes a fourth tab, the fourth tab has the first polarity, the fourth tab corresponds to the second tab, and the third loop can input voltage and current to the battery cell body or output voltage and current from the battery cell body. Therefore, in the battery scheme with more lugs, the technical scheme provided by the invention can be applied to realize the effect of regulating the resistance of a plurality of loops.

Optionally, the resistance of the third loop is smaller than the resistance of the second loop, the third loop is provided with the resistance adjusting module, and the resistance adjusting module is used for increasing the resistance of the third loop, and the increased resistance of the third loop is smaller than the resistance of the second loop.

Optionally, the first polarity is positive and the second polarity is negative. Alternatively, the first polarity is a negative polarity and the second polarity is a positive polarity.

In a second aspect, there is provided a charge control method applied to an electronic device provided with the battery module as provided in the first aspect and any one of its possible designs, the method comprising: when the electronic equipment starts to charge, the electronic equipment acquires the working parameters of the battery module, and adjusts the resistance of the resistance adjustment module in the battery module according to the working parameters so as to increase the resistance of a loop in which the resistance adjustment module is located.

Thus, the electronic device can determine whether the adjustment of the resistance on the small-resistance loop needs to be triggered by collecting the working parameters. Thereby realizing the effect of adaptively adjusting the impedance difference between the loops under different scenes.

Optionally, the operating parameters of the battery module include at least one of the following: the charging times and the charging time are different in resistance of the first loop and the second loop in the charging process. The first loop is a loop corresponding to a first tab and a second tab in the battery module, the second loop is a loop corresponding to a third tab and the second tab in the battery module, the polarities of the first tab and the third tab are the same, and the polarity of the second tab is different from the first tab.

It can be understood that the larger the number of charging, the larger the bias current ratio on different loops, so that the resistance on the small-resistance loop can be controlled according to the number of charging. In other implementations, the longer the charging time, the greater the bias current ratio on different loops, so the resistance of the small-resistance loops can be controlled according to the charging time. Similarly, in other implementations, the greater the difference in resistance across the loop, the more pronounced the bias current is indicated, and thus the magnitude of the resistance across the small resistance loop can be controlled based on the difference in resistance. The number of charges and the resistance of each loop can be obtained from an electricity meter on the processing link.

Optionally, the operating parameters of the battery module include charging times, and the electronic device obtains the operating parameters of the battery module, including: the electronic device obtains the current charging times. The electronic device adjusts the resistance of the resistance adjustment module in the battery module according to the working parameter, including: and under the condition that the current charging times are larger than a preset charging times threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

Optionally, the working parameters of the battery module include a charging time period, and the electronic device obtains the working parameters of the battery module, including: the electronic device obtains a current charging duration. The electronic device adjusts the resistance of the resistance adjustment module in the battery module according to the working parameter, including: and under the condition that the current charging time length is larger than a preset charging time length threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

Optionally, the working parameters of the battery module include a resistance difference between the first loop and the second loop, and the electronic device obtains the working parameters of the battery module, including: the electronic device obtains a current resistance difference. The electronic device adjusts the resistance of the resistance adjustment module in the battery module according to the working parameter, including: and under the condition that the current resistance difference is larger than a preset resistance difference threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

The working state of at least one MOS tube is switched to the cut-off state, so that the resistance of the resistance adjusting module is increased, namely the resistance connected in series on the small-resistance loop is increased. Thus, the resistance difference between the small resistance loop and other loops is reduced, and larger bias current is avoided. It can be understood that when the electronic device just starts to charge, the resistance difference of each loop is not large, so that all the MOS transistors can be in a conductive state, so as to provide a larger space for subsequent impedance adjustment.

Optionally, before the electronic device adjusts the resistance of the resistance adjustment module in the battery module according to the operating parameter, the method further includes: the electronic device determines that the current charging number is greater than a first preset number. Therefore, the working state of the MOS tube is triggered and adjusted through the magnitude relation between the charging times and the preset times, and the reasonable configuration of the resistance adjustment triggering is realized.

Optionally, the method further comprises: and under the condition that the current charging times are greater than the second preset times, the electronic equipment adjusts the resistance of the resistance adjustment module in the battery module according to the working parameters, so that the continuous resistance of a loop in which the resistance adjustment module is positioned is increased. Under the condition that a plurality of switching units are arranged, the resistance of the small-resistance loop can be gradually improved through triggering the resistance adjusting mechanism for a plurality of times, and the effect of multistage adjustment is achieved.

In a third aspect, there is provided an electronic device such as the battery module provided by the first aspect and any one of the possible designs thereof, which performs the charge control method as provided by the second aspect and any one of the possible designs thereof when the electronic device is charged.

In a fourth aspect, an electronic device is provided that includes one or more processors and one or more memories. One or more memories are coupled to the one or more processors, the one or more memories storing computer instructions. The computer instructions, when executed by one or more processors, cause the electronic device to perform the method as provided in the second aspect and any one of its possible designs described above.

In a fifth aspect, a chip system is provided, the chip system comprising an interface circuit and a processor. The interface circuit and the processor are interconnected by a wire. The interface circuit is for receiving signals from the memory and transmitting signals to the processor, the signals including computer instructions stored in the memory. When the processor executes the computer instructions, the system-on-chip performs the method as provided in the second aspect and any one of its possible designs described above.

In a sixth aspect, there is provided a computer readable storage medium comprising computer instructions which, when run, perform a method as provided in the second aspect and any one of its possible designs described above.

In a seventh aspect, a computer program product is provided, comprising instructions in the computer program product, which when run on a computer, enables the computer to perform the method as provided in the second aspect and any one of its possible designs described above, according to the instructions.

It should be understood that the technical features of the technical solutions provided in the third aspect to the seventh aspect may all correspond to the technical solutions provided in the first aspect or the second aspect and the possible designs thereof, so that the beneficial effects that can be achieved are similar, and are not repeated here.

Drawings

Fig. 1 is a schematic diagram illustrating a battery module arrangement in an electronic device;

FIG. 2 is a schematic view of a multi-tab battery module;

fig. 3 is a schematic operation diagram of a three-pole ear battery module;

FIG. 4 is a schematic diagram of bias current ratio of two loops;

FIG. 5 is a diagram showing the difference in temperature rise between two circuits;

fig. 6 is a schematic diagram of an electronic device according to an embodiment of the present application;

fig. 7 is a schematic diagram illustrating a battery module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a resistance adjustment module according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a resistance adjustment module according to an embodiment of the present application;

fig. 10 is a schematic flow chart of a charging control method according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a charging process according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a resistance adjustment module according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a resistance adjustment module according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a resistance adjustment module according to an embodiment of the present application;

fig. 15 is a schematic flow chart of a charging control method according to an embodiment of the present application;

fig. 16 is a schematic diagram of an electronic device according to an embodiment of the present application;

Fig. 17 is a schematic diagram of a system-on-chip according to an embodiment of the present application.

Detailed Description

The electronic equipment can be provided with a battery module which is used for supplying power to each electronic component of the electronic equipment under the condition of no external power supply so as to support the normal operation of each electronic component.

In an exemplary embodiment, in conjunction with fig. 1, an electronic device is taken as an example of a mobile phone. A battery module may be provided in the mobile phone. The battery module may be connected to a main board through an inter-Board To Board (BTB) connector. The motherboard may serve as a carrier for electronic components such as processors. When the battery module is required to supply power to the electronic component, the BTB connector outputs current to the electronic component correspondingly arranged on the main board, so that the power supply to the electronic component is realized.

As a possible implementation, fig. 2 shows a specific construction schematic of a battery module. As shown in fig. 2, the battery module may include at least one battery cell, and a processing circuit.

The battery core can be used as an energy storage component of the battery module and used for storing electric energy in a charging process and outputting electric energy to other electronic components in a discharging process. The cell may be provided with a positive electrode and a negative electrode. The positive electrode and the negative electrode can be respectively provided with a tab made of metal. Electrical connection to other components (e.g., processing circuitry) is achieved through the tabs.

As shown in fig. 2, in the present example, two battery cells, such as a battery cell 21 and a battery cell 22, may be provided in the battery module. The battery cells 21 and 22 may be provided with positive electrode tabs, respectively. For example, positive electrode tab b1+ may be provided on cell 21, and positive electrode tab b2+ may be provided on cell 22. A negative electrode tab may be further provided on the battery cell 21 and the battery cell 22. In some implementations, the negative tabs of cell 21 and cell 22 can multiplex the same tab, such as negative tab B-. Of course, in other embodiments, the battery module may also include more battery cells. The arrangement manner between the respective cells may be set with reference to the structure of two cells as shown in fig. 2. It should be noted that, in one implementation of the embodiment of the present application, the cell 21 and the cell 22 may be physically divided, that is, two independent cells may be included in the battery module. In another implementation of the embodiment of the present application, the battery cells 21 and 22 may be a logic division, that is, one battery cell may be included in the battery module. The positive electrode lug B1+, the negative electrode lug B-and the positive electrode lug B2+ are sequentially arranged on one edge of the battery cell, which is close to the main board. Thus, a logical cell 21 is formed between the positive tab b1+ and the negative tab B-, and a logical cell 22 is formed between the positive tab b2+ and the negative tab B-.

In this example, a processing circuit may also be included in the battery module. In some implementations, the processing circuitry may be disposed on the aforementioned protective plate. The processing circuitry may be disposed between the BTB connector and the battery cells. In some implementations, the processing circuitry may include battery protection circuitry, battery anti-counterfeiting circuitry, fuel gauges, and the like.

From a logic division, the battery cells 21 and 22 may be respectively corresponding to respective processing circuits for performing corresponding processing of current and/or voltage on the electrical signals during the charge/discharge process of the battery cells 21 or 22. As shown in fig. 2, each component and the connection line on the processing circuit corresponding to the battery cell 21 may form the processing link 21 corresponding to the battery cell 21. Each component and the connection line on the processing circuit corresponding to the battery cell 22 may form the processing link 22 corresponding to the battery cell 21.

Illustratively, the processing chain 21 may include a positive tab B1+ connected at one end to the cell 21, and the processing chain 21 may further include a negative tab B-connected at one end to thereby electrically connect the processing chain 21 to the cell 21. The processing circuit 21 may further comprise at least one PIN (PIN) connected at one end to the BTB, so that the battery 21 supplies power to the motherboard via the BTB or charges via the motherboard. Similarly, the processing link 22 may include a positive tab B2+ connected at one end to the cell 22, and the processing link 22 may also include a negative tab B-connected at one end to thereby effect electrical connection of the processing link 22 to the cell 22. The processing circuit 22 may also include at least one PIN (PIN) connected at one end to the BTB to facilitate powering the motherboard by the BTB or charging the motherboard by the battery cell 22.

In this way, the battery cell 21 and the processing circuit 21 corresponding to the battery cell 21 can constitute a charge/discharge circuit of the battery cell 21. The battery cell 22 and the processing circuit 22 corresponding to the battery cell 22 may constitute a charge-discharge circuit of the battery cell 22.

It will be appreciated that the battery module arrangement including a plurality of cells in this example is capable of forming two parallel loops (such as loops corresponding to each of the cells 21 and 22) within the cells by two positive tabs and one negative tab, relative to a single cell arrangement. Therefore, the overall internal resistance of the battery cell is reduced, the charging speed is increased, and the temperature rise of the battery cell in the charging and discharging process is reduced. In this example, the two cell designs correspond to three tabs, while in some implementations, the cell 21 and the cell 22 as shown in fig. 2 may also correspond to one complete cell, so the cell design as shown in fig. 2 may also be referred to as a three-tab cell scheme, or a three-tab battery scheme.

In general, in the three-pole ear cell scheme, in order to avoid the battery energy density loss caused by the symmetrical design, the loop resistances corresponding to the two cells may be set to different resistances. The resistance of the battery core is not easy to adjust, so that the resistance of a corresponding processing link can be adjusted, and the asymmetric design of loop resistance is realized.

For example, in connection with fig. 3. The resistance of the processing link 21 corresponding to the cell 21 may be set to R. The resistance of the processing link 22 corresponding to the cell 22 may be different from R. For example, the resistance of the processing link 22 may be set to 3R. Thus, in this example, the loop resistances of the two cells may approach a 1:3 relationship.

Due to the difference in resistance, the current on the loop is also different when the two cells are operating.

As an example, a charging process is taken as an example. The current flows from the positive electrode lug to the negative electrode lug in the battery cell. In the case where the magnitude of the current flowing out on the negative electrode tab B-is 4X, the current flowing in the positive electrode tab b1+ corresponding to the cell 21 having a smaller loop resistance may be larger, for example, 3X. Correspondingly, the current flowing into the positive tab B2+ corresponding to the cell 22 with a larger loop resistance may be smaller, such as X.

Thus, due to the asymmetric design of the loop resistance, bias currents on the two positive tabs are unavoidable.

For example, fig. 4 shows a change of the bias current ratio of the current on the positive tab b1+ to the bias current on the positive tab b2+ with an increase of the charging time in one charging period. It can be seen that the bias current ratio is about 2.5 at the start of charging. As the charging time increases, the bias current ratio gradually increases. That is, as the charging time increases, the current on the positive tab b1+ and the current on the positive tab b2+ are increasingly different.

This can lead to a series of problems. For example, when the battery cell is a lithium battery cell, irreversible metal lithium precipitation (i.e., lithium precipitation) tends to occur on the positive electrode tab b1+ having a large current. For another example, under the condition that the bias current ratio reaches a certain value, the temperature rise of the two positive lugs can be greatly different. Illustratively, with reference to the illustration of fig. 5, both the positive tab b1+ and the positive tab b2+ experience a degree of temperature rise over time. And the temperature rise on the positive electrode lug B1+ with larger current is faster, so that the temperature rise difference between the positive electrode lug B1+ and the positive electrode lug B2+ in charging reaches 5 ℃ at maximum.

The above lithium precipitation phenomenon and the difference in temperature rise of the two positive electrode tabs can influence the overall working stability and the service life of the battery module.

In order to solve the above problems, the embodiment of the application provides a scheme that a resistance adjusting module is additionally arranged on a loop with a smaller resistance so as to flexibly adjust the resistance of the loop with the smaller resistance according to actual working conditions. For example, when the charging frequency is greater than a preset charging frequency threshold, the resistance on the smaller resistance loop is adjusted to be large by controlling the resistance adjusting module, so that the influence of the continuous increase of bias current on the battery module in the asymmetric design of the three-pole ear cell and the like is avoided.

The following will describe the technical scheme provided by the embodiment of the present application in detail with reference to the accompanying drawings.

The technical scheme provided by the embodiment of the application can be applied to electronic equipment. The electronic equipment can be provided with a battery module which is used for supplying power to the electronic equipment under the condition of no external power supply.

By way of example, the electronic device to which embodiments of the present application relate may include at least one of a cell phone, a foldable electronic device, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (personal digital assistant, PDA), an augmented reality (augmented reality, AR) device, a Virtual Reality (VR) device, an artificial intelligence (artificial intelligence, AI) device, a wearable device, a vehicle-mounted device, a smart home device, or a smart city device. The embodiment of the application does not limit the specific type of the electronic device.

As a possible implementation, please refer to fig. 6, which is a schematic diagram of hardware components of an electronic device according to an embodiment of the present application.

As shown in fig. 6, in this example, the electronic device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) connector 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a key 190, a motor 191, an indicator 192, a camera 193, a display 194, a subscriber identity module (subscriber identification module, SIM) card interface 195, and the like. The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

It should be understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the application, the electronic device may include more or less components than illustrated, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

In the example shown in fig. 6, the processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The processor 110 may generate operation control signals according to the instruction operation code and the timing signals to complete instruction fetching and instruction execution control. A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 may be a cache memory. The memory may hold instructions or data that are used or used more frequently by the processor 110. If the processor 110 needs to use the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thus increasing the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others. The processor 110 may be connected to the touch sensor, the audio module, the wireless communication module, the display, the camera, etc. module through at least one of the above interfaces.

It should be understood that the connection relationship between the modules illustrated in the embodiments of the present application is only illustrative, and does not limit the structure of the electronic device. In other embodiments of the present application, the electronic device may also use different interfacing manners, or a combination of multiple interfacing manners in the foregoing embodiments.

The wireless communication function of the electronic device may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The antennas 1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device may be used to cover a single or multiple communication bands. Different antennas may also be multiplexed to increase the utilization of the antennas. For example: the antenna 1 may be multiplexed into a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The wireless communication module 160 may provide solutions for wireless communication including wireless local area network (wireless local area networks, WLAN) (e.g., wireless fidelity (wireless fidelity, wi-Fi) network), bluetooth (BT), bluetooth low energy (bluetooth low energy, BLE), ultra Wide Band (UWB), global navigation satellite system (global navigation satellite system, GNSS), frequency modulation (frequency modulation, FM), near field wireless communication technology (near field communication, NFC), infrared technology (IR), etc. for application on an electronic device. The wireless communication module 160 may be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the electromagnetic wave signals, filters the electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, frequency modulate it, amplify it, and convert it to electromagnetic waves for radiation via the antenna 2.

The electronic device may implement display functions through a GPU, a display screen 194, an application processor, and the like. The GPU is a microprocessor for image processing, and is connected to the display 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel. The display panel may employ a liquid crystal display (liquid crystal display, LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED) or an active-matrix organic light-emitting diode (matrix organic light emitting diode), a flexible light-emitting diode (flex), a mini, a Micro led, a Micro-OLED, a quantum dot light-emitting diode (quantum dot light emitting diodes, QLED), or the like. In some embodiments, the electronic device may include 1 or more display screens 194.

The electronic device may implement camera functions through camera module 193, isp, video codec, GPU, display 194, and application processor AP, neural network processor NPU, etc.

The digital signal processor is used for processing digital signals, and can also process other digital signals. For example, when the electronic device selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, and so on.

Video codecs are used to compress or decompress digital video. The electronic device may support one or more video codecs. In this way, the electronic device may play or record video in a variety of encoding formats, such as: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The NPU is a neural-network (NN) computing processor, and can rapidly process input information by referencing a biological neural network structure, for example, referencing a transmission mode between human brain neurons, and can also continuously perform self-learning. Applications such as intelligent cognition of electronic devices can be realized through the NPU, for example: image recognition, face recognition, speech recognition, text understanding, etc.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card. Or transfer files such as music, video, etc. from the electronic device to an external memory card.

The internal memory 121 may be used to store computer executable program code that includes instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device (e.g., audio data, phonebook, etc.), and so forth. In addition, the internal memory 121 may include a flash random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 110 performs various functional methods or data processing of the electronic device by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The electronic device may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

In the electronic device as provided in fig. 6, the charge management module 140 is configured to receive a charging input of a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charge management module 140 may receive a charging input of a wired charger through the USB interface 130. In some wireless charging embodiments, the charge management module 140 may receive wireless charging input through a wireless charging coil of the electronic device. The charging management module 140 may also supply power to the electronic device through the power management module 141 while charging the battery 142.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charge management module 140 to power the processor 110, the internal memory 121, the display 194, the camera 193, the wireless communication module 160, and the like. The power management module 141 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, resistance) and other parameters. In other embodiments, the power management module 141 may also be provided in the processor 110. In other embodiments, the power management module 141 and the charge management module 140 may be disposed in the same device.

In this example, the battery 142 may correspond to the battery module in the foregoing example. That is, in some embodiments, a battery 142 may include a cell (e.g., a three-pole ear cell) and corresponding processing circuitry. In other embodiments, other types of cells, such as cells with more tabs, may also be included in the battery 142.

As described in the previous examples, a three-pole ear cell is taken as an example. When the battery 142 is charged, two loops having different resistances may be formed.

In connection with fig. 7, in the present application, a resistance adjustment module may be provided on a loop having a smaller resistance. For example, the resistance adjustment module may be connected in series with the corresponding loop of the cell 21, or the resistance adjustment module may be connected in series with the corresponding loop of the positive tab b1+ and the negative tab B-. As an implementation, one end of the resistance adjustment module may be connected in series at point 71 of the loop and the other end of the resistance adjustment module may be connected in series at point 72 of the loop. The points 71 and 72 are outside of the cell 21 and cell 22 common link (e.g., negative ear B-direct link). Thus, the resistance module can only carry out resistance adjustment on the corresponding loop of the battery cell 21, and the resistance of the corresponding loop of the battery cell 22 is not affected.

In the following description, a loop having a smaller resistance may be referred to as a small-resistance loop. For example, the cell 21 corresponds to a loop, and for example, the cell corresponds to a loop in the positive tab B1+ and the negative tab B-. The loop having a larger resistance may be referred to as a large resistance loop. For example, the cell 22 corresponds to a loop, and for example, the cell corresponds to a loop in the positive tab B2+ and the negative tab B-.

In some embodiments, the resistance adjustment unit may operate at a first resistance having a smaller resistance value. Wherein the first resistance is less than the difference between the resistances of the large resistance loop and the small resistance loop. The operating scenario may correspond to a situation where the two loop bias conditions are relatively less severe. For example, a shorter charge duration, or fewer charges, etc.

Then, when the battery is charged, the first resistor may be connected in series to the small-resistance circuit, thereby raising the resistance of the small-resistance circuit by a small amount. Therefore, the difference of the resistances between the small-resistance loop and the large-resistance loop is reduced, and the bias current condition of the two loops is further weakened. Thus, the problem that the overall working stability and the service life of the battery module are influenced due to bias current can be solved.

In other embodiments, the resistance adjustment unit may operate at the second resistance. The second resistance is smaller than the difference between the resistances of the large resistance loop and the small resistance loop, and the second resistance is larger than the first resistance. The operating scenario may correspond to a situation where the two loop bias conditions are relatively severe. For example, a longer charging period, or a larger number of times of charging.

Then, when the battery is charged, the second resistor may be connected in series in the small-resistance circuit, thereby significantly increasing the resistance of the small-resistance circuit. Therefore, the difference of the resistances between the small-resistance loop and the large-resistance loop is obviously reduced, the bias current which is obvious originally is corrected, and the bias current conditions of the two loops are further weakened. Thus, the problem that the overall working stability and the service life of the battery module are influenced due to bias current can be solved.

As a possible implementation, fig. 8 shows a schematic of the composition of a resistance adjustment module.

As shown in fig. 8, the resistance adjustment module may include a switching unit and a resident resistor R1. Wherein the resistance of the resistor R1 is smaller than the difference between the resistances of the small-resistance loop and the large-resistance loop. The resistance adjusting module can provide different resistances according to different states of the switching unit.

In some embodiments, the switching unit may be in a conductive state. The switching cell in the on state may have an on internal resistance r0. Then, the resistor provided by the resistor adjusting module may be a first resistor, which is equivalent to a resistor formed by connecting the resident resistor R1 and the conducting internal resistor R0 in parallel.

In other embodiments, the switching unit may be in an off state (or an off state). Then, the resistor provided by the resistor adjusting module may be a second resistor, where the second resistor is equivalent to the resistor after the resistor R1 and the cut-off internal resistance of the switching unit are connected in parallel. It is understood that the cut-off internal resistance of the switching unit may be near infinity, and then the second resistance may be approximately R1.

In connection with the example of fig. 8, fig. 9 shows an example in which a switching unit is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, simply referred to as MOS transistor), and shows an implementation of the setting of the resistance adjustment module in the battery module. The loops corresponding to the positive electrode lug B1+ and the negative electrode lug B-are small-resistance loops, and the loops corresponding to the positive electrode lug B2+ and the negative electrode lug B-are large-resistance loops. It should be noted that in different implementations, the MOS transistor may be an N-channel MOS transistor, a P-channel MOS transistor, or other types of MOS transistors. In this example, an N-channel MOS transistor is taken as an example for illustration.

As shown in fig. 9, the point 71 and the point 72 may be disposed close to the cathode tab b1+ outflow/inflow. For example, the point 71 may be an isoelectric point of the positive tab b1+. Point 72 may be closer to positive tab b1+ than point 71. A resident resistor R1 may be provided in series between the point 71 and the point 72. A MOS transistor Q1 may be further provided in series between the point 71 and the point 72. Resistor R1 and MOS transistor Q1 may thus be arranged in a parallel configuration between points 71 and 72.

Specifically, the drain (D-pole) of MOS transistor Q1 may be connected to point 72. The source (S-pole) of MOS transistor Q1 may be connected to point 71. The gate (G pole) of the MOS transistor Q1 may be connected to the processor of the electronic device through an idle pin (NC pin) on the BTB connector. Therefore, the processor can adjust and manage the working state of the MOS transistor Q1 through the G electrode, such as on or off.

In the embodiment of the application, the processor of the electronic device can manage the working state of the MOS tube Q1 according to the working parameters of the battery module. By way of example, the operating parameters of the battery module may include at least one of: the number of times of charging the battery, the charging time of the battery, and the resistance difference of two loops (such as a small resistance loop and a large resistance loop) in the charging process.

In some embodiments, the operating state of the MOS transistor Q1 is managed by the number of times (or referred to as the number of turns) of the battery. The primary charging may correspond to an operation of charging the battery module by a user through the charger. In some implementations, the one-time charge may be an effective charge, e.g., a charging process with a continuous charge time greater than a preset effective charge duration may be referred to as a one-time charging process. The processor can record the charging times, and when the charging times are smaller than a preset charging times threshold value, the MOS tube Q1 is controlled to work in a conducting state. Correspondingly, when the charging frequency is greater than a preset charging frequency threshold value, the processor can control the MOS tube Q1 to work in a cut-off state.

It can be understood that, when the MOS transistor Q1 is operated in the on state, the resistor connected in series on the small-resistance loop corresponds to the on internal resistance of the MOS transistor and the parallel effect (such as the first resistor) of the resistor R1. That is, in this state, the resistance connected in series to the small-resistance circuit is smaller than R1. In connection with the examples of fig. 4 and 5, the bias current situation is not severe in the case of a small number of charges (e.g., just started charging). Therefore, by connecting a resistance smaller than R1 in series in a small-resistance loop, the difference in resistance between the two loops can be reduced. Thereby reducing the bias current ratio and the difference of temperature difference of the two loops.

Correspondingly, when the MOS transistor Q1 is operated in the off state, the resistor connected in series on the small-resistor loop corresponds to an effect (such as the second resistor) close to the resistor R1. In connection with the examples of fig. 4 and 5, the bias current ratio and the temperature difference over the two loops are more pronounced in case of a higher number of charges (e.g. a period of time that has been charged). Therefore, by connecting the resistances close to R1 in series in a small-resistance loop, the difference in resistance between the two loops can be reduced more significantly. Thereby reducing the bias current ratio and the difference of temperature difference of the two loops.

In other embodiments, the operating state of the MOS transistor Q1 is managed by the charging time of the battery. The charging duration may be: and after the electronic equipment is activated, charging time is long. Alternatively, the charging duration may be: and after the battery module of the electronic equipment is replaced, charging time is long. A charging duration threshold may be preset in the electronic device. When the charging duration is less than the charging duration threshold, the processor may control the MOS transistor Q1 to operate in a conducting state, so as to connect a smaller resistor (e.g., the first resistor) in series on the small-resistor loop for adjustment. When the charging time is longer than the charging time threshold, the processor can control the MOS transistor Q1 to work in a cut-off state so as to connect a larger resistor (such as a second resistor) in series on the small-resistor loop for adjustment.

In other embodiments, the working state of the MOS transistor Q1 is managed by the difference between the resistances of the two loops (e.g., the small-resistance loop and the large-resistance loop) in the charging process. Under the condition that the resistance difference is smaller than a preset resistance difference threshold value, the processor can control the MOS tube Q1 to work in a conducting state so as to connect smaller resistors (such as a first resistor) in series on the small-resistance loop to carry out resistance adjustment of the loop. Under the condition that the resistance difference is larger than a preset resistance difference threshold value, the processor can control the MOS tube Q1 to work in a cut-off state so as to connect a larger resistor (such as a second resistor) in series on a small-resistance loop to carry out resistance adjustment of the loop.

As one implementation, the processor may obtain the resistance on at least one loop through the fuel gauge and determine the resistance of another loop according to a preset correspondence. The processor may also determine a difference in resistance across the loops based on the resistances across the two loops.

In connection with the previous description of the processing circuit, an electricity meter may be provided in the processing circuit. The electricity meter can be used for collecting the input/output current of each cell in the working process of the battery module. In this example, the electricity meter may also be used to obtain the resistance magnitude of the corresponding location on the processing circuit. For example, the meter may be used to obtain the resistance of a small resistance loop in real time as it is accessed into the processing link 21. As another example, the resistance of the process high resistance loop may be obtained in real time as the electricity meter is connected to the process link 22. It can be understood that, for a multi-cell battery module structure (such as a three-pole ear cell scheme), there is a fixed correspondence between the resistance of the small-resistance loop and the resistance of the large-resistance loop. The correspondence of resistances on the different loops may be stored in the electronic device in advance. Thus, the processor can determine the resistance on one loop based on the currently acquired resistance on the other loop and the correspondence. And thus the difference in resistance of the two loops can be determined. In other implementations, the processor may obtain the resistances on both loops by an electricity meter and determine the difference in resistances on the loops. In this way, the electronic device does not need to have the corresponding relation of the resistances in the different loops.

It should be noted that, in other embodiments, the processor of the electronic device may trigger and detect the working parameters of the battery module according to a preset time, so as to determine whether to activate the corresponding MOS transistor Q1 to adjust. For example, the preset time may be a number of charging turns, a charging duration, or the like.

Taking preset time as the number of charging turns, the working state of the MOS tube Q1 is managed by the resistance difference of two loops (such as a small resistance loop and a large resistance loop) in the charging process. For example, the number of charging turns corresponding to the preset timing may be set to 200. When the number of charging turns (or the number of times of charging) reaches an integral multiple of 200, the processor of the electronic device can acquire the resistance difference of the two loops through the fuel gauge, and then the working state of the current MOS tube Q1 is determined according to the scheme.

In addition, in other embodiments, the electronic device may further combine the working parameters of the above multiple different battery modules to comprehensively determine the working state of the MOS transistor Q1. For example, the electronic device may adjust the operating state of the MOS transistor Q1 to the off state when the charging frequency is greater than a preset charging frequency threshold and the charging time is greater than the charging time threshold, so that the second resistor is connected in series to the small-resistor loop.

As an example, please refer to fig. 10, which is a flowchart of a charging control method according to an embodiment of the present application. Through this scheme as shown in fig. 10, the processor of the electronic device can flexibly adjust the operating state of the MOS transistor Q1 according to the operating parameters of the battery module. Therefore, the resistance adjusting modules connected in series on the small-resistance loops can be equivalent to resistances of different sizes, and therefore resistance differences on different loops are adjusted under different charging conditions, and bias current ratio and temperature difference differences are reduced.

In this example, the operating parameters include the number of charges.

As shown in fig. 10, the scheme may include:

s1001, detecting that the electronic equipment starts to charge, and acquiring the current charging times.

For example, the number of charges may be obtained by the processor through an electricity meter. For example, each time the fuel gauge detects a charging current, it corresponds to counter +1. Thus, when the electronic device is detected to start charging, the processor can determine the current charging times by reading the value of the counter.

S1002, judging the magnitude relation between the current charging times and a preset charging times threshold value.

When the current charge number is smaller than the preset charge number threshold, S1003 is executed. When the current charge number is less than the preset charge number threshold, S1004 is performed.

S1003, controlling the MOS tube to work in a conducting state.

S1004, controlling the MOS tube to work in the cut-off state.

Thus, the processor can achieve the effect shown in fig. 11 by the scheme shown in fig. 10. For example, when the number of charging times is smaller than the threshold value of the number of charging times, the small-resistance loop is connected with a first resistor in series, and the first resistor corresponds to the parallel connection effect of the MOS tube conduction internal resistance R0 and the resistor R1. And when the charging times are greater than the charging times threshold value, a second resistor is connected in series on the small-resistance loop, and the second resistor corresponds to the parallel effect of the approximate resistor R1.

In the examples of fig. 8-11, the resistor adjustment module includes a switching unit (e.g., MOS transistor Q1) as an example. In other embodiments of the present application, the resistance adjustment module may further include more switching units, thereby achieving the effect of multi-stage adjustment. Taking the switching unit as an MOS tube as an example.

For example, in connection with fig. 12, N MOS transistors are taken as an example. The N MOS transistors can comprise MOS transistors Q1-Qn.

The S-pole of each MOS transistor may be connected to point 71, respectively. For example, the S-pole (e.g., S1) of the MOS transistor Q1 can be connected to the point 71, the S-pole (e.g., S2) of the MOS transistor Q2 can be connected to the point 71, and so on, the S-pole (e.g., sn) of the MOS transistor Qn can be connected to the point 71.

The D-pole of each MOS transistor may be connected to point 72, respectively. For example, the D-pole (e.g., D1) of MOS transistor Q1 may be connected to point 72, the D-pole (e.g., D2) of MOS transistor Q2 may be connected to point 72, and so on, the D-pole (e.g., dn) of MOS transistor Qn may be connected to point 72.

Thus, the N MOS transistors may be connected in parallel with the resistor R1 between the point 71 and the point 72, respectively.

The G poles of the N MOS tubes can be connected to the processor through one pin of the BTB connector. For example, the G pole (e.g., G1) of the MOS transistor Q1 may be connected to the processor through one pin of the BTB connector; the G pole (such as G2) of the MOS transistor Q2 can be connected to the processor through the other pin of the BTB connector; similarly, the D pole (e.g., dn) of MOS transistor Qn may be connected to point 72. Therefore, the processor can realize on-off control of the N MOS tubes through the G pole of each MOS tube. It can be understood that the larger the number of MOS transistors in the on state, the larger the on internal resistance R0 connected in parallel with the resistor R1.

Then, as shown in fig. 13, when all N MOS transistors are in the on state, the path where each MOS transistor is located is equivalent to an on internal resistance r0. Thus, the resistances in series between points 71 and 72 are parallel resistances of the resistor R1 and the N internal resistances R0. At this time, the resistance adjustment module may provide the smallest series resistance.

As shown in fig. 14, when all N MOS transistors are in the off state, the resistance connected in series between the point 71 and the point 72 is close to the resistance R1. At this time, the resistance adjustment module may provide the maximum series resistance.

It will be appreciated that the processor may adjust the resistance in series between points 71 and 72 by controlling the number of turn-on numbers in the N MOS transistors. For example, based on the state shown in fig. 13, each time the processor controls one MOS transistor to turn off, the resistance connected in series between the point 71 and the point 72 gradually increases. Until the processor controls all the MOS transistors to be turned off, thereby obtaining the state shown in fig. 14.

In the present application, based on the above description as shown in fig. 12 to 14, the electronic device may adjust the number of MOS transistors in on/off states according to the operating parameters of different battery modules. Thereby achieving a finer resistance adjustment effect than in the scheme shown in fig. 10. The implementation of the scheme for adjusting the on/off states of each MOS transistor according to the operating parameters of the battery module may refer to the implementation of the scheme provided with one MOS transistor (e.g., the MOS transistor Q1) described above, which will not be described in detail herein.

In the following examples, the operation mechanism of the resistance adjustment module provided with N MOS transistors is exemplarily described taking an example in which the operation parameters of the battery module include the number of times of charging (i.e., the number of charging turns) and the difference in resistance between the two loops.

Fig. 15 is a schematic flow chart of a charging control method according to an embodiment of the application. As shown in fig. 15, the scheme may include:

s1501, detecting that the electronic equipment starts to charge, and acquiring the current charging times.

In this example, the electronic device is in a first-time charging state (e.g., first-time charging after shipping), and the N MOS transistors are all turned on. Thereby allowing a minimum resistance to be placed in series between points 71 and 72.

The S1501 may be executed each time the electronic apparatus starts charging thereafter, i.e., the current number of times of charging is acquired. The processor of the electronic device may determine, for example, that charging is currently started by the fuel gauge, and determine the current number of charges based on a value of a counter for recording the number of charges. In this example, the scheme of specifically acquiring the current charge number may also refer to S1001 as shown in fig. 10.

S1502, when the charging times reach the first preset times, determining the resistance difference of the two loops.

The first preset number of times may be set to 400, for example. Then, when the number of charging times reaches the first preset number, the resistance difference between the two loops may be already large, and a significant bias current ratio or temperature rise difference is generated. In this case, the processor of the electronic device may obtain the difference in resistance on both loops by means of an electricity meter. The manner of obtaining the resistance difference may be as described above with reference to fig. 10.

And S1503, when the resistance difference between the two loops is larger than the first resistance difference, the processor controls the first number of MOS tubes to be in a cut-off state.

In this example, when the resistance difference between the two loops is greater than the first resistance difference, a certain number of MOS transistors may be triggered to be turned off, so as to increase the series resistance between the point 71 and the point 72. The effect of reducing the resistance difference of the two loops is achieved.

S1504, when the charging times reach a second preset times, determining the resistance difference of the two loops.

In S1505, when the resistance difference between the two loops is greater than the second resistance difference, the processor controls the second number of MOS transistors to be in the off state.

The second preset number of times may be set to 600, for example. Then, when the number of charges reaches the second preset number, the resistance difference between the two loops may be at a larger level again, thereby generating a more significant bias current ratio or temperature rise difference. In this case, the processor of the electronic device may trigger again the adjustment of the magnitude of the series resistance connected in series on the small resistance loop. For example, when the resistance difference is greater than the second resistance difference, a greater number of MOS transistors (e.g., a second number) are controlled to be in an off state. Thereby further increasing the magnitude of the resistance in series between points 71 and 72. The effect of reducing the resistance difference of the two loops is achieved.

In some embodiments, the first resistance difference and the second resistance difference may be the same. In other embodiments, the first resistance difference and the second resistance difference may be set to different values according to actual situations.

Note that, as in the example of fig. 15, the description is given taking as an example the adjustment performed twice according to the number of charging times. In other embodiments of the present application, after performing the adjustment twice, the electronic device may further control more MOS transistors to be in the off state under the condition of more subsequent charging times. Thereby achieving multi-stage adjustment.

For example, table 1 below shows an example of a scheme for four-level adjustment.

TABLE 1

Number of times of charging	Small resistance loop resistance	Large resistance loop resistance	Resistance difference	Number of MOS transistors disconnected
					0	16	30	14	0
200	18	32	14	0
					400	20	35	15	1
600	22	38	16	2
					800	24	42	18	4
1000	26	45	19	5

In the example of table 1, the small resistance loop resistance may be 16 ohms when not charged. The large resistance loop resistance may be 30 ohms. The difference in resistance was 14 ohms at this time. The electronic device can determine that the bias current is not serious, and does not need to be adjusted, namely, all MOS tubes are kept on. Similarly, before the 200 th charging, the electronic device may determine that the bias current is not severe, and need not be adjusted, i.e. keep all MOS transistors on.

When the number of charging times reaches a first preset number (e.g. 400), the electronic device may determine that the bias current starts to become significant, and needs to adjust the resistance on the small-resistance loop, for example, to turn the working state of one MOS transistor into the off state. Therefore, the resistance of the resistance adjusting module connected in series on the small resistance loop can be equivalent to the parallel resistance of the resistance R1 and the internal resistances of the N-1 MOS tubes. Therefore, the resistance difference between the small resistance loop and the large resistance loop in the current situation is reduced, and the damage of larger bias current to the battery is avoided.

When the number of charging times continues to increase and reaches a second preset number of times (e.g., 600), the electronic device may determine that the bias current begins to become significant again, and needs to adjust the resistance on the small-resistance loop, for example, to turn the working states of the two MOS transistors into an off state. Therefore, the resistance of the resistance adjusting module connected in series on the small resistance loop can be equivalent to the parallel resistance of the resistance R1 and the internal resistances of the N-2 MOS tubes. Therefore, the resistance difference between the small resistance loop and the large resistance loop in the current situation is reduced, and the damage of larger bias current to the battery is avoided.

In the example shown in table 1, the electronic device may further be provided with a third preset number of times (e.g. 800) and a fourth preset number of times (e.g. 1000), and based on the relationship between the number of charging times and the preset number of times, the MOS transistor operating state is adjusted according to the mechanism shown in table 1. Therefore, as the charging times are increased, the number of MOS tubes in an off state is increased, and the resistor connected in series with the small resistor loop is more and more close to the resident resistor R1. Therefore, the multi-stage adjustment of the resistance on the small-resistance loop can be realized, and the resistance difference on the two loops is correspondingly adjusted under different charging conditions, so that the damage of larger bias current to the battery is more accurately avoided.

Therefore, through the scheme example shown in fig. 1, the on/off state of the MOS transistor can be flexibly controlled according to the resistance difference between the two loops, so that the resistances connected in series to the small-resistance loop are adjusted, and the resistances of the small-resistance loop under different conditions can be close to or equal to the circuit on the large-resistance loop. This avoids significant bias currents due to excessive resistance differences.

In the above examples, implementation of the three-pole ear cell scheme is taken as an example. In other embodiments, when more cells (e.g., M cells) are included in the battery module, the resistance adjustment module in the above example may be provided on at least one of the M-1 loops other than the loop with the largest impedance. Thus, based on the mechanism shown in fig. 10 or 15, the resistance difference between at least one loop and other loops is reduced, the bias current is balanced, and damage to the battery module caused by the bias current is reduced.

It should be understood that the foregoing describes the solution provided by the embodiments of the present application mainly from the perspective of the electronic device. To achieve the above functions, it includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can divide the functional modules of the devices involved in the method according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

As an example, please refer to fig. 16, which is a schematic diagram illustrating a composition of another electronic device according to an embodiment of the present application. The electronic device 1600 may be provided therein with a battery module 1603 as provided in the foregoing example. The battery module 1603 may include at least three tabs, and the at least three tabs may include at least one negative tab. A resistance adjustment module as shown in fig. 7 to 9 or fig. 12 may be provided on at least one circuit in the battery module 1603. The electronic device 1600 may further include: a processor 1601, and a memory 1602. The memory 1602 is used to store computer-executable instructions. For example, in some embodiments, the processor 1601, when executing instructions stored in the memory 1602, may cause the electronic device 1600 to perform any of the technical solutions described in relation to the embodiments above.

It should be noted that, all relevant contents of each step related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

Fig. 17 shows a schematic diagram of the composition of a chip system 1700. The chip system 1700 may include: a processor 1701 and a communication interface 1702 for supporting the relevant devices to implement the functions referred to in the above embodiments. In one possible design, the system on a chip also includes memory to hold the necessary program instructions and data for the terminal. The chip system can be composed of chips, and can also comprise chips and other discrete devices. It should be noted that, in some implementations of the present application, the communication interface 1702 may also be referred to as an interface circuit. The system-on-chip 1700 may cause the electronic device to perform battery charging according to the scheme shown in fig. 10 or 15 by executing instructions stored therein.

The functions or acts or operations or steps and the like in the embodiments described above may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A battery module, characterized in that the battery module comprises an electric core;

the battery cell comprises a battery cell body, a first electrode lug, a second electrode lug and a third electrode lug; the first electrode lug, the second electrode lug and the third electrode lug are respectively and electrically connected with the battery cell body; the first tab and the third tab have a first polarity, and the second tab has a second polarity;

the second tab and the first tab, and the corresponding first processing link correspond to a first loop capable of inputting or outputting voltage and current to or from the cell body;

The third tab and the first tab, and the corresponding second processing link correspond to a second loop, the first loop being capable of inputting voltage and current to the cell body or capable of outputting voltage and current from the cell body;

the resistance of the first loop is smaller than the resistance of the second loop;

the first loop is provided with a resistance adjusting module, and the resistance adjusting module is used for increasing the resistance of the first loop.

2. The battery module of claim 1, wherein the resistance adjustment module is equivalent to a first resistance in a first state of charge and the resistance adjustment module is equivalent to a second resistance in a second state of charge;

the first charging state is smaller than the second charging state in charging times, and the first resistance is smaller than the second resistance.

3. The battery module according to claim 1 or 2, wherein,

the resistance adjusting module comprises a resident resistor R1 and at least one switching unit, and a first switching unit and the resident resistor R1 are arranged on the first loop in parallel; the first switching unit is included in the at least one switching unit;

The working states of the first switching unit comprise a first working state and a second working state, the equivalent resistance of the first switching unit in the first working state is a third resistance, the equivalent resistance of the first switching unit in the second working state is a fourth resistance, and the third resistance is smaller than the fourth resistance.

4. The battery module according to claim 3, wherein,

the first switching unit comprises a first MOS tube, the first working state corresponds to the conducting state of the first MOS tube, and the second working state corresponds to the cutting-off state of the first MOS tube.

5. The battery module of claim 3 or 4, wherein the resistance adjustment module further comprises a second switching unit in parallel relationship with the first switching unit and the resident resistor R1.

6. The battery module of any one of claims 1-5, wherein the cell further comprises a fourth tab having the first polarity, the fourth tab corresponding to the second tab a third loop capable of inputting or outputting voltage and current to or from the cell body.

7. The battery module according to claim 6, wherein the third circuit has a resistance smaller than that of the second circuit, and the resistance adjustment module is provided on the third circuit for increasing the resistance of the third circuit.

8. The battery module of claim 1 or 6, wherein the first polarity is a positive polarity and the second polarity is a negative polarity; alternatively, the first polarity is a negative polarity and the second polarity is a positive polarity.

9. A charging control method, characterized in that the method is applied to an electronic device in which the battery module according to any one of claims 1 to 8 is provided, the method comprising:

when the electronic equipment starts to charge, the electronic equipment acquires the working parameters of the battery module,

and according to the working parameters, the electronic equipment adjusts the resistance of the resistance adjusting module in the battery module so as to increase the resistance of a loop in which the resistance adjusting module is positioned.

10. The method of claim 9, wherein the operating parameters of the battery module include at least one of:

The charging times and the charging time are long, and the resistance difference of the first loop and the second loop is generated in the charging process; the first loop is a loop corresponding to a first tab and a second tab in the battery module, the second loop is a loop corresponding to a third tab and the second tab in the battery module, the polarities of the first tab and the third tab are the same, and the polarities of the second tab are different from those of the first tab.

11. The method of claim 10, wherein the operating parameters of the battery module include the number of charges,

the electronic equipment obtains the working parameters of the battery module, and the method comprises the following steps:

the electronic equipment acquires the current charging times;

according to the working parameters, the electronic device adjusts the resistance of the resistance adjustment module in the battery module, and the resistance adjustment module comprises:

and under the condition that the current charging times are larger than a preset charging times threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

12. The method according to claim 10 or 11, wherein the operating parameters of the battery module include a charge duration,

the electronic equipment acquires the current charging time length;

and under the condition that the current charging time length is larger than a preset charging time length threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

13. The method according to any one of claims 10 to 12, wherein the operating parameters of the battery module include a difference in resistance of the first circuit and the second circuit,

the electronic equipment acquires the current resistance difference;

and under the condition that the current resistance difference is larger than a preset resistance difference threshold value, the electronic equipment switches the working state of at least one MOS tube in the resistance adjustment module from an on state to an off state.

14. The method according to any one of claims 9-13, wherein before the electronic device adjusts the resistance of the resistance adjustment module in the battery module according to the operating parameter, the method further comprises:

the electronic equipment determines that the current charging times are larger than a first preset times.

15. The method according to any one of claims 9-14, further comprising:

and under the condition that the current charging times are greater than the second preset times, the electronic equipment adjusts the resistance of a resistance adjustment module in the battery module according to the working parameters, so that the continuous resistance of a loop in which the resistance adjustment module is positioned is increased.

16. An electronic apparatus, characterized in that the battery module according to any one of claims 1 to 8 is configured to perform the charge control method according to any one of claims 9 to 15 when the electronic apparatus is charged.