CN114415776A

CN114415776A - Band-gap reference voltage source circuit and electronic device

Info

Publication number: CN114415776A
Application number: CN202011173865.XA
Authority: CN
Inventors: 张现聚; 刘铭
Original assignee: Shanghai Geyi Electronic Co ltd; GigaDevice Semiconductor Beijing Inc
Current assignee: Shanghai Geyi Electronic Co ltd; GigaDevice Semiconductor Beijing Inc
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2022-04-29
Anticipated expiration: 2040-10-28
Also published as: CN114415776B

Abstract

The application discloses band gap reference voltage source circuit and electronic device. The band-gap reference voltage source circuit can realize that the band-gap reference voltage is not limited by the change influences of process, temperature and the like, and can adjust the range of the band-gap reference voltage within a certain range, thereby enhancing the design flexibility of the band-gap reference voltage source circuit. Meanwhile, the range based on the band-gap reference voltage is large, the adjustable range of the output voltage of the band-gap reference voltage source circuit is correspondingly large, and therefore the yield of the circuit is improved. In addition, the branch current of the output branch of the band-gap reference voltage source circuit is large, and the anti-noise performance can be improved. Furthermore, the plurality of selection switches arranged in the output branch adopt NMOS tubes, so that the circuit and the connection can be simplified. The same is true for the electronic device adopting the circuit.

Description

Band-gap reference voltage source circuit and electronic device

Technical Field

The present disclosure relates to electronic technologies, and particularly to a bandgap reference voltage source circuit and an electronic device.

Background

The reference voltage source is generally used to provide a stable reference voltage for other circuits, and the voltage reference value provided by the reference voltage source is slightly affected by process, temperature and power supply variations. Therefore, the reference voltage source plays a very important role in chip circuit design. A common reference voltage source is, for example, a bandgap reference voltage source. In power supply applications with relatively high output voltages, such as 2.5V or 1.8V, the bandgap reference voltage is typically 1.2V. With the low voltage application of the power supply voltage, the bandgap reference voltage source circuit is also under continuous improvement to generate a bandgap reference voltage (or referred to as a reference voltage, hereinafter the same) with lower power consumption and lower voltage value, for example, a bandgap reference voltage below 1V. In practical industrial applications, in order to improve the yield of products, the bandgap reference voltage needs to have a flexible adjustable range.

However, in practice, the conventional low-voltage bandgap reference voltage range cannot be flexibly adjusted due to the limitation of the process parameters of the electronic components.

In view of the above, how to realize flexible adjustment of the bandgap reference voltage range becomes an important research project for relevant researchers or developers.

Disclosure of Invention

The embodiment of the application provides a band-gap reference voltage source circuit and an electronic device. The band-gap reference voltage source circuit can adjust the size of band-gap reference voltage within a certain range, so that the design flexibility of the band-gap reference voltage source circuit is enhanced. Meanwhile, the range based on the band-gap reference voltage is large, the adjustable range of the output voltage is correspondingly large when the band-gap reference voltage source circuit is produced in a mass mode, and therefore the yield of the circuit is improved. In addition, the branch current of the output branch of the band-gap reference voltage source circuit is large, and the anti-noise performance can be improved. Furthermore, the plurality of selection switches arranged in the output branch adopt NMOS tubes, so that the circuit and the connection can be simplified. The same is true for the electronic device adopting the circuit.

According to a first aspect of the present application, there is provided a bandgap reference voltage source circuit comprising: the reference current generation module is used for outputting a reference current positively correlated with the temperature; a first resistor; a transistor, a first pole of the transistor is connected with an output node of the reference current generation module through the first resistor; and a second resistor, a first end of the second resistor being connected to the control electrode of the transistor, a second end of the second resistor and a second electrode of the transistor being connected to a common potential.

On the basis of the technical scheme, the method can be further improved.

Optionally, a second terminal of the second resistor and a second pole of the transistor are grounded.

Optionally, the second resistor is an adjustable resistor.

Optionally, the transistor is a PMOS transistor.

Optionally, the transistor is a PNP triode, the first pole of the transistor is an emitter, and the second pole of the transistor is a collector.

Optionally, the second resistor includes a plurality of second sub-resistors connected in series between the control electrode and the second electrode of the transistor, and a bypass path bypassing at least one of the plurality of second sub-resistors based on a selection signal.

Optionally, the bypass path includes a plurality of bypass switches controlled by a selection signal, a first end of each bypass switch is connected to a first end of the corresponding second sub-resistor, and a second end of each bypass switch is connected to a second end of the corresponding second sub-resistor.

Optionally, the bypass path includes a plurality of bypass switches controlled by a selection signal, each of the second sub-resistors has a first end close to the control electrode of the transistor and a second end close to the second electrode of the transistor, the first end of each of the bypass switches is connected to the second electrode of the transistor, and the second end of each of the bypass switches is connected to the first end of the corresponding second sub-resistor.

Optionally, the bypass path includes a plurality of bypass switches controlled by a selection signal, each of the second sub-resistors has a first end close to the control electrode of the transistor and a second end close to the second electrode of the transistor, the first end of each of the bypass switches is connected to the control electrode of the transistor, and the second end of each of the bypass switches is connected to the second end of the corresponding second sub-resistor.

Optionally, the bypass switch is a MOS transistor switch.

Optionally, the bandgap reference voltage source circuit further includes a third resistor, a first end of the third resistor is connected to the output node of the reference current generating module, and a second end of the third resistor is connected to the control electrode of the transistor.

Optionally, the bandgap reference voltage source circuit further includes a plurality of third sub-resistors connected in series between the output node of the reference current generating module and the control electrode of the transistor, and each of the third sub-resistors includes a first end close to the output node of the reference current generating module and a second end close to the control electrode of the transistor.

Optionally, the bandgap reference voltage source circuit further includes a plurality of selection switches, a first end of each selection switch is connected to a first end of the corresponding third sub-resistor, a second end of each selection switch is connected to a common node, and the common node is a connection node between the second resistor and the third sub-resistor close to the control electrode of the transistor.

Optionally, the reference current generation module comprises a proportional to absolute temperature current generation circuit.

Optionally, the proportional to absolute temperature current generating circuit comprises a transistor operating in a sub-threshold region.

According to a second aspect of the present application, there is also provided a bandgap reference voltage source circuit comprising: a proportional to absolute temperature current generating circuit; a first branch; and a second branch, the first branch and the second branch being connected in parallel between the output node of the proportional to absolute temperature current generating circuit and ground, the first branch including a first resistor and a transistor for providing a voltage complementary to absolute temperature, a first end of the first resistor being connected to the output node of the proportional to absolute temperature current generating circuit, a second end of the first resistor being connected to a first pole of the transistor, a second pole of the transistor being connected to ground, the second branch including a second resistor and a third resistor connected in series between the output node of the proportional to absolute temperature current generating circuit and ground, a control pole of the transistor being connected to a common node of the second resistor and the third resistor.

Optionally, the second resistor is an adjustable resistor.

According to a third aspect of the present application, there is also provided an electronic device comprising the above bandgap reference voltage source circuit.

Optionally, the electronic device is a non-volatile memory.

The band-gap reference voltage source circuit can realize that the band-gap reference voltage is not limited by the change influences of process, temperature and the like, and the range size of the band-gap reference voltage can be adjusted randomly within a certain range, so that the design flexibility of the band-gap reference voltage source circuit is enhanced. And the range based on the band-gap reference voltage is larger, and the adjustable range of the output voltage is correspondingly larger when the band-gap reference voltage source circuit is produced in a mass mode, so that the yield of the circuit is improved. In addition, the branch current of the output branch of the band-gap reference voltage source circuit is large, and the anti-noise performance can be improved. Furthermore, the plurality of selection switches arranged in the output branch adopt NMOS tubes, so that the circuit and the connection can be simplified. The same is true for the electronic device adopting the circuit.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a bandgap reference voltage source circuit according to an embodiment of the present application.

Fig. 2A is a schematic structural diagram of a bandgap reference voltage source circuit in another embodiment of the present application.

Fig. 2B is another structural schematic diagram of a bandgap reference voltage source circuit in another embodiment of the present application.

Fig. 2C is a schematic diagram of another bandgap reference voltage source circuit according to another embodiment of the present application.

Fig. 3 is a schematic structural diagram of a bandgap reference voltage source circuit in another embodiment of the present application.

Fig. 4 is a schematic structural diagram of another embodiment of the reference current generating module shown in fig. 1.

Fig. 5 is a schematic structural diagram of another embodiment of the reference current generating module shown in fig. 1.

FIG. 6 is a diagram illustrating the effect of the bandgap reference voltage source circuit in the embodiment of the present application.

FIG. 7 is a diagram illustrating the effect of the bandgap reference voltage source circuit in the embodiment of the present application.

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as being fixed or detachable or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

The application provides a band gap reference voltage source circuit, it includes: the reference current generation module is used for outputting a reference current positively correlated with the temperature; a first resistor; a transistor, a first pole of which is connected with the output node of the reference current generation module through the first resistor, and a second pole of which is grounded; and a second resistor, wherein a first end of the second resistor is connected with the control electrode of the transistor, and a second end of the second resistor is connected with the second electrode of the transistor. The first resistor and the transistor may form a first branch, and the second resistor may form a second branch (or called an output branch, the same applies hereinafter). In some embodiments, the connection relationship between the first resistor in the first branch and the transistor and the second resistor in the second branch is reasonably designed, so that the size of the bandgap reference voltage can be adjusted correspondingly by changing the resistance value of the second resistor, and the temperature coefficient of the bandgap reference voltage is not affected, thereby enabling great flexibility in setting of the bandgap reference voltage. In addition, the second resistor can be improved and designed into a plurality of second sub-resistors and a plurality of bypass switches for matching use, so that the branch current of the second branch circuit is adjusted to a larger current value, and the noise resistance performance is better. Furthermore, by providing a plurality of third sub-resistors and a plurality of selection switches in the second branch to trim (trim) the output voltage of the second branch, the output voltage related to the bandgap reference voltage can be brought to the design target value by performing the trimming operation even though the bandgap reference voltage may deviate from the predetermined value due to process variations. Furthermore, the selection switch for performing trimming operation can adopt NMOS tube, thereby simplifying circuit and connection.

An embodiment of the present application provides a bandgap reference voltage source circuit, which includes: the reference current generating module, the first resistor, the transistor and the second resistor. The reference current generation module is used for outputting a reference current positively correlated with the temperature. The first resistor is connected in series with the transistor and forms a first branch circuit. The first end of the first resistor is connected to the output node of the reference current generation module, and the second end of the first resistor is connected to the first pole of the transistor. The second and control electrodes of the transistor are grounded. The first end of the second resistor is connected with the control electrode of the transistor, and the second end of the second resistor is connected with the second electrode of the transistor.

Specifically, in this embodiment, the transistor may be a PNP transistor. That is, the first pole of the transistor is the emitter and the second pole of the transistor is the collector. Of course, in other embodiments, the transistors may be other types of transistors, such as PMOS transistors described below, without limitation.

Further, in this embodiment, the second resistor may be connected to the output node of the reference current generating module through a third resistor. That is, the first terminal of the third resistor is connected to the output node of the reference current generating module, and the second terminal of the third resistor is connected to the first terminal of the second resistor. The second terminal of the second resistor is connected to the second pole (here the collector) of the transistor. The second resistor and the third resistor form a second branch circuit. The resistance value of the branch resistor (i.e. the equivalent resistor) of the second branch is equal to the sum of the resistance value of the second resistor and the resistance value of the third resistor.

Since the proportional absolute temperature current generating circuit in the reference current generating module generates a reference current positively correlated to temperature (i.e. positive temperature coefficient), and the transistor in the first branch connected to the output node of the reference current generating module can generate a voltage complementary to the positive temperature coefficient, the bandgap reference voltage source circuit can generate a bandgap reference voltage (or referred to as reference voltage, the same as below) with zero temperature coefficient. The bandgap reference voltage is equal to the sum of the voltage generated by the first resistor and the voltage generated by the transistor.

Further, by utilizing different taps of the third resistor, an output voltage associated with the bandgap reference voltage and having a certain adjustable range can be generated.

Through research, in the bandgap reference voltage source circuit of this embodiment, the output voltage of the second branch has a certain adjustable range. However, the resistance of the branch resistor in the second branch is very large, for example, more than 3 mega ohms, which may occupy a large area of the circuit layout. Furthermore, the current value of the branch current in the second branch is very small, for example less than 0.2 μ a, about a quarter of the proportion of the reference current (here 0.8 μ a), which is susceptible to circuit noise interference. In order to increase the current value of the branch current of the second branch, if the branch resistance of the second branch is reduced to about 1 mega ohm, the current value of the branch current of the second branch can be ensured to be relatively large, which is about over half of the reference current, but the output voltage is 0.51V at this time. Considering the process deviation of the transistor in the first branch, if the voltage value of the output voltage is too small, the use in the actual current is limited, and thus the use of the subsequent circuit is inconvenient.

Therefore, it is further improved on the basis of the above-described bandgap reference voltage source circuit, and a bandgap reference voltage source circuit as described below is provided.

Referring to fig. 1, in an embodiment of the present application, the bandgap reference voltage source circuit 100 includes: the reference current generating module 110, the first branch circuit 120, and the second branch circuit 130 have a Proportional To Absolute Temperature (PTAT) current generating circuit. Specifically, the bandgap reference voltage source circuit 100 includes: a PTAT current generating circuit, a first branch 120 and a second branch 130. Wherein the first branch 120 and the second branch 130 are connected in parallel between the output node a of the PTAT current generating circuit and the ground GND, the first branch 120 includes a first resistor R1 and a transistor P4 for providing a voltage complementary to the absolute temperature in series. The first end of the first resistor R1 is connected to the output node A of the PTAT current generating circuit, and the second end of the first resistor R1 is connected to the first pole of the transistor P4. That is, the first pole of the transistor P4 is connected to the output node a of the PTAT current generation circuit through the first resistor R1. In addition, the second pole of the transistor P4 is connected to ground GND. In this embodiment, the transistor P4 is a PMOS transistor, i.e., the source and substrate terminals of the transistor P4 are connected to the second terminal of the first resistor R1, the drain of the transistor P4 is grounded, and the gate of the transistor P4 is connected to the first terminal of the second resistor R2 described below. The transistor P4 operates in the saturation region. In other embodiments, the transistor P4 may be a PNP transistor, the branch current flowing through the second branch is greater than the branch current flowing through the first branch, the amplification factor (β) of the PNP transistor is large enough, and the base current is much smaller than the branch current of the second branch.

With continued reference to fig. 1, the second branch 130 includes a second resistor R2 and a third resistor R3 connected in series between the output node a of the reference current generating module 110 and the ground GND, and the control electrode of the transistor P4 is connected to the common node B of the second resistor R2 and the third resistor R3. Specifically, a first end of the second resistor R2 is connected to the control electrode of the transistor P4 and the third resistor R3, respectively, and a second end of the second resistor R2 is connected to the second electrode of the transistor P4. The second pole of the transistor P4 is grounded, and therefore, the second terminal of the second resistor R2 is also grounded. The branch resistance Rt (i.e., equivalent resistance) of the second branch 130 is equal to the sum of the resistance of the second resistor R2 and the resistance of the third resistor R3.

Referring to fig. 1, the voltage Vbgh of the first terminal of the first resistor R1 is equal to the sum of the voltage across the first resistor R1, the source-gate voltage of the transistor P4, and the gate-drain voltage of the transistor P4. The source-gate voltage of transistor P4 has a negative temperature coefficient. In the present embodiment, the second resistor R2 is an adjustable resistor. When the second resistor R2 is adjusted, the voltage between the gate and the drain of the transistor P4 changes accordingly, thereby changing the voltage Vbgh.

Preferably, the second resistor R2 includes a plurality of second sub-resistors (R2a, R2b, R2c, etc.) and the bypass path 131. The plurality of second sub-resistors (R2a, R2b, R2c, etc.) are connected in series between a control electrode (here, a gate) and a second electrode (here, a drain) of the transistor P4, and the bypass path 131 bypasses at least one of the plurality of second sub-resistors (R2a, R2b, R2c, etc.) based on a selection signal.

As shown in fig. 2A, in some embodiments, the bypass path 131 includes a plurality of bypass switches controlled by a selection signal (S1, S2 … Sn). The first end of each bypass switch (S1, S2 … Sn) is connected with the first end of the corresponding second sub-resistor, and the second end of each bypass switch (S1, S2 … Sn) is connected with the second end of the corresponding second sub-resistor.

In some embodiments, as shown in fig. 2B, the bypass path 131 includes a plurality of bypass switches (S1, S2 … Sn) controlled by a selection signal, each of the second sub-resistors (R2a, R2B, R2c, etc.) has a first end close to the gate of the transistor P4 and a second end close to the second pole of the transistor P4, the first end of each of the bypass switches (S1, S2 … Sn) is connected to the second pole of the transistor P4, and the second end of each of the bypass switches (S1, S2 … Sn) is connected to the first end of the corresponding one of the second sub-resistors (R2a, R2B, R2c, etc.).

In other embodiments, as shown in fig. 2C, the bypass path 131 includes a plurality of bypass switches (S1, S2 … Sn) controlled by a selection signal, each of the second sub-resistors (R2a, R2b, R2C, etc.) has a first end close to the gate of the transistor P4 and a second end close to the second pole of the transistor P4, the first end of each of the bypass switches (S1, S2 … Sn) is connected to the gate of the transistor P4, and the second end of each of the bypass switches (S1, S2 … Sn) is connected to the second end of the corresponding one of the second sub-resistors (R2a, R2b, R2C, etc.).

As shown in fig. 2A, 2B, and 2C, different configurations of the bypass path 131 are shown. Further, in the above embodiment, the bypass switch (S1, S2 … Sn) may be a MOS switch, and the resistance of the equivalent resistor has almost no influence on the resistance of the branch resistor Rt (or equivalent resistor) corresponding to the second branch 130. Of course, in other embodiments, the bypass switch (S1, S2 … Sn) may also be another switch with a very low resistance value, so as to avoid affecting the resistance value of the branch resistor Rt corresponding to the second branch 130.

Compared to the above-mentioned transistor in the first branch 120 using a PNP transistor, in the present embodiment, the transistor P4 uses a PMOS transistor, and considering that the voltage between the source and the gate of the PMOS transistor has a negative temperature coefficient, an output voltage Vbgh independent of temperature can be obtained, and Vbgh can be adjusted by the second resistor.

Continuing with fig. 1, in this embodiment, the PTAT current generation circuit may generate a current Proportional To Absolute Temperature (PTAT). The circuit comprises a first P-type current mirror and a first N-type current mirror; the first end of the first P-type current mirror is connected with a power supply end VDD, and the second end of the first P-type current mirror is connected with the first end of the first N-type current mirror; and the second end of the first N-type current mirror is grounded. Further, the first P-type current mirror includes a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3; the first N-type current mirror comprises a first NMOS transistor N1 and a second NMOS transistor N2; the PTAT circuit further comprises a reference resistor Rref; one end of the reference resistor Rref is connected with the source electrode of the second NMOS transistor N2, and the other end of the reference resistor Rref is grounded; the drain electrode of the first NMOS transistor N1 is respectively connected with the drain electrode of the first PMOS transistor P1, the gate electrode of the first NMOS transistor N1 and the gate electrode of the second NMOS transistor N2; the drain electrode of the second NMOS transistor N2 is respectively connected with the gate electrode of the first PMOS transistor P1, the gate electrode of the second PMOS transistor P2, the drain electrode of the second PMOS transistor P2 and the gate electrode of the third PMOS transistor P3; the drain of the third PMOS transistor P3 is connected in proportion to the output node a of the absolute temperature current generation (PTAT) circuit. In some embodiments, the bandgap reference voltage source circuit further comprises a start-up (startup) circuit for generating an initial voltage of the node PB and an initial voltage of the node NB. Note that the output node a of the PTAT current generation circuit serves as the output node of the reference current generation module 110.

Of course, the form of the PTAT current generation circuit is not limited to the form shown in fig. 1, and may take other forms as long as it can generate a current of a positive temperature coefficient. In some other embodiments, the first PMOS transistor P1 and the second PMOS transistor P2 may adopt a cascode structure to improve the effect of the trench length adjustment, as shown in fig. 4. Alternatively, in some other embodiments, the current proportional to the absolute temperature is generated by a PMOS transistor, and the first NMOS transistor N1 and the second NMOS transistor N2 adopt a cascode structure, as shown in fig. 5.

Specifically, referring to fig. 4, the PTAT current generation circuit 140 includes a first P-type current mirror and a first N-type current mirror. Wherein the first P-type current mirror comprises 3 branches. The first branch circuit comprises a first PMOS tube P1 and a fifth PMOS tube P5, the second branch circuit comprises a second PMOS tube P2 and a sixth PMOS tube P6, and the third branch circuit comprises a third PMOS tube P3 and a seventh PMOS tube P7. The sources of the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 are connected with a power supply end VDD, and the gates of the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 are connected with a common node PB 1. The source electrode of the fifth PMOS tube P5 is connected with the drain electrode of the first PMOS tube P1, the source electrode of the sixth PMOS tube P6 is connected with the drain electrode of the second PMOS tube P2, the source electrode of the seventh PMOS tube P7 is connected with the drain electrode of the third PMOS tube P3, and the grid electrodes of the fifth PMOS tube P5, the sixth PMOS tube P6 and the seventh PMOS tube P7 are connected with the common node PB 2. The first N-type current mirror includes a first NMOS transistor N1, a second NMOS transistor N2, and a reference resistor Rref. The drain of the first NMOS transistor N1 is connected to the drain of the fifth PMOS transistor P5, and the drain of the second NMOS transistor N2 is connected to the drain of the sixth fifth PMOS transistor P6. The grid electrode of the first NMOS transistor N1, the grid electrode of the second NMOS transistor N2 and the drain electrode of the second NMOS transistor N2 are connected with the common node NB. The source of the first NMOS transistor N1 is grounded. One end of the reference resistor Rref is connected with the source electrode of the second NMOS transistor N2, and the other end of the reference resistor Rref is grounded. The drain of the seventh PMOS transistor P7 is connected to the output node a of the PTAT current generating circuit 140.

In addition, as shown in fig. 4, the reference current generating module 110 with the PTAT current generating circuit 140 further includes a self-bias voltage generating circuit 150. The PTAT current generation circuit 140 is connected to the self-bias voltage generation circuit 150. Specifically, the first output terminal of the self-bias voltage generating circuit 150 is respectively connected to the gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2, and the gate of the third PMOS transistor P3; a second output terminal of the self-bias voltage generating circuit 150 is respectively connected to the gate of the fifth PMOS transistor P5, the gate of the sixth PMOS transistor P6 and the gate of the seventh PMOS transistor P7; the input end of the self-bias voltage generating circuit 150 is respectively connected to the drain of the first NMOS transistor N1 and the drain of the fifth PMOS transistor P5. The self-bias voltage generating circuit 150 is configured to obtain a drain voltage of the first NMOS transistor N1, and output a first bias power supply voltage PB1 and a second bias power supply voltage PB2, respectively. In addition, a bias voltage NB is applied to a connection point between the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2.

Specifically, referring to fig. 5, the PTAT current generation circuit 140 includes: the transistor comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4 and a reference resistor Rref. The source electrode of the first PMOS tube P1 is respectively connected with a power supply end VDD, one end of a reference resistor Rref and the source electrode of a third PMOS tube, the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second PMOS tube P2, the drain electrode of the second PMOS tube P2 and the drain electrode of the fourth NMOS tube N4, and the drain electrode of the first PMOS tube P1 is connected with the drain electrode of the third NMOS tube. The gate of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4, and the source of the third NMOS transistor N3 is connected to the drain of the first NMOS transistor N1. The gate of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2, and the source of the first NMOS transistor N1 is grounded. One end of the reference resistor Rref is connected to the power supply terminal VDD, and the other end of the reference resistor Rref is connected to the source of the second PMOS transistor P2. The grid electrode of the second PMOS tube P2 is respectively connected with the drain electrode of the second PMOS tube P2 and the drain electrode of the fourth NMOS tube N4, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the fourth NMOS tube N4. The source of the fourth NMOS transistor N4 is connected to the drain of the second NMOS transistor N2. The source of the second NMOS transistor N2 is grounded. The source of the third PMOS transistor P3 is connected to the power supply terminal VDD. The drain of the third PMOS transistor P3 is connected to the output node a of the PTAT current generating circuit 140.

In addition, as shown in fig. 5, the reference current generating module 110 with the PTAT current generating circuit 140 further includes a self-bias voltage generating circuit 150. The PTAT current generation circuit 140 is connected to the self-bias voltage generation circuit 150. Specifically, the first output terminal of the self-bias voltage generating circuit 150 is respectively connected to the gate of the third NMOS transistor N3, the gate of the fourth NMOS transistor N4, and the gate of the third PMOS transistor P3; a second output end of the self-bias voltage generating circuit 150 is respectively connected to the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2; the input end of the self-bias voltage generating circuit 150 is respectively connected to the drain of the first PMOS transistor P1 and the drain of the third NMOS transistor N3. The self-bias voltage generation circuit 150 is configured to adjust the bias voltage NB and the gate voltage of the third PMOS transistor P3 according to the source voltage of the first PMOS transistor P1. In addition, a bias voltage PB is applied to a connection point between the gate of the first PMOS transistor P1 and the gate of the second PMOS transistor P2.

With continued reference to fig. 1, in this embodiment, the PTAT current generation circuit includes a first P-type current mirror including a first PMOS transistor P1, a second PMOS transistor P2, and a third PMOS transistor P3. Specifically, since the first PMOS transistor P1, the second PMOS transistor P2 and the third PMOS transistor P3 are of a common-gate structure, the ratio of the current flowing through the third PMOS transistor P3 to the current flowing through the second PMOS transistor P2 is equal to the ratio of the width to the length of the third PMOS transistor P3 to the width to the length of the second PMOS transistor P2. If the length and width of the third PMOS transistor P3 are equal to the length and width of the second PMOS transistor P2, the current flowing through the third PMOS transistor P3 is equal to the current flowing through the second PMOS transistor P2.

The PTAT current generating circuit further comprises a first N-type current mirror, and the first N-type current mirror comprises a first NMOS tube N1 and a second NMOS tube N2. The first NMOS transistor N1 and the second NMOS transistor N2 generate a current I0, and the current I0 is a PATA current. Therefore, the current I0 can be copied to the third PMOS transistor P3 by the first P-type current mirror and the first N-type current mirror.

It is assumed that the first NMOS transistor N1 and the second NMOS transistor N2 operate in the sub-threshold region when the current flowing through the third PMOS transistor P3 is equal to the current flowing through the second PMOS transistor P2. Thus, the bandgap reference voltage Vbgh at the output node a of the PTAT current generating circuit 140 is equal to the sum of the source-drain voltage of the transistor P4 and the voltage generated by the first resistor. Further, the source-drain voltage of the transistor P4 is equal to the source-gate voltage of the transistor P4 and the gate-drain voltage of the transistor P4, and the gate-drain voltage of the transistor P4 is equal to the voltage generated by the second resistor R2. In other words, the bandgap reference voltage

Vbgh＝I1*R1+VGS4+R2*It＝(I0-It)*R1+VGS4+R2*It＝(Rt*(I0+VGS4/R1)+

Rt/R1 VOS)/(1+ Rt/R1), where VOS is R2/Rt Vbgh, VOS is the voltage of the common node B of the second resistor R2 and the third resistor R3, R2 is the second resistor, Rt is the branch resistor (or equivalent resistor) of the second branch 130, VGS4 is the voltage between the source and the gate of the transistor P4, R1 is the first resistor, I0 is η Vt/Rref ln (K2/K1), K2/K1 represents the channel width-length ratio of the second NMOS transistor and the first NMOS transistor, η is a fixed number, and Vt is a thermoelectric potential and has a positive temperature coefficient. According to the band gap reference voltage formula, the band gap reference voltage Vbgh with zero temperature coefficient can be obtained by reasonably selecting the relevant resistance in the formula. The voltage VOS of the common node B is also temperature-independent, and is only a proportional value of the bandgap reference voltage Vbgh (i.e., the ratio of the branch resistance Rt to the second resistance R2, i.e., R2/Rt). As described above, when the resistance value of the second resistor R2 is changed, the voltage value of the band gap reference voltage Vbgh can be arbitrarily changed within a certain range without affecting the temperature coefficient of the band gap reference voltage Vbgh, so that the setting of the band gap reference voltage Vbgh has great flexibility.

Referring to fig. 1 and 3, fig. 3 is a schematic structural diagram of a bandgap reference voltage source circuit according to another embodiment of the present application. In this embodiment, the circuit configuration is the same as that shown in fig. 1 or as that shown in fig. 2A to 2C, except that the form of the third resistor R3 in the second branch 130 is different. In this embodiment, the second resistor R2 may be in the form of the second resistor R2 shown in fig. 1 or in the form of the second resistor R2 shown in fig. 2A to 2C. Here, the form of the second resistor R2 is not described in detail.

In this embodiment, a first terminal of the third resistor R3 is connected to the output node of the reference current generating module 110 (i.e., the output node a of the PTAT current generating circuit), and a second terminal of the third resistor R3 is connected to the control electrode of the transistor P4. When the transistor P4 is a PMOS transistor, the second terminal of the third resistor R3 is connected to the gate of the transistor P4.

Preferably, the third resistor R3 includes a plurality of third sub-resistors (R3a, R3b, R3c, etc.) connected in series between the output node of the reference current generating module 110 and the control electrode of the transistor P4. Each of the third sub-resistors (R3a, R3b, R3c, etc.) includes a first terminal near the output node a of the reference current generating module 110 and a second terminal near the control electrode of the transistor P4. Meanwhile, the bandgap reference voltage source circuit 100 further includes a plurality of selection switches (K1, K2 … Kn), a first terminal of each of the selection switches (K1, K2 … Kn) is connected to a first terminal of a corresponding third sub-resistor (R3a, R3b, R3c, etc.), and a second terminal of each of the selection switches (K1, K2 … Kn) is connected to a common node, wherein the common node is a connection node between the second resistor and the third sub-resistor close to the control electrode of the transistor. Therefore, by selection of the selection switches (K1, K2 … Kn), one of the plurality of selection switches (K1, K2 … Kn) is brought into a closed state, thereby regulating the output voltage Vbg. Even when the band gap reference voltage Vbgh of the reference current generating block 110 deviates from a predetermined value due to process variations of circuit devices, the voltage value of the output voltage Vbg is brought to a design target value by the plurality of selection switches described above.

In this embodiment, as shown in fig. 3, when the first selection switch K1 is closed and the other selection switches are off, the voltage value of the output voltage Vbg is equal to the voltage value of the bandgap reference voltage Vbgh. When the Nth selection switch Kn is closed and other selection switches are closed, the voltage value of the output voltage Vbg is equal to the value obtained by the product of the ratio of the first equivalent resistance and the second equivalent resistance and the voltage value of the band-gap reference voltage Vbgh, wherein the first equivalent resistance is the total resistance of the first third sub-resistor R3a to the N-1 third sub-resistor R3 (N-1); the second equivalent resistance is the total resistance of the second resistor R2 and the third resistor R3.

In addition, in the embodiment shown in fig. 3, the selection switches (K1, K2 … Kn) are CMOS tube switches capable of passing high and low voltages and providing the output voltage Vbg. When the CMOS tube switch is adopted, only one CMOS tube is closed at a time, and other CMOS tube switches are closed. The type of the selection switch is not limited to the CMOS transistor switch, but may be a PMOS transistor switch or an NMOS transistor switch. When a PMOS tube switch or an NMOS tube switch is adopted, the selection function can be completed only by a single PMOS tube or NMOS tube, compared with the CMOS tube switch, the design can save the area of a circuit layout and simplify the connection.

In addition, in the embodiment shown in fig. 3, the number of adjustable gear positions of the output voltage Vbg may be determined according to design requirements, for example, 8 th gear or 16 th gear.

As described above, when the bandgap reference voltage source circuit 100 is designed such that it includes: the reference current generating module 110, a first resistor R1, a transistor P4 and a second resistor R2, wherein the first resistor R1 and the transistor P4 are arranged in series, a first end of the first resistor R1 is connected to an output node of the reference current generating module 110, and a second end of the first resistor R1 is connected to a first pole of the transistor P4. The second pole and the control pole of the transistor P4 are grounded, and the second resistor R2 is connected between the output node of the reference current generating module 110 and the ground. When the transistor P4 is a PMOS transistor, the output voltage Vbg may be lower than the target value of some output voltage in this case, which is 0.51V. When the bandgap reference voltage source circuit 100 is designed as the circuit structure shown in fig. 1, the voltage of the transistor P4 is greater than or equal to 0.1V by selecting the appropriate second resistor R2, so that the output voltage Vbg is greater than or equal to 0.6V, and the requirement of the target value of the output voltage is further satisfied. Meanwhile, the current value of the branch current It of the second branch 130 may be maintained at more than half the proportion of the reference current, thereby improving the noise immunity. Referring specifically to the waveform shown in fig. 6 (where the abscissa is temperature and the ordinate is voltage), when the output voltage Vbg increases to 0.651V, the branch current It of the second branch 130 remains at 0.455 μ a, and the voltage of the common node B is 0.14V. The temperature coefficient of the output voltage Vbg remains substantially uniform. If the output voltage Vbg with a larger voltage value needs to be provided, the resistance of the second resistor R2 in the second branch 130 needs to be increased.

Similarly, referring to fig. 7 (where the abscissa is temperature and the ordinate is voltage), if the resistance of the second resistor R2 in the second branch 130 is changed, for example, from 310K ohm to 645K ohm, and the other circuit device parameters of the bandgap reference voltage source circuit 100 are not changed, the voltage value of the output voltage Vbg can be changed from 0.651V to 0.801V; the current value of the reference current I3 in FIG. 7 is substantially the same as the current value of the reference current I3 in FIG. 6, so that the current value of the branch current in FIG. 7 is 0.460 μ A, which is not much different from the current value of the branch current in FIG. 6, which is 0.455 μ A; the trend of the output voltage Vbg with temperature in fig. 7 is also substantially the same as the trend of the output voltage Vbg with temperature in fig. 6.

The band-gap reference voltage source circuit 100 can realize that the reference voltage is not limited by the change influence of process, temperature and the like, and the range size of the band-gap reference voltage can be adjusted randomly within a certain range, so that the design flexibility of the band-gap reference voltage source circuit is enhanced. And the band-gap reference voltage-based range is relatively large, and the adjustable range of the output voltage Vbg is relatively large when the band-gap reference voltage source circuit is produced in mass, so that the yield of the circuit is improved. In addition, the branch current of the second branch 130 of the bandgap reference voltage source circuit 100 is relatively large, so that the noise immunity can be improved. Furthermore, the selection switches disposed in the second branch 130 are NMOS transistors, so as to simplify the circuit and the connection.

Referring to fig. 8, the present application further provides an electronic device 800, where the electronic device 800 includes the bandgap reference voltage source circuit 100, and details thereof are not repeated herein. Therefore, the electronic device 800 can generate a stable bandgap reference voltage, the voltage value of the bandgap reference voltage Vbgh is little or negligible affected by the process, temperature and power supply, and the range of the bandgap reference voltage Vbgh can be arbitrarily adjusted within a certain range, thereby enhancing the design flexibility of the bandgap reference voltage source circuit 100. Moreover, the band-gap reference voltage Vbgh has a relatively large range, and the adjustable range of the output voltage Vbg is relatively large when the band-gap reference voltage source circuit 100 is mass-produced, so that the designed target value is satisfied.

In some embodiments, the electronic device 800 is a non-volatile memory. Non-volatile memory refers to a type of memory that retains data after power is removed, i.e., the stored data is not lost after power is removed.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The band-gap reference voltage source circuit and the electronic device provided by the embodiments of the present application are described in detail above, and specific examples are applied in the present application to explain the principles and implementations of the present application, and the description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A bandgap reference voltage source circuit, comprising:

the reference current generation module is used for outputting a reference current positively correlated with the temperature;

a first resistor;

a transistor, a first pole of the transistor is connected with an output node of the reference current generation module through the first resistor; and

and a first end of the second resistor is connected with the control electrode of the transistor, and a second end of the second resistor and a second electrode of the transistor are connected with a common potential.

2. The bandgap reference voltage source circuit of claim 1, wherein the second terminal of the second resistor and the second pole of the transistor are grounded.

3. The bandgap reference voltage source circuit of claim 1, wherein the second resistor is an adjustable resistor.

4. The bandgap reference voltage source circuit of claim 1, wherein the transistor is a PMOS transistor.

5. The bandgap reference voltage source circuit of claim 1, wherein the transistor is a PNP transistor, the first pole of the transistor is an emitter, and the second pole of the transistor is a collector.

6. The bandgap reference voltage source circuit of claim 1, wherein the second resistor comprises a plurality of second sub-resistors connected in series between the control electrode and the second electrode of the transistor, and a bypass path bypassing at least one of the plurality of second sub-resistors based on a selection signal.

7. The bandgap reference voltage source circuit of claim 6, wherein the bypass path comprises a plurality of bypass switches controlled by a selection signal, a first terminal of each of the bypass switches is connected to a first terminal of the corresponding second sub-resistor, and a second terminal of each of the bypass switches is connected to a second terminal of the corresponding second sub-resistor.

8. The bandgap reference voltage source circuit of claim 6, wherein the bypass path comprises a plurality of bypass switches controlled by a selection signal, each of the second sub-resistors has a first end near the control electrode of the transistor and a second end near the second electrode of the transistor, the first end of each of the bypass switches is connected to the second electrode of the transistor, and the second end of each of the bypass switches is connected to the first end of the corresponding second sub-resistor.

9. The bandgap reference voltage source circuit of claim 6, wherein the bypass path comprises a plurality of bypass switches controlled by a selection signal, each of the second sub-resistors has a first end near the control electrode of the transistor and a second end near the second electrode of the transistor, the first end of each of the bypass switches is connected to the control electrode of the transistor, and the second end of each of the bypass switches is connected to the second end of the corresponding second sub-resistor.

10. The bandgap reference voltage source circuit according to any of claims 7 to 9, wherein the bypass switch is a MOS transistor switch.

11. The bandgap reference voltage source circuit according to claim 1, further comprising a third resistor, wherein a first terminal of the third resistor is connected to the output node of the reference current generating module, and a second terminal of the third resistor is connected to the control electrode of the transistor.

12. The bandgap reference voltage source circuit as claimed in claim 1, further comprising a plurality of third sub-resistors connected in series between the output node of the reference current generating module and the control electrode of the transistor, each of the third sub-resistors comprising a first end close to the output node of the reference current generating module and a second end close to the control electrode of the transistor.

13. The bandgap reference voltage source circuit as claimed in claim 12, further comprising a plurality of selection switches, wherein a first terminal of each selection switch is connected to a first terminal of a corresponding third sub-resistor, and a second terminal of each selection switch is connected to a common node, wherein the common node is a connection node between the second resistor and the third sub-resistor close to the control electrode of the transistor.

14. The bandgap voltage reference source circuit of claim 1, wherein the reference current generating module comprises a proportional to absolute temperature current generating circuit.

15. The bandgap voltage reference source circuit of claim 14, wherein the proportional to absolute temperature current generating circuit comprises a transistor operating in a sub-threshold region.

16. A bandgap reference voltage source circuit, comprising:

a proportional to absolute temperature current generating circuit;

a first branch; and

a second branch-off circuit is arranged on the second branch-off circuit,

the first branch and the second branch are connected in parallel between the output node of the proportional to absolute temperature current generation circuit and the ground, the first branch comprises a first resistor and a transistor used for providing a voltage complementary to absolute temperature, a first end of the first resistor is connected with the output node of the proportional to absolute temperature current generation circuit, a second end of the first resistor is connected with a first pole of the transistor, a second pole of the transistor is grounded, the second branch comprises a second resistor and a third resistor which are connected in series between the output node of the proportional to absolute temperature current generation circuit and the ground, and a control pole of the transistor is connected with a common node of the second resistor and the third resistor.

17. The bandgap reference voltage source circuit of claim 16, wherein the second resistor is an adjustable resistor.

18. An electronic device comprising the bandgap reference voltage source circuit as claimed in any one of claims 1 to 17.

19. The electronic device of claim 18, wherein the electronic device is a non-volatile memory.