KR101892069B1 - Bandgap voltage reference circuit - Google Patents

Abstract

The band gap voltage reference circuit of the present invention includes a self-biased OP amp that outputs a bias reference current using a first input voltage and a second input voltage; A PSRR enhancement circuit to improve the power supply rejection ratio (PSRR) for the output of a self-biased op amp; And an active load circuit for outputting a reference voltage as a load to the output of the PSRR enhancement circuit. Therefore, according to the present invention, PSRR can be improved.

Description

BANDGAP VOLTAGE REFERENCE CIRCUIT [0002]

The present invention relates to a bandgap voltage reference circuit, and more particularly, to a bandgap voltage reference circuit having a supply voltage of 0.9 [V] to 4 [V], a temperature coefficient of 5.5 ppm / Quot ;, and " Ratio "). Here, the temperature coefficient of 5.5 ppm / ° C was obtained in the temperature range of 0 to 125 ° C, and the power of the whole circuit was consumed 0.21 [ μW ] when 0.9 [V] was supplied at 27 ° C. At 100 Hz and 10 MHz, the PSRR was lower than 63 and 66.5 [dB], respectively, and the effective area of the circuit was 0.0028 mm ² .

An analog / high-frequency circuit or a digital circuit which is fabricated in the form of an integrated circuit requires a stable and accurate bias voltage for efficient operation. That is, even if the external power supply voltage, temperature, or process fluctuates, they must be prevented from affecting the inside of the integrated circuit, and each device should be able to perform its own functions stably. However, a bias voltage provided in a conventional bias circuit has a problem that the bias voltage does not maintain a constant value over time due to a temperature change occurring during operation of the circuit.

In order to solve the above problem, a band gap voltage reference circuit is used. The band gap voltage reference circuit uses a voltage produced by a proportional to absolute temperature (PTAT) circuit with a characteristic proportional to the absolute temperature and a voltage produced by a complementary to absolute temperature (CTAT) circuit having a characteristic inversely proportional to the absolute temperature And outputs a stable reference voltage that is not affected by the temperature change.

Dependent voltage references to process variations, voltage and temperature (PVT) are widely used in analog circuits, mixed signal processing, RF fields and digital circuits . The structure of a bandgap voltage reference circuit can be divided into three main parts: the generation of two voltages (or currents), one proportional to absolute temperature (PTAT) The other is complementary to absolute temperature (CTAT) and biasing.

However, the conventional bandgap voltage reference circuit generates a CTAT voltage with a P-N junction exhibiting some non-linear characteristics with respect to temperature. Most of the prior art utilize two nodes to generate CTAT and PTAT currents by using resistors of the same value. Additionally, the startup circuit design methodology for the bandgap voltage reference circuit pursued in the prior art requires either an external power on reset signal (POR) for the reset signal or a bias current bias currents. On the other hand, PSRR, as opposed to power spurious, is the most important factor in bandgap voltage reference circuits when these circuits are used with low dropout (LDO) regulators.

Korean Patent No. 10-0694985 (registered on Mar. 07, 2007) relates to a bandgap reference circuit for a low voltage and a semiconductor device including the same, and includes a comparator, a first current source circuit , A second current source circuit, a first load circuit, and a second load circuit. The comparator compares the first voltage and the second voltage, and outputs the control voltage according to the comparison result. The first current source circuit supplies a first current to the first node in response to the control voltage. The second current source circuit supplies a second current to the second node in response to the control voltage. The first load circuit generates first and second voltages that are determined by a first current received through the first node and its resistance value. The second load circuit generates a second current received through the second node and a reference voltage determined by its resistance value. The bandgap reference circuit according to the prior art document and the semiconductor device including the bandgap reference circuit stably operate even when a power supply voltage of a low voltage is supplied.

Korean Patent Laid-Open No. 10-2009-0048295 (published on May 13, 2009) discloses a bandgap reference voltage generating circuit for a semiconductor device, which can generate a bandgap reference voltage having immunity to PVT under an operating power source environment And to provide a bandgap reference voltage generating circuit of a semiconductor device capable of controlling an output level independent of a temperature characteristic without increasing the layout area. According to an aspect of the present invention, there is provided a semiconductor device comprising: a first current generator for generating a first current proportional to a temperature change using a temperature characteristic of a diode-connected MOS transistor; A second current generator for generating a second current inversely proportional to the temperature change using the temperature characteristic of the diode-connected MOS transistor; And a summation unit for copying the output currents of the first and second current generators and for summing them together and outputting them as a reference voltage.

The prior art documents present two nodes for generating CTAT and PTAT currents, do not present a bandgap core based on one node, and also provide a start-up circuit with a plurality of transistors The above-mentioned problems can not be solved, and the motivation for solving the above problems can not be obtained.

Accordingly, the present invention includes a start-up circuit composed of one transistor for a self-biased op-amp, as described above, and includes a bandgap voltage reference circuit . Unlike a traditional bandgap core, the present invention discloses a structure based on one node. The bandgap voltage reference circuit of the present invention includes an arrangement for exerting an enhanced PSRR. The self-biased OP amplifier of the present invention includes a design that is designed such that the noise of the external power supply is reduced and is no longer present at the output.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bandgap voltage reference circuit having an improved power supply voltage rejection ratio.

In order to accomplish the above object, a bandgap voltage reference circuit according to an embodiment of the present invention includes a bias reference voltage generating circuit for generating a bias reference voltage using a first input voltage and a second input voltage, a self-biased op-amp that outputs current; A PSRR enhancement circuit for improving a power supply rejection ratio (PSRR) for an output of the self-biased OP amplifier; And an active load circuit for outputting a reference voltage as a load to the output of the PSRR enhancement circuit.

In addition, the bandgap voltage reference circuit according to an embodiment of the present invention includes a proportional to absolute temperature (PTAT) current having a characteristic proportional to the gap absolute temperature and a complementary to absolute temperature Lt; RTI ID = 0.0 > (n) < / RTI > currents.

Also, the PTAT current and the CTAT current may flow through a first branch and a second branch, respectively, which branch at a single-node having the second input voltage.

In the first branch, a first NMOS having a first resistor R ₁ and a gate terminal and a drain terminal connected to a common node may be connected in series.

In addition, a second resistor (R ₂ ) may be connected to the second branch.

Also, the PTAT current may be a current flowing in the first resistor R _{1 to} which a difference between the gate-source voltage of the first NMOS and the gate-source voltage of the second NMOS is applied.

Also, the CTAT current may be a current flowing in the second resistor R _{2 to} which the gate-source voltage of the second NMOS is applied.

In addition, the bandgap voltage reference circuit according to an embodiment of the present invention may further include a start-up circuit for driving the CMOS bandgap core.

Further, the start-up circuit may be composed of only one NMOS.

In addition, the bandgap voltage reference circuit may include only a CMOS transistor as an entire constituent transistor.

According to the present invention, the power supply voltage rejection ratio (PSRR) can be improved. In addition, it is possible to reduce the noise of the self-biased OP amplifier. In addition, since the entire circuit is constituted by CMOS, it is possible to increase the degree of home contact.

1 is a block diagram showing an equivalent circuit of a band gap voltage reference circuit according to an embodiment of the present invention.
2 is a circuit diagram of a band gap voltage reference circuit according to an embodiment of the present invention.
3A is a graph illustrating a change in a reference voltage according to a supply voltage of a bandgap voltage reference circuit according to an embodiment of the present invention.
FIG. 3B is a graph illustrating changes in reference voltage according to temperature of a bandgap voltage reference circuit according to an embodiment of the present invention, according to input voltages. Referring to FIG.
3C is a graph showing the PSRR of the bandgap voltage reference circuit according to the embodiment of the present invention.
FIG. 3D is a graph showing the noise included in the reference voltage of the bandgap voltage reference circuit according to the embodiment of the present invention.
4A is a Monte Carlo histogram of a bandgap voltage reference circuit according to an embodiment of the present invention.
4B is a block diagram showing a layout of a bandgap voltage reference circuit according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements. It is also to be understood that the structural and functional descriptions that are specific to embodiments of the present invention are presented for purposes of describing embodiments of the present invention only and that, unless otherwise defined, all terms used herein, including technical or scientific terms, The terms have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as ideal or overly formal in the sense of the art unless explicitly defined herein .

1 is a block diagram showing an equivalent circuit of a band gap voltage reference circuit according to an embodiment of the present invention.

Referring to FIG. 1, a bandgap voltage reference circuit 100 according to an embodiment of the present invention includes a self-biased OP amplifier 110, a PSRR enhancement circuit 120 And an active load circuit 130.

Where each of the self-biased OP amplifier 110, the PSRR enhancement circuit 120 and the load active circuit 130 is an equivalent circuit comprising an OP amp Can be expressed. A self-biased OP amplifier 110 may be represented as an OP amplifier 110 with an open loop gain A ₁ and a PSRR enhancement circuit 120 may be represented as an open- Can be represented as an OP amp 120 with a loop gain A ₂ and a load active circuit 130 can be represented as an OP amp 130 with an open loop gain A ₃ .

The self-biased OP amplifier 110 outputs a bias reference current and a bias reference voltage ( V _OTA ) using a first input voltage and a second input voltage. Here, the first input voltage is a voltage input to the plus terminal of the OP amplifier 110, and the second input voltage is a voltage input to the minus terminal of the OP amplifier 110. [

The PSRR enhancement circuitry 120 improves the power supply rejection ratio (PSRR) for the output of the self-biased OP amplifier 110. Specifically, the PSRR enhancement circuit 120 receives the output of the self-biased OP amplifier 110 through the negative terminal, receives the driving voltage V _dd through the positive terminal, and outputs the common node voltage V _c Output.

The load activation circuit 130 outputs an output reference voltage V _ref as a load to the output of the PSRR enhancement circuit. Likewise, the load activation circuit 130 receives the output of the PSRR enhancement circuit 120 through the negative terminal and receives the drive voltage V _dd through the positive terminal.

In the conventional bandgap voltage reference circuit, the base-emitter voltage ( V _BE ) of a bipolar junction transistor (BJT) is compensated by a proportional to absolute temperature (PTAT) voltage generator having a characteristic proportional to absolute temperature And generates a complementary absolute temperature (CTAT) with a characteristic that is inversely proportional to the compensated absolute temperature.

As a result, the output reference voltage V _ref has a low temperature dependence, which is obtained by the sum of the CTAT voltage and the PTAT voltage multiplied by the gain factor k.

On the other hand, the circuit of FIG. 1 according to an embodiment of the present invention includes a CMOS bandgap core in which all transistors are made of CMOS to generate CTAT and PTAT voltages. The band gap voltage reference circuit 100 according to the embodiment of the present invention will be described in more detail.

2 is a circuit diagram of a bandgap voltage reference circuit according to an embodiment of the present invention.

Referring to FIG. 2, a bandgap voltage reference circuit 100 according to an embodiment of the present invention includes a self-biased OP amplifier 110, a PSRR enhancement circuit 120 And active load circuits 131 and 132 and may further include a CMOS bandgap core 140 and a start up circuit 150. [

 The components 110, 120 and 131, 132 described above in accordance with one embodiment of the present invention may be implemented using the circuit elements shown in Fig. Components 110, 120 and 131, 132 have been described above and will be described briefly, and additional components 140 and 150 will be described in detail.

The self-biased operational amplifier 110, which is represented by the operational amplifier 110 as an equivalent circuit in FIG. 1, can be implemented in CMOS of M1 to M4, MSB1 and MSB2.

The gate voltage of M1 is represented by V _b, and the gate voltage of M2 is represented by V _a. V _b denotes a second input voltage of the OP amplifier 110 shown in FIG. 1, V _a represents a first input voltage of the OP amplifier 110 shown in FIG. And V _b And V _a corresponds to the PTAT and CTAT voltages generated by the CMOS bandgap core 140, respectively.

The load activating circuit 130 shown in Fig. 1 can be represented by components 131 and 132 in the circuit diagram of Fig. Here, 131 may be implemented as a PMOS, and 132 may be implemented as an NMOS. The node to which the drain terminal and the gate terminal of the NMOS 132 are connected represents an output reference voltage V _ref .

The CMOS bandgap core 140 generates a proportional to absolute temperature (PTAT) current having a characteristic proportional to an absolute temperature and a complementary to absolute temperature (CTAT) current having a characteristic inversely proportional to an absolute temperature.

Referring again to FIG. 2, the CMOS bandgap core 140 may be implemented using only CMOS transistors as constituent transistors. The load activation circuits 131 and 132 may generate the current I _L and the CMOS band gap core 140 may generate the currents I ₁ and I ₂ . A detailed description of each current will be described later.

The bandgap voltage reference circuit 100 in accordance with an embodiment of the present invention is a mono-characterized in that it generates a PTAT current and the CTAT current branch from node using the node (V _b), one.

The start-up circuit 150 is a circuit for driving the CMOS bandgap core 140. The transistor MST included in the start-up circuit 150 is used to quickly drive the bandgap voltage reference circuit according to the embodiment of the present invention.

The start-up circuit 150 included in the bandgap voltage reference circuit 100 according to the embodiment of the present invention includes one start-up transistor.

Here, one start-up transistor may be implemented through an NMOS (MST). That is, the gate terminal of the start-up transistor MST is connected to the terminal V _st of the self-biased OP amplifier 110, the drain terminal is connected to the common node V _c , which is the output of the PSRR enhancement circuit, May be coupled to a node having _a first input voltage ( V _a ) generated by a CMOS bandgap core (140).

A description will now be made of a temperature compensation technique that can be implemented by a configuration according to an embodiment of the present invention.

Referring again to FIG. 2, by considering that the active load transistor M8 operates in a saturation region, the output voltage of the bandgap voltage reference circuit 100 according to the embodiment of the present invention the output voltage V _ref can be given as follows.

Where I _L is the bias current of _M8 and k _M8 = C _ox ( W _M8 / L _M8 ). μ is C _ox is the oxide capacitance per unit area, W is the channel width, and L is the channel length. From equation (1), the first component (threshold voltage, V _th ) and the second component (mobility) of V _ref are temperature coefficients that can be disturbed by a bias current proportional to electron mobility, Lt; / RTI >

Referring to Equation (2), the self-biased OP amp input voltages ( V _a , V _b ) must be equalized by controlling I ₁ , I ₂ .

Referring to Equation (3), the common node voltage ( V _c ) is responsible for equalizing I ₁ , I ₂ and I _L.

V _b is a single-node of the bandgap core circuit to produce I _2, thus I _L , which is temperature dependent.

I ₂ is controlled by currents I _R1 and I _R2 respectively flowing through the R ₁ and R ₂ resistors and by M 10.

The NMOSs M10 and M12 connected to the diode are defined to operate in a weak inversion regime. Thus, the drain current can be derived as: < RTI ID = 0.0 >

_{Here, I t (= 2 nC ox} [k B T / q] 2) is a dependent parameter (20nA) the process, n is the unit threshold slope factor (subthreshold slope factor) represents the (1.5), k _B is Boltzmann (Boltzmann constant), q is the elementary charge, and T is the absolute temperature. By reconstructing Equation (4), the difference between the gate-source voltages ( V _gs ) of M10 and M12 can be expressed as:

Where V _T represents the thermal voltage (26 mV, at room temperature). Using equation (5), I _R1 can be derived as: &_lt; RTI _{ID = 0.0} >

Equation 6 shows that V _T has a positive temperature coefficient of 0.086 mV / C. Thus, I _R1 can be approximated to be proportional to PTAT. On the other hand, I _R2 is proportional to V _gs12 , which is set equal to V _b as follows:

From Equation (4), and the source (source) and the bulk (bulk) terminal of M12 (terminals) are connected to each other, V _th can be expressed as follows:

(N _A는 도핑밀도(doping density) 그리고 ε는 투자율(permittivity)이다)이고 φ _F는 페르미 레벨(fermi level)을 나타낸다.Where E _g is the band-gap of silicon,

(Where N _A is the doping density and E is the permittivity) and φ _F is the fermi level.

Equation (8) shows that V _th is proportional to the reciprocal of T. Thus, V _gs12 (and I _R2 ) in equation (4) is proportional to CTAT. As a result, I _R1 and I _R2 that branch at the common node are used to generate positive and negative temperature coefficients, respectively. Therefore, temperature dependent I _L can be derived from equations (3), (6) and (7). Replacing I _L in equation (1) can be written as:

Next, the PSRR improving circuit of the bandgap voltage reference circuit according to the embodiment of the present invention will be described.

Referring again to FIG. 1, FIG. 1 illustrates a bandgap voltage reference circuit 100 according to an embodiment of the present invention having open loop gains A ₁ , A _2, and A ₃ of _{three components} . Fig. The total open loop gain of the equivalent network is A = A ₁ A ₂ A ₃ . The power supply gain of the network can be expressed as A _p = A _p3 + A ₃ [1 - ( A _p2 + A ₂ (1 - A _p1 )). Therefore, the PSRR of the equivalent network is expressed by Equation (10).

or,

_{Here, PSRR 1 = A 1 / A} p1 = - g m, M1 / (g o, M1 + g o, M4), PSRR 2 = - A 2 / A p2 = - g m, M5 / g o, M5, a _{g m, M7 / g o,} M7 - PSRR 3 = - a 3 / a p3 =. g _{m, Mi} and g _{o and Mi} represent the transconductance and the conductance of the transistors, respectively, when i = 1 to 8. By replacing the transconductance and conductance in Equation (11), the modified Equation (11) can be expressed as follows.

,

From equation (12), PSRR can be improved by adjusting g _{o, M5} .

FIGS. 3A through 3D show post-layout simulation results in a Hynix 0.18m CMOS process of a circuit according to an embodiment of the present invention. FIG.

3A is a graph illustrating a change in a reference voltage according to a supply voltage of a bandgap voltage reference circuit according to an embodiment of the present invention.

Referring to FIG. 3A, for a supply voltage of DC 0.9-4 V , the bandgap voltage reference circuit according to an embodiment of the present invention has an average V _ref of 507 mV at a line sensitivity of 0.36% at 27 ° C .

FIG. 3B is a diagram summarizing changes in the reference voltage according to the temperature of the bandgap voltage reference circuit according to the embodiment of the present invention.

Referring to FIG. 3B, in the range of 0 to 125 占 폚, the lowest temperature coefficient TC is 5.5 ppm / 占 폚, which is the case when V _dd = 2V.

3C is a graph showing the PSRR of the bandgap voltage reference circuit according to the embodiment of the present invention.

Referring to FIG. 3C, a structure according to an embodiment of the present invention achieves a PSRR improvement of 25 dB, as compared to a conventional bandgap voltage reference circuit.

FIG. 3D is a graph showing the noise included in the reference voltage of the bandgap voltage reference circuit according to the embodiment of the present invention.

4A is a Monte Carlo histogram of a bandgap voltage reference circuit according to an embodiment of the present invention.

When Figure 3d with reference to Figure 4a, the output noise is, in a ^{10Hz 0.18 μV / (Hz) 1} /2 , and process variation coefficient (process variation coefficient) (σ / μ) is from 27 ℃ 0.91%.

4B is a block diagram showing a layout of a bandgap voltage reference circuit according to an embodiment of the present invention.

Referring to FIG. 4B, the bandgap voltage reference circuit according to the embodiment of the present invention can be integrated into a block having a width of 64.23 .mu.m and a length of 42.89 .mu.m, so that the effect of reducing the integrated area is generated.

Table 1 below summarizes the performance of the bandgap voltage reference circuit according to the embodiment of the present invention in comparison with the prior art.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that it is possible.

100: Bandgap voltage reference circuit, 110: Self-biased OP amplifier,
120: PSRR enhancement circuit, 130 (131, 132): load activation circuit,
140: CMOS bandgap core, 150: Start-up circuit

Claims (10)

A self-biased op-amp that outputs a bias reference current and a reference voltage using a first input voltage and a second input voltage;
A PSRR enhancement circuit for improving a power supply rejection ratio (PSRR) for an output of the self-biased OP amplifier;
An active load circuit for outputting a reference voltage with respect to an output of the PSRR enhancement circuit;
A CMOS bandgap core that generates a proportional to absolute temperature (PTAT) current having a characteristic proportional to an absolute temperature and a complementary to absolute temperature (CTAT) current having a characteristic inversely proportional to an absolute temperature; And
And a start-up circuit for driving the CMOS bandgap core, the start-up circuit comprising only one NMOS. delete The method according to claim 1,
Wherein the PTAT current and the CTAT current flow in each of a first branch and a second branch that branch at a single-node having the second input voltage. The method of claim 3,
In the first branch,
Wherein a first resistor (R1) and a first NMOS having a gate terminal and a drain terminal connected to a common node are connected in series. The method of claim 3,
In the second branch,
And a second resistor (R2) is connected. The method of claim 4,
The PTAT current,
And a current flowing in a first resistor (R1) to which a difference between a gate-source voltage of the first NMOS and a gate-source voltage of the second NMOS is applied. The method of claim 4,
The CTAT current may be,
And a current flowing in a second resistor (R2) to which a gate-source voltage of the second NMOS is applied. delete delete The method according to claim 1,
The band gap voltage reference circuit includes:
Wherein the transistor is implemented using only a CMOS transistor as a whole constituent transistor.

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