CN117118409B - Hysteresis comparison circuit and electronic chip - Google Patents
Hysteresis comparison circuit and electronic chip Download PDFInfo
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- CN117118409B CN117118409B CN202311384696.8A CN202311384696A CN117118409B CN 117118409 B CN117118409 B CN 117118409B CN 202311384696 A CN202311384696 A CN 202311384696A CN 117118409 B CN117118409 B CN 117118409B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2436—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using a combination of bipolar and field-effect transistors
- H03K5/2445—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using a combination of bipolar and field-effect transistors with at least one differential stage
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Abstract
The embodiment of the invention discloses a hysteresis comparison circuit and an electronic chip, wherein the hysteresis comparison circuit comprises a gain amplification module, a hysteresis generation module and a signal output module, the hysteresis generation module comprises a first hysteresis generation unit and a second hysteresis generation unit, the first hysteresis generation unit comprises a first impedance adjustment subunit and a first switch subunit, and the first impedance adjustment subunit is connected with the first switch subunit; the second hysteresis generation unit comprises a second impedance adjustment subunit and a second switch subunit, and the second impedance adjustment subunit is connected with the second switch subunit; the hysteresis generating module is used for generating hysteresis voltage of the input signal according to the feedback signal of the signal output module, and the first impedance adjusting subunit and the second impedance adjusting subunit are used for adjusting the range of the hysteresis voltage. The scheme can improve the precision of the hysteresis voltage range and is beneficial to reducing the deviation of the hysteresis voltage range.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronics, in particular to a hysteresis comparison circuit and an electronic chip.
Background
The hysteresis comparator is a comparator with hysteresis characteristics, and can not act as long as the oscillation amplitude of the noise signal does not exceed the hysteresis range of the hysteresis comparator, so that the anti-interference capability of the comparator can be greatly improved.
At present, the hysteresis function of the comparator is usually realized by adopting positive feedback of an external resistor network, or the hysteresis function is realized by adding current controlled by an output signal to the output end of the comparator. However, the hysteresis voltage range of the hysteresis comparator in the prior art has large deviation, and the problem of erroneous output is easy to occur.
Disclosure of Invention
The embodiment of the invention provides a hysteresis comparison circuit and an electronic chip, which are used for reducing hysteresis voltage range deviation.
According to an aspect of the present invention, there is provided a hysteresis comparison circuit including: the first voltage input end, the second voltage input end and the signal output end; further comprises:
the gain amplifying module is used for amplifying input signals received by the first voltage input end and the second voltage input end;
the hysteresis generation module comprises a first hysteresis generation unit and a second hysteresis generation unit, the first hysteresis generation unit comprises a first impedance adjustment subunit and a first switch subunit, the first end of the first impedance adjustment subunit is connected with a power supply voltage, the second end of the first impedance adjustment subunit is connected with the first end of the first switch subunit, and the control end of the first switch subunit is connected with the second output end of the gain amplification module; the second hysteresis generation unit comprises a second impedance adjustment subunit and a second switch subunit, wherein the first end of the second impedance adjustment subunit is connected with the power supply voltage, the second end of the second impedance adjustment subunit is connected with the first end of the second switch subunit, and the control end of the second switch subunit is connected with the first output end of the gain amplification module;
The control end of the first impedance adjustment subunit is connected with the second feedback end of the signal output module, the control end of the second impedance adjustment subunit is connected with the first feedback end of the signal output module, the first control end of the signal output module is connected with the second end of the first impedance adjustment subunit, the second control end of the signal output module is connected with the second end of the second impedance adjustment subunit, and the output end of the signal output module is connected with the signal output end; the hysteresis generating module is used for generating hysteresis voltage of the input signal according to the feedback signal of the signal output module, and the first impedance adjusting subunit and the second impedance adjusting subunit are used for adjusting the range of the hysteresis voltage.
Optionally, the hysteresis generating module further includes a first current source, and the first current source is connected to the second end of the first switch subunit and the second end of the second switch subunit respectively;
in the same working state of the hysteresis comparison circuit, the impedance of the first impedance adjusting subunit and the impedance of the second impedance adjusting subunit are different, the first impedance adjusting subunit is used for adjusting the negative threshold value of the hysteresis voltage, and the second impedance adjusting subunit is used for adjusting the positive threshold value of the hysteresis voltage.
Optionally, the first impedance adjusting subunit includes a first transistor, a first resistor and a second resistor, the first switch subunit includes a second transistor, a first end of the first resistor is connected to a power supply voltage, a second end of the first resistor is connected to a first end of the second resistor, a second end of the second resistor is connected to a first pole of the second transistor, a second pole of the second transistor is connected to a first current source, a control of the first transistor is a control end of the first impedance adjusting subunit, a first pole of the first transistor is connected to a first end of the first resistor, a second pole of the first transistor is connected to a second end of the first resistor, a control of the second transistor is a control end of the first switch subunit, and a second end of the second resistor is a second end of the first impedance adjusting subunit;
the second impedance adjusting subunit comprises a third transistor, a third resistor and a fourth resistor, the second switching subunit comprises a fourth transistor, the first end of the third resistor is connected with a power supply voltage, the second end of the third resistor is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the first pole of the fourth transistor, the second pole of the fourth transistor is connected with a first current source, the control end of the third transistor is a control end of the second impedance adjusting subunit, the first pole of the third transistor is connected with the first end of the third resistor, the second pole of the third transistor is connected with the second end of the third resistor, the control end of the fourth transistor is a control end of the second switching subunit, and the second end of the fourth resistor is a second end of the second impedance adjusting subunit.
Optionally, the resistance of the first resistor is equal to the resistance of the third resistor, and the resistance of the second resistor is equal to the resistance of the fourth resistor;
the first transistor and the third transistor are field effect transistors, the second transistor and the fourth transistor are bipolar junction transistors, and the first transistor and the third transistor are not simultaneously turned on.
Optionally, the gain amplifying module comprises a first amplifying unit and a second amplifying unit, the control end of the first amplifying unit is connected with the first voltage input end, and the control end of the second amplifying unit is connected with the second voltage input end;
the first amplifying unit comprises a second current source, a fifth resistor and a fifth transistor, wherein the input end of the second current source is connected with a power supply voltage, the output end of the second current source is connected with a first pole of the fifth transistor through the fifth resistor, a second pole of the fifth transistor is grounded, the control end of the fifth transistor is a control end of the first amplifying unit, and the output end of the second current source is an output end of the first amplifying unit;
the second amplifying unit comprises a third current source and a sixth transistor, the input end of the third current source is connected with a power supply voltage, the output end of the third current source is connected with the first pole of the sixth transistor, the second pole of the sixth transistor is grounded, the control end of the sixth transistor is the control end of the second amplifying unit, and the output end of the third current source is the output end of the second amplifying unit;
The fifth resistor is used for adjusting the level inversion threshold value of the hysteresis comparison circuit and setting the level inversion threshold value to be a negative value.
The signal output module comprises a cascode amplifying unit, a first inverter, a second inverter and a buffer;
the first control end of the common-source common-gate amplifying unit is connected with the first output end of the hysteresis generating module, the second control end of the common-source common-gate amplifying unit is connected with the second output end of the hysteresis generating module, the output end of the common-source common-gate amplifying unit is connected with the input end of the first phase inverter, the output end of the first phase inverter is respectively connected with the input end of the second phase inverter and the control end of the second impedance adjusting subunit, the output end of the second phase inverter is respectively connected with the input end of the buffer and the control end of the first impedance adjusting subunit, and the output end of the buffer is connected with the signal output end of the hysteresis comparing circuit.
The cascode amplifying unit includes a seventh transistor, an eighth transistor, a fourth current source, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
a first electrode of the ninth transistor is connected with a power supply voltage, a second electrode of the ninth transistor is connected with a first electrode of the tenth transistor, a second electrode of the tenth transistor is connected with a first electrode of the eleventh transistor, a second electrode of the eleventh transistor is connected with a first electrode of the twelfth transistor, a second electrode of the twelfth transistor is grounded, a control electrode of the ninth transistor is connected with a control electrode of the thirteenth transistor, a control electrode of the tenth transistor is connected with a control electrode of the fourteenth transistor, a control electrode of the eleventh transistor is connected with a first electrode of the eleventh transistor, and a control electrode of the twelfth transistor is connected with a first electrode of the twelfth transistor;
A first electrode of the thirteenth transistor is connected with a power supply voltage, a second electrode of the thirteenth transistor is connected with a first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected with a first electrode of the sixteenth transistor, a second electrode of the sixteenth transistor is grounded, a control electrode of the fifteenth transistor is connected with a control electrode of the eleventh transistor, and a control electrode of the sixteenth transistor is connected with a control electrode of the twelfth transistor;
the control electrode of the seventh transistor is connected with the second end of the second impedance adjusting subunit, the first electrode of the seventh transistor is connected with the second electrode of the ninth transistor, the second electrode of the seventh transistor is grounded through the fourth current source, the control electrode of the eighth transistor is connected with the second end of the first impedance adjusting subunit, the first electrode of the eighth transistor is connected with the second electrode of the thirteenth transistor, and the second electrode of the eighth transistor is grounded through the fourth current source.
Optionally, the signal output module further comprises a current bias unit, wherein the current bias unit is used for providing bias current for the cascode amplifying unit;
the current bias unit comprises a seventeenth transistor, an eighteenth transistor, a sixth resistor and a fifth current source, wherein a first pole of the seventeenth transistor is connected with a power supply voltage, a second pole of the seventeenth transistor is connected with a first pole of the eighteenth transistor, a second pole of the eighteenth transistor is connected with a first end of a sixth resistor, a second end of the sixth resistor is grounded through the fifth current source, a control pole of the seventeenth transistor is respectively connected with a control pole of the thirteenth transistor and a second pole of the eighteenth transistor, and a control pole of the eighteenth transistor is respectively connected with a control pole of the fourteenth transistor and a second end of the sixth resistor.
Optionally, the system further comprises a voltage stabilizing module, wherein the voltage stabilizing module is used for providing power supply voltage for the gain amplifying module, the hysteresis generating module and the signal output module.
According to another aspect of the present invention, there is provided an electronic chip including the hysteresis comparison circuit provided by any of the embodiments of the present invention.
The hysteresis comparison circuit provided by the embodiment of the invention comprises a gain amplification module, a hysteresis generation module and a signal output module, wherein the gain amplification module is used for receiving differential signals of a first voltage input end and a second voltage input end, amplifying the received differential signals, and outputting the amplified signals to a hysteresis generation module of a later stage, the hysteresis generation module comprises a first hysteresis generation unit and a second hysteresis generation unit, the first hysteresis generation unit comprises a first impedance adjustment subunit and a first switch subunit, and the second hysteresis generation unit comprises a second impedance adjustment subunit and a second switch subunit. The first impedance adjusting subunit is controlled by the signal fed back by the second feedback end of the signal output module to adjust the impedance of the branch where the first impedance adjusting subunit is located, and the second impedance adjusting subunit is controlled by the signal fed back by the first feedback end of the signal output module to adjust the impedance of the branch where the second impedance adjusting subunit is located, so that the accurate setting of the hysteresis voltage is realized, the precision of the hysteresis voltage range is improved, and the deviation of the hysteresis voltage range is reduced.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a hysteresis comparator circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another hysteresis comparator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another hysteresis comparator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another hysteresis comparator circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a signal output module according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of a hysteresis comparison circuit according to an embodiment of the present invention, and referring to fig. 1, the hysteresis comparison circuit provided in this embodiment includes a first voltage input end a, a second voltage input end B, and a signal output end RO, where the first voltage input end a and the second voltage input end B are differential voltage input ends for receiving differential signals, and the signal output end RO is a single-ended output port for outputting control signals.
The hysteresis comparison circuit further includes:
the gain amplifying module 10 is configured to amplify the input signals received by the first voltage input terminal a and the second voltage input terminal B.
The hysteresis generating module 20 comprises a first hysteresis generating unit 201 and a second hysteresis generating unit 202, the first hysteresis generating unit 201 comprises a first impedance adjusting subunit 210 and a first switching subunit 220, a first end of the first impedance adjusting subunit 210 is connected with a power supply voltage VDD, a second end of the first impedance adjusting subunit 210 and a first end of the first switching subunit 220 are connected to a point E, and a control end of the first switching subunit 220 is used as a third control end c3 of a hysteresis comparing circuit to be connected with a second output end b2 of the gain amplifying module 10; the second hysteresis generating unit 202 includes a second impedance adjusting subunit 230 and a second switching subunit 240, where a first end of the second impedance adjusting subunit 230 is connected to the power supply voltage VDD, a second end of the second impedance adjusting subunit 230 is connected to the first end of the second switching subunit 240 at the point F, and a control end of the second switching subunit 240 is connected to the first output end a2 of the gain amplifying module 10 as a first control end c1 of the hysteresis comparing circuit.
The control end of the first impedance adjustment subunit 210 is used as a fourth control end c4 of the hysteresis comparison circuit to be connected with the second feedback end d2 of the signal output module 30, the control end of the second impedance adjustment subunit 230 is used as a second control end c2 of the hysteresis comparison circuit to be connected with the first feedback end d1 of the signal output module 30, the first control end d3 of the signal output module 30 is connected with the second end of the first impedance adjustment subunit 210, the second control end d4 of the signal output module 30 is connected with the second end of the second impedance adjustment subunit 230, and the output end d5 of the signal output module 30 is connected with the signal output end RO; the hysteresis generating module 20 is configured to generate a hysteresis voltage of the input signal according to the feedback signal of the signal output module 30.
Specifically, the first input terminal a1 of the gain amplifying module 10 is connected to the first voltage input terminal a of the hysteresis comparing circuit, and the second input terminal B1 is connected to the second voltage input terminal B of the hysteresis comparing circuit, for amplifying the differential signal input by the first voltage input terminal a and the second voltage input terminal B and outputting the differential signal from the first output terminal a2 and the second output terminal B2 thereof.
The first impedance adjusting subunit 210 and the second impedance adjusting subunit 230 are used for introducing a hysteresis voltage, and the range of the hysteresis voltage is changed by adjusting the impedance of the corresponding branch through the first impedance adjusting subunit 210 and the second impedance adjusting subunit 230.
In this embodiment, the output level of the signal output module 30 is controlled by the voltages at the point E and the point F, for example, the signal output module 30 outputs a high level in response to the voltage operation at the point E and outputs a low level in response to the voltage operation at the point F. Therefore, the level inversion can be realized by changing the voltage of the E point and the F point. The voltages at the point E and the point F are controlled by the output voltage of the gain amplification module 10, and when the difference between the voltages input by the gain amplification module 10 changes in the positive direction or in the negative direction, the branch currents of the first hysteresis generation unit 201 and the second hysteresis generation unit 202 change, so that the voltages at the point E and the point F are changed. When the difference in the voltages output from the gain amplification module 10 is greater than a positive threshold (upper limit of hysteresis voltage) or less than a negative threshold (lower limit of hysteresis voltage), the signal level output from the signal output module 30 is inverted.
The hysteresis voltage range of the input signal may be introduced by the first impedance adjusting subunit 210 and the second impedance adjusting subunit 230, where the first impedance adjusting subunit 210 and the second impedance adjusting subunit 230 are controlled by the feedback signals (the voltages fed back by the first feedback end d1 and the second feedback end d2 of the signal output module 30) of the signal output module 30, so that the modules are related to each other, and the impedance on the corresponding branch is adjusted by the impedance adjusting subunit to change the node voltage so as to define the hysteresis voltage, so that when the difference value of the signals received by the first voltage input end a and the second voltage input end B reaches the hysteresis voltage, the output level of the output module 30 is changed.
The hysteresis comparison circuit provided by the embodiment of the invention comprises a gain amplification module, a hysteresis generation module and a signal output module, wherein the gain amplification module is used for receiving differential signals of a first voltage input end and a second voltage input end, amplifying the received differential signals, and outputting the amplified signals to a hysteresis generation module of a later stage, the hysteresis generation module comprises a first hysteresis generation unit and a second hysteresis generation unit, the first hysteresis generation unit comprises a first impedance adjustment subunit and a first switch subunit, and the second hysteresis generation unit comprises a second impedance adjustment subunit and a second switch subunit. The first impedance adjusting subunit is controlled by the signal fed back by the second feedback end of the signal output module to adjust the impedance of the branch where the first impedance adjusting subunit is located, and the second impedance adjusting subunit is controlled by the signal fed back by the first feedback end of the signal output module to adjust the impedance of the branch where the second impedance adjusting subunit is located, so that the accurate setting of the hysteresis voltage is realized, the precision of the hysteresis voltage range is improved, and the deviation of the hysteresis voltage range is reduced.
With continued reference to fig. 1, the hysteresis generating module 20 further includes a first current source I1, where the first current source I1 is respectively connected to the second end of the first switch subunit 220 and the second end of the second switch subunit 240, and the first current source I1 is configured to provide bias currents for the first hysteresis generating unit 201 and the second hysteresis generating unit 202.
In this embodiment, the impedance of the first impedance adjusting subunit 210 and the impedance of the second impedance adjusting subunit 230 in the same working state of the hysteresis comparing circuit are different, so as to precisely define the hysteresis voltage range. Here, the same operation state of the hysteresis comparator refers to an operation state in which the output level is regarded as one without being inverted, and another operation state in which the output level is regarded as the other operation state. Wherein the first impedance adjusting subunit 210 is configured to adjust a positive threshold of the hysteresis voltage, and the second impedance adjusting subunit 230 is configured to adjust a negative threshold of the hysteresis voltage. The specific working principle thereof will be described in detail in the following embodiments.
Referring to fig. 2, optionally, the first impedance adjusting subunit 210 includes a first transistor Q1, a first resistor R1, and a second resistor R2, the first switch subunit 220 includes a second transistor Q2, a first end of the first resistor R1 is connected to the power supply voltage VDD, a second end of the first resistor R1 is connected to a first end of the second resistor R2, a second end of the second resistor R2 is connected to a first pole of the second transistor Q2, a second pole of the second transistor Q2 is connected to the first current source I1, a control terminal of the first transistor Q1 is a control terminal of the first impedance adjusting subunit 210, a first pole of the first transistor Q1 is connected to a first end of the first resistor R1, a second pole of the first transistor Q1 is connected to a second end of the first resistor R1, a control terminal of the second transistor Q2 is a control terminal of the first switch subunit 220, and a second terminal of the second resistor R2 is a second terminal of the first impedance adjusting subunit 210.
The second impedance adjusting subunit 230 includes a third transistor Q3, a third resistor R3, and a fourth resistor R4, the second switching subunit 240 includes a fourth transistor Q4, a first end of the third resistor R3 is connected to the power supply voltage VDD, a second end of the third resistor R3 is connected to a first end of the fourth resistor R4, a second end of the fourth resistor R4 is connected to a first pole of the fourth transistor Q4, a second pole of the fourth transistor Q4 is connected to the first current source I1, a control of the third transistor Q3 is a control end of the second impedance adjusting subunit 230, a first pole of the third transistor Q3 is connected to a first end of the third resistor R3, a second pole of the third transistor Q3 is connected to a second end of the third resistor R3, a control of the fourth transistor Q4 is a control end of the second switching subunit 240, and a second end of the fourth resistor R4 is a second end of the second impedance adjusting subunit 230.
Specifically, when the differential voltage VA-VB input by the first voltage input terminal a and the second voltage input terminal B changes in the forward direction, for example, VA-VB increases gradually from-1V, VA < VB when VA-vb= -1V, the voltage of the first output terminal a2 of the gain amplification module 10 is smaller than the voltage of the second output terminal B2, the current IC2 of the first pole of the second transistor Q2 is larger than the current IC4 of the first pole of the fourth transistor Q4, so that the point E voltage VE is smaller than the point F voltage VF, and the signal output module 30 is controlled by the high voltage output high level of the point F. In this state, the first feedback terminal d1 of the signal output module 30 outputs a low level, the second feedback terminal d2 outputs a high level, the third transistor Q3 is turned on, and the first transistor Q1 is turned off. Therefore, the impedance in the second impedance adjusting subunit 230 is the resistance value of the fourth resistor R4, and the impedance in the first impedance adjusting subunit 210 is the sum of the resistance values of the first resistor R1 and the second resistor R2.
Here, the forward threshold Vth of the hysteresis voltage + Can be expressed as:
wherein VBE4 represents the voltage between the gate (base) and the second electrode (emitter) of the fourth transistor Q4, VBE2 represents the voltage V2 between the gate (base) and the second electrode (emitter) of the second transistor Q2, R1 represents the resistance value of the first resistor R1, R2 represents the resistance value of the second resistor R2, and R4 represents the resistance value of the fourth resistor R4.
When VA-VB changes in the forward direction to a forward threshold value greater than the hysteresis voltage, the voltage of the first output terminal a2 of the gain amplification module 10 is greater than the voltage of the second output terminal b2, the current IC2 of the first pole of the second transistor Q2 is smaller than the current IC4 of the first pole of the fourth transistor Q4, so that the voltage VE of the point E is greater than the voltage VF of the point F, and the signal output module 30 is controlled by the high voltage output low level of the point E. In this state, the first feedback terminal d1 of the signal output module 30 outputs a high level, the second feedback terminal d2 outputs a low level, the third transistor Q3 is turned off, and the first transistor Q1 is turned on.
The differential voltage VA-VB input by the first voltage input terminal a and the second voltage input terminal B gradually decreases from 1V when the differential voltage VA-VB changes in the negative direction, for example, when VA-vb=1v, the third transistor Q3 is turned off and the first transistor Q1 is turned on. When VA-VB is smaller than negative threshold Vth of hysteresis voltage - When the voltage at the first output terminal a2 of the gain amplification module 10 is smaller than the voltage at the second output terminal b2, the current IC2 at the first pole of the second transistor Q2 is larger than the current IC4 at the first pole of the fourth transistor Q4, so that the voltage VE at the point E is smaller than the voltage VF at the point F, and the signal output module 30 is controlled by the high voltage output at the point F to output a high level.
Here, the forward threshold Vth of the hysteresis voltage - Can be expressed as:
wherein R3 represents the resistance of the third resistor R3.
In this embodiment, the signal output by the first feedback end d1 and the signal output by the second feedback end d2 of the signal output module 30 are opposite signals, so that when one of the first transistor Q1 and the third transistor Q3 is on, the other is off, so as to control the impedance of the two branches, thereby realizing the hysteresis function. The range of the hysteresis voltage can be accurately set through the first resistor R1 and the third resistor R3, so that the precision of the hysteresis voltage range is improved.
Alternatively, in the present embodiment, the resistance value of the first resistor R1 is equal to the resistance value of the third resistor R3, and the resistance value of the second resistor R2 is equal to the resistance value of the fourth resistor R4, so that hysteresis can be introduced into the comparison circuit.
Alternatively, the first transistor Q1 and the third transistor Q3 are field effect transistors, and the second transistor Q2 and the fourth transistor Q4 are bipolar junction transistors. The purpose of this arrangement is that by arranging the second transistor Q2 and the fourth transistor Q4 as bipolar junction transistors, matching of layout accuracy can be better achieved, and the influence of the second transistor Q2 and the fourth transistor Q4 on the level inversion threshold value is reduced.
Fig. 3 is a schematic structural diagram of another hysteresis comparing circuit according to the embodiment of the present invention, referring to fig. 3, based on the above technical solutions, optionally, the gain amplifying module 10 includes a first amplifying unit 110 and a second amplifying unit 120, where a control terminal a1 of the first amplifying unit 110 is connected to the first voltage input terminal a, a control terminal B1 of the second amplifying unit 120 is connected to the second voltage input terminal B, an output terminal a2 of the first amplifying unit 110 is connected to the first control terminal c1 of the hysteresis generating module 20, and an output terminal B2 of the second amplifying unit 120 is connected to the third control terminal c3 of the hysteresis generating module 20. Wherein the first amplifying unit 110 and the second amplifying unit 120 together form a differential circuit to amplify the received differential signal.
Referring to fig. 4, the first amplifying unit 110 includes a second current source I2, a fifth resistor R5, and a fifth transistor Q5, wherein an input terminal of the second current source I2 is connected to a power voltage VDD, an output terminal of the second current source I2 is connected to a first pole of the fifth transistor Q5 via the fifth resistor R5, a second pole of the fifth transistor Q5 is grounded, a control terminal a1 of the first amplifying unit 110 is controlled by the fifth transistor Q5, and an output terminal of the second current source I2 is an output terminal a2 of the first amplifying unit 110.
The second amplifying unit 120 includes a third current source I3 and a sixth transistor Q6, where an input end of the third current source I3 is connected to the power supply voltage VDD, an output end of the third current source I3 is connected to a first pole of the sixth transistor Q6, a second pole of the sixth transistor Q6 is grounded, a control terminal of the sixth transistor Q6 is a control terminal b1 of the second amplifying unit 120, and an output end of the third current source I3 is an output terminal b2 of the second amplifying unit 120.
The fifth transistor Q5 and the sixth transistor Q6 are differential input pair transistors formed by bipolar junction transistors, and are used for amplifying differential signals received by the first voltage input terminal a and the second voltage input terminal B. The second current source I2 and the third current source I3 are used for providing bias current for the branch, and the current of the second current source I2 and the current of the third current source I3.
In order to meet the fail-safe function, that is, when the first voltage input terminal a and the second voltage input terminal B are in an open circuit, a short circuit or an idle state, the hysteresis comparison circuit can forcedly output a certain level state, the fifth resistor R5 is set to adjust the level inversion threshold of the hysteresis comparison circuit, and the level inversion threshold is set to be a negative value. Specifically, due to the fifth resistor R5, when the same current flows through the first amplifying unit 110 and the second amplifying unit 120, the point C voltage VC is greater than the point D voltage VD, and vc=vd can be only made to be the negative threshold value flip voltage when the differential voltage VA-VB of the first voltage input terminal a and the second voltage input terminal B is changed in the negative direction.
Fig. 5 is a schematic structural diagram of a signal output module according to an embodiment of the present invention, referring to fig. 5, based on the above technical solutions, optionally, the signal output module 30 includes a common-source common-gate amplifying unit 310, a first inverter INV1, a second inverter INV2, and a Buffer, a first control end of the common-source common-gate amplifying unit 310 is connected to a first output end c5 of the hysteresis generating module 20 as a first control end d3 of the signal output module 30, a second control end of the common-source common-gate amplifying unit 310 is connected to a second output end c6 of the hysteresis generating module 30 as a second control end d4 of the signal output module 30, the output end of the cascode amplifying unit 310 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the second control end c2 of the hysteresis generating module 20 (i.e., the control end of the second impedance adjusting subunit 230), the output end of the second inverter INV2 is connected to the input end of the Buffer and the fourth control end c4 of the hysteresis generating module 20 (i.e., the control end of the first impedance adjusting subunit 210), respectively, and the output end of the Buffer is connected to the signal output end RO of the hysteresis comparing circuit.
Specifically, the cascode amplifying unit 310 includes a seventh transistor Q7, an eighth transistor Q8, a fourth current source I4, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, and a sixteenth transistor Q16. A first pole of the ninth transistor Q9 is connected to the power supply voltage VDD, a second pole of the ninth transistor Q9 is connected to a first pole of the tenth transistor Q10, a second pole of the tenth transistor Q10 is connected to a first pole of the eleventh transistor Q11, a second pole of the eleventh transistor Q11 is connected to a first pole of the twelfth transistor Q12, a second pole of the twelfth transistor Q12 is grounded, a control pole of the ninth transistor Q9 is connected to a control pole of the thirteenth transistor Q13, a control pole of the tenth transistor Q10 is connected to a control pole of the fourteenth transistor Q14, a control pole of the eleventh transistor Q11 is connected to a first pole of the eleventh transistor Q11, and a control pole of the twelfth transistor Q12 is connected to a first pole of the twelfth transistor Q12; the first pole of the thirteenth transistor Q13 is connected to the power supply voltage VDD, the second pole of the thirteenth transistor Q13 is connected to the first pole of the fourteenth transistor Q14, the second pole of the fourteenth transistor Q14 is connected to the first pole of the fifteenth transistor Q15, the second pole of the fifteenth transistor Q15 is connected to the first pole of the sixteenth transistor Q16, the second pole of the sixteenth transistor Q16 is grounded, the control pole of the fifteenth transistor Q15 is connected to the control pole of the eleventh transistor Q11, and the control pole of the sixteenth transistor Q16 is connected to the control pole of the twelfth transistor Q12.
The control electrode of the seventh transistor Q7 is connected to the second end of the second impedance adjusting subunit 230 (i.e., the second output terminal c6 of the hysteresis generating module 20), the first electrode of the seventh transistor Q7 is connected to the second electrode of the ninth transistor Q9, the second electrode of the seventh transistor Q7 is grounded via the fourth current source I4, the control electrode of the eighth transistor Q8 is connected to the second end of the first impedance adjusting subunit 210 (i.e., the first output terminal c5 of the hysteresis generating module 20), the first electrode of the eighth transistor Q8 is connected to the second electrode of the thirteenth transistor Q13, and the second electrode of the eighth transistor Q8 is grounded via the fourth current source I4.
Optionally, the signal output module 30 further includes a current bias unit 320, where the current bias unit 320 is configured to provide a bias current to the cascode unit 310; the current bias unit 320 includes a seventeenth transistor Q17, an eighteenth transistor Q18, a sixth resistor R6, and a fifth current source I5, a first pole of the seventeenth transistor Q17 is connected to the power supply voltage VDD, a second pole of the seventeenth transistor Q17 is connected to a first pole of the eighteenth transistor Q18, a second pole of the eighteenth transistor Q18 is connected to a first end of the sixth resistor R6, a second end of the sixth resistor R6 is grounded via the fifth current source I5, a control pole of the seventeenth transistor Q17 is connected to a control pole of the thirteenth transistor Q13 and a second pole of the eighteenth transistor Q18, and a control pole of the eighteenth transistor Q18 is connected to a control pole of the fourteenth transistor Q14 and a second end of the sixth resistor R6, respectively.
With reference to fig. 1 to 5, the specific working principle of the hysteresis comparison circuit provided in this embodiment is as follows:
the differential voltage VA-VB input by the first voltage input terminal a and the second voltage input terminal B gradually increases from-1V, for example, when the differential voltage VA-VB changes in the forward direction. When VA-vb= -1V, VA < VB, the base-emitter voltage of the fifth transistor Q5 is greater than the base-emitter voltage of the sixth transistor Q6, and therefore, the current flowing through the emitter of the fifth transistor Q5 is greater than the current flowing through the emitter of the sixth transistor Q6, and the C-point voltage VC is less than the D-point voltage VD. Since VC < VD, the collector current of the second transistor Q2 is greater than the collector current of the fourth transistor Q4, so that the point E voltage VE is smaller than the point F voltage VF. The current flowing through the seventh transistor Q7 is larger than the current flowing through the eighth transistor Q8, and since the ninth transistor Q9 and the thirteenth transistor Q13 are fixed bias currents supplied by the current mirror (current bias unit 320), the current flowing through the tenth transistor Q10 is smaller than the current flowing through the fourteenth transistor Q14, and the branch current where the ninth transistor Q9 is located is copied to the fifteenth transistor Q15 and the sixteenth transistor 16 through the current mirror formed by the eleventh transistor Q11 and the twelfth transistor Q12, so that the pull-up current capability of the thirteenth transistor Q13/the fourteenth transistor Q14 is stronger than the pull-down current capability of the fifteenth transistor Q15/the sixteenth transistor Q16, and thus, the G point is high.
The high level of the G point outputs the low level to the control electrode (gate) of the third transistor Q3 through the first inverter INV1, and outputs the high level to the gate of the first transistor Q1 through the second inverter INV2, and the third transistor Q3 is turned on and the first transistor Q1 is turned off. The signal output terminal RO outputs a high level.
When VA-VB changes in the forward direction to a forward threshold value greater than the hysteresis voltage, the base-emitter voltage of the fifth transistor Q5 is less than the base-emitter voltage of the sixth transistor Q6, and therefore, the current flowing through the emitter of the fifth transistor Q5 is less than the current flowing through the emitter of the sixth transistor Q6, and the point C voltage VC is greater than the point D voltage VD. Since VC > VD, the collector current of the second transistor Q2 is smaller than the collector current of the fourth transistor Q4, so that the point E voltage VE is greater than the point F voltage VF. The current flowing through the seventh transistor Q7 is smaller than the current flowing through the eighth transistor Q8 and the current flowing through the tenth transistor Q10 is larger than the current flowing through the fourteenth transistor Q14 so that the pull-up current capability of the thirteenth transistor Q13/fourteenth transistor Q14 is weaker than the pull-down current capability of the fifteenth transistor Q15/sixteenth transistor Q16, and thus, the G point is flipped to a low level.
The low level of the G point outputs the high level to the gate of the third transistor Q3 after passing through the first inverter INV1, and outputs the low level to the gate of the first transistor Q1 after passing through the second inverter INV2, and the third transistor Q3 is turned off and the first transistor Q1 is turned on. The signal output terminal RO outputs a low level.
The differential voltage VA-VB input by the first voltage input terminal a and the second voltage input terminal B gradually decreases from 1V when the differential voltage VA-VB changes in the negative direction, for example, when VA-vb=1v, the third transistor Q3 is turned off and the first transistor Q1 is turned on. When VA-VB is smaller than negative threshold Vth of hysteresis voltage - At this time, the base-emitter voltage of the fifth transistor Q5 is greater than the base-emitter voltage of the sixth transistor Q6, and thus, the current flowing through the emitter of the fifth transistor Q5 is greater than the current flowing through the emitter of the sixth transistor Q6, and the C-point voltage VC is less than the D-point voltage VD. Since VC < VD, the collector current of the second transistor Q2 is greater than the collector current of the fourth transistor Q4, so that the point E voltage VE is smaller than the point F voltage VF. The current flowing through the seventh transistor Q7 is greater than the current flowing through the eighth transistor Q8, the current flowing through the tenth transistor Q10 is less than the current flowing through the fourteenth transistor Q14, the branch current in which the ninth transistor Q9 is located is copied to the fifteenth transistor Q15 and the sixteenth transistor 16 through the current mirror formed by the eleventh transistor Q11 and the twelfth transistor Q12, so that the pull-up current capability of the thirteenth transistor Q13/fourteenth transistor Q14 is greater than the pull-down current capability of the fifteenth transistor Q15/sixteenth transistor Q16, and thus, the G point is flipped high.
The high level of the G point outputs the low level to the control electrode (gate) of the third transistor Q3 through the first inverter INV1, and outputs the high level to the gate of the first transistor Q1 through the second inverter INV2, and the third transistor Q3 is turned on and the first transistor Q1 is turned off. The signal output terminal RO outputs a high level.
In the above technical solutions, the level inversion threshold includes a positive threshold and a negative threshold, that is, a hysteresis voltage range.
In addition, the level inversion threshold is also affected by the power supply voltage VDD, and the fluctuation and noise of the power supply voltage VDD may seriously affect the operation state of the rear circuit (cause inaccuracy of the node voltage, thereby affecting the operation state). Optionally, the hysteresis comparing circuit provided in this embodiment further includes a voltage stabilizing module, configured to provide the power supply voltage VDD to the gain amplifying module 10, the hysteresis generating module 20 and the signal output module 30, so as to reduce the influence of the power supply voltage VDD on the hysteresis voltage range.
In this embodiment, the hysteresis comparator circuit may be adapted for use in a serial communication receiver, where the first voltage input a and the second voltage input B are connected to a BUS.
In a specific embodiment, by setting the resistance values of the first resistor R1 and the third resistor R3, setting the hysteresis voltage range to be (-130 mV, -100 mV), and when the differential signal of the BUS is greater than-100 mV (forward threshold), the hysteresis comparison circuit outputs a high level; when the differential signal of the US bus is smaller than minus 130mV (negative threshold), the hysteresis comparison circuit outputs a low level, so that the requirement of an RS485 bus protocol can be met, and the receiver is effectively prevented from being interfered by noise signals.
Optionally, the invention further provides an electronic chip, such as an RS485 chip, which includes the hysteresis comparing circuit provided by any embodiment of the invention, and by reducing the hysteresis voltage range deviation of the hysteresis comparing circuit, the electronic chip is prevented from outputting an error signal due to the interference of a noise signal in the application process.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A hysteresis comparison circuit, comprising: the first voltage input end, the second voltage input end and the signal output end; further comprises:
The gain amplifying module is used for amplifying the input signals received by the first voltage input end and the second voltage input end;
the first hysteresis generation unit comprises a first impedance adjustment subunit and a first switch subunit, wherein a first end of the first impedance adjustment subunit is connected with a power supply voltage, a second end of the first impedance adjustment subunit is connected with a first end of the first switch subunit, a control end of the first switch subunit is connected with a second output end of the gain amplification module, and the first switch subunit is used for responding to a signal output by the second output end of the gain amplification module and adjusting the voltage of the second end of the first impedance adjustment subunit; the second hysteresis generation unit comprises a second impedance adjustment subunit and a second switch subunit, wherein the first end of the second impedance adjustment subunit is connected with the power supply voltage, the second end of the second impedance adjustment subunit is connected with the first end of the second switch subunit, the control end of the second switch subunit is connected with the first output end of the gain amplification module, and the second switch subunit is used for responding to the signal output by the first output end of the gain amplification module and adjusting the voltage of the second end of the second impedance adjustment subunit;
The control end of the first impedance adjustment subunit is connected with the second feedback end of the signal output module, the control end of the second impedance adjustment subunit is connected with the first feedback end of the signal output module, the first control end of the signal output module is connected with the second end of the first impedance adjustment subunit, the second control end of the signal output module is connected with the second end of the second impedance adjustment subunit, and the output end of the signal output module is connected with the signal output end; the signal output module is used for responding to the voltage of the second end of the first impedance adjustment subunit or the voltage of the second end of the second impedance adjustment subunit to output a level signal from the output end of the signal output module;
the hysteresis generating module is used for generating hysteresis voltage of the input signal according to the feedback signal output by the first feedback end and the feedback signal output by the second feedback end of the signal output module, the first impedance adjusting subunit is used for adjusting the range of the hysteresis voltage according to the feedback signal output by the second feedback end of the signal output module received by the self control unit, and the second impedance adjusting subunit is used for adjusting the range of the hysteresis voltage according to the feedback signal output by the first feedback end of the signal output module received by the self control unit.
2. The hysteresis comparison circuit of claim 1, wherein the hysteresis generation module further comprises a first current source connected to the second terminal of the first switch subunit and the second terminal of the second switch subunit, respectively;
and under the same working state of the hysteresis comparison circuit, the impedance of the first impedance adjusting subunit and the impedance of the second impedance adjusting subunit are different, the first impedance adjusting subunit is used for adjusting the negative threshold value of the hysteresis voltage, and the second impedance adjusting subunit is used for adjusting the positive threshold value of the hysteresis voltage.
3. The hysteresis comparison circuit of claim 2, wherein the first impedance adjustment subunit comprises a first transistor, a first resistor, and a second resistor, the first switch subunit comprises a second transistor, the first terminal of the first resistor is connected to the power supply voltage, the second terminal of the first resistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the first pole of the second transistor, the second pole of the second transistor is connected to the first current source, the control of the first transistor is the control terminal of the first impedance adjustment subunit, the first pole of the first transistor is connected to the first terminal of the first resistor, the second pole of the first transistor is connected to the second terminal of the first resistor, the control terminal of the second transistor is the control terminal of the first switch subunit, and the second terminal of the second resistor is the second terminal of the first impedance adjustment subunit;
The second impedance adjusting subunit comprises a third transistor, a third resistor and a fourth resistor, the second switching subunit comprises a fourth transistor, the first end of the third resistor is connected with the power supply voltage, the second end of the third resistor is connected with the first end of the fourth resistor, the second end of the fourth resistor is connected with the first pole of the fourth transistor, the second pole of the fourth transistor is connected with the first current source, the control of the third transistor is the control end of the second impedance adjusting subunit, the first pole of the third transistor is connected with the first end of the third resistor, the second pole of the third transistor is connected with the second end of the third resistor, the control of the fourth transistor is the control end of the second switching subunit, and the second end of the fourth resistor is the second end of the second impedance adjusting subunit.
4. The hysteresis comparison circuit of claim 3, wherein the first resistor has a resistance equal to the resistance of the third resistor, and the second resistor has a resistance equal to the resistance of the fourth resistor;
the first transistor and the third transistor are field effect transistors, the second transistor and the fourth transistor are bipolar junction transistors, and the first transistor and the third transistor are not conducted at the same time.
5. The hysteresis comparison circuit of claim 1, wherein the gain amplification module comprises a first amplification unit and a second amplification unit, a control terminal of the first amplification unit is connected to the first voltage input terminal, and a control terminal of the second amplification unit is connected to the second voltage input terminal;
the first amplifying unit comprises a second current source, a fifth resistor and a fifth transistor, wherein the input end of the second current source is connected with a power supply voltage, the output end of the second current source is connected with a first pole of the fifth transistor through the fifth resistor, a second pole of the fifth transistor is grounded, the control end of the fifth transistor is a control end of the first amplifying unit, and the output end of the second current source is an output end of the first amplifying unit;
the second amplifying unit comprises a third current source and a sixth transistor, the input end of the third current source is connected with the power supply voltage, the output end of the third current source is connected with the first pole of the sixth transistor, the second pole of the sixth transistor is grounded, the control end of the sixth transistor is the control end of the second amplifying unit, and the output end of the third current source is the output end of the second amplifying unit;
The fifth resistor is used for adjusting the level inversion threshold value of the hysteresis comparison circuit and setting the level inversion threshold value to be a negative value.
6. The hysteresis comparison circuit of claim 1, wherein the signal output module comprises a cascode unit, a first inverter, a second inverter, and a buffer;
the first control end of the cascode amplifying unit is used as a first control end of the signal output module and is connected with the first output end of the hysteresis generating module, the second control end of the cascode amplifying unit is used as a second control end of the signal output module and is connected with the second output end of the hysteresis generating module, the output end of the cascode amplifying unit is connected with the input end of the first inverter, the output end of the first inverter is respectively connected with the input end of the second inverter and the control end of the second impedance adjusting subunit, the output end of the second inverter is respectively connected with the input end of the buffer and the control end of the first impedance adjusting subunit, and the output end of the buffer is used as the output end of the signal output module and is connected with the signal output end of the hysteresis comparing circuit.
7. The hysteresis comparison circuit according to claim 6, wherein the cascode amplifying unit includes a seventh transistor, an eighth transistor, a fourth current source, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;
a first electrode of the ninth transistor is connected to a power supply voltage, a second electrode of the ninth transistor is connected to a first electrode of the tenth transistor, a second electrode of the tenth transistor is connected to a first electrode of the eleventh transistor, a second electrode of the eleventh transistor is connected to a first electrode of the twelfth transistor, a second electrode of the twelfth transistor is grounded, a control electrode of the ninth transistor is connected to a control electrode of the thirteenth transistor, a control electrode of the tenth transistor is connected to a control electrode of the fourteenth transistor, a control electrode of the eleventh transistor is connected to a first electrode of the eleventh transistor, and a control electrode of the twelfth transistor is connected to a first electrode of the twelfth transistor;
a first electrode of the thirteenth transistor is connected to the power supply voltage, a second electrode of the thirteenth transistor is connected to a first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected to a first electrode of the fifteenth transistor, a second electrode of the fifteenth transistor is connected to a first electrode of the sixteenth transistor, a second electrode of the sixteenth transistor is grounded, a control electrode of the fifteenth transistor is connected to a control electrode of the eleventh transistor, and a control electrode of the sixteenth transistor is connected to a control electrode of the twelfth transistor;
The control electrode of the seventh transistor is connected with the second end of the second impedance adjustment subunit, the first electrode of the seventh transistor is connected with the second electrode of the ninth transistor, the second electrode of the seventh transistor is grounded through the fourth current source, the control electrode of the eighth transistor is connected with the second end of the first impedance adjustment subunit, the first electrode of the eighth transistor is connected with the second electrode of the thirteenth transistor, and the second electrode of the eighth transistor is grounded through the fourth current source.
8. The hysteresis comparison circuit of claim 7, wherein the signal output module further comprises a current bias unit for providing a bias current to the cascode amplifying unit;
the current bias unit comprises a seventeenth transistor, an eighteenth transistor, a sixth resistor and a fifth current source, wherein a first electrode of the seventeenth transistor is connected with a power supply voltage, a second electrode of the seventeenth transistor is connected with a first electrode of the eighteenth transistor, a second electrode of the eighteenth transistor is connected with a first end of the sixth resistor, a second end of the sixth resistor is grounded through the fifth current source, a control electrode of the seventeenth transistor is respectively connected with a control electrode of the thirteenth transistor and a second electrode of the eighteenth transistor, and a control electrode of the eighteenth transistor is respectively connected with a control electrode of the fourteenth transistor and a second end of the sixth resistor.
9. The hysteresis comparison circuit of claim 1, further comprising a voltage stabilizing module for providing a supply voltage to the gain amplification module, the hysteresis generation module, and the signal output module.
10. An electronic chip comprising a hysteresis comparison circuit according to any one of claims 1-9.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004304515A (en) * | 2003-03-31 | 2004-10-28 | Matsushita Electric Ind Co Ltd | Comparator with hysteresis |
| DE202014002367U1 (en) * | 2014-03-17 | 2014-04-15 | Dialog Semiconductor Gmbh | Dynamic hysteresis comparator |
| CN114614801A (en) * | 2020-12-09 | 2022-06-10 | 北京兆易创新科技股份有限公司 | Hysteresis comparator and voltage generation circuit |
| CN115756058A (en) * | 2022-11-25 | 2023-03-07 | 圣邦微电子（北京）股份有限公司 | Low dropout regulator and enable control circuit therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4342111B2 (en) * | 2001-01-30 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | Current pulse receiver circuit |
| TWI469527B (en) * | 2009-03-06 | 2015-01-11 | 國立台灣大學 | Method of phase-frequency adjustment and an associated phase-locked circuit |
-
2023
- 2023-10-24 CN CN202311384696.8A patent/CN117118409B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004304515A (en) * | 2003-03-31 | 2004-10-28 | Matsushita Electric Ind Co Ltd | Comparator with hysteresis |
| DE202014002367U1 (en) * | 2014-03-17 | 2014-04-15 | Dialog Semiconductor Gmbh | Dynamic hysteresis comparator |
| CN114614801A (en) * | 2020-12-09 | 2022-06-10 | 北京兆易创新科技股份有限公司 | Hysteresis comparator and voltage generation circuit |
| CN115756058A (en) * | 2022-11-25 | 2023-03-07 | 圣邦微电子（北京）股份有限公司 | Low dropout regulator and enable control circuit therefor |
Non-Patent Citations (2)
| Title |
|---|
| A wide band envelope modulator for envelope tracking RF power amplifiers;Atefeh Salimi;《2013 21st Iranian Conference on Electrical Engineering (ICEE)》;1-4 * |
| 一种应用于CAN收发器的宽输入范围的迟滞比较器设计;冯世勤;《电子技术应用》;52-56 * |
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