CN113848415A - IRF generator, fault resistance generation method and IRF injection method - Google Patents
IRF generator, fault resistance generation method and IRF injection method Download PDFInfo
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Abstract
The application provides an IRF generator, a fault resistance generation method and an IRF injection method, wherein the IRF generator comprises: a programmable resistor; and the control circuit is connected with the programmable resistor to control the programmable resistor to realize resistance change at a speed of nanosecond or more. Therefore, the programmable resistor is controlled by the control circuit, and the high-speed switching control of the resistance value output by the programmable resistor is realized by using a digital circuit control mode, so that the analog requirement of the IRF is met, and a reliable realization basis is provided for the analog reproduction of the IRF fault. Therefore, engineers can use the IRF generator to realize the simulation reproduction of the IRF fault, and the problem that the observation sample is seriously insufficient due to the difficulty in reproduction of the IRF fault at present is solved.
Description
Technical Field
The application relates to the technical field of electronics, in particular to an IRF generator, a fault resistance generation method and an IRF injection method.
Background
Intermittent Faults (IF) are prevalent in various products, and the occurrence of such Faults will result in high maintenance costs and high safety risks. Specifically, IF may result in No fault discovery (No Faults Found, NFF), error removal (ERs Remove, ER), Retest OK (RTOK), and other maintenance issues. Taking an electrical connector as an example, as a basic electromechanical element, the electrical connector is widely used for electrical interconnection among different electronic and electrical devices, and is widely applied in the fields of aerospace, ships, submarines, high-speed railways and the like, and the intermittent fault of the electrical connector may cause a serious problem.
An Intermittent Resistance Fault (IRF) is used as one of the main Intermittent Faults of a circuit, and refers to a fault that a Resistance value at a certain position of an electronic component is randomly mutated from a normal value to an abnormal value for many times, and the normal Resistance value is automatically recovered without any reparative maintenance activity after the Resistance value is continuously maintained for a very short effective time (nanosecond level).
The above-mentioned features of the IRF make it difficult for existing fault simulation and injection methods to simulate such faults. For example, in a conventional fault injection method using a relay, resistance fault injection can be realized by providing a plurality of resistors and using the relay as a switch for opening and closing a short circuit between the resistors.
However, the IRF requires random abrupt resistance change, and the conventional fault injection method based on the relay has only a few fixed resistance values, so that the IRF cannot meet the requirement. Furthermore, since the relay switch speed is fastest in the order of microseconds, the requirement of the fault resistance duration (in nanoseconds) in the IRF is not met, so it cannot simulate such faults.
The occurrence of IRF may cause problems such as errors in the logic function of the digital circuitry, distortion of the analog circuitry signal, etc. However, the detection of IRF is currently immature, mainly because IRF is infrequent and difficult to detect, making the available samples for study limited.
Disclosure of Invention
An object of the embodiments of the present application is to provide an IRF generator, a fault resistance generation method, and an IRF injection method, so as to solve the problem that an IRF fault is difficult to reproduce at present, which results in a serious deficiency of an observation sample.
The embodiment of the application provides an intermittent resistance fault generator, including: a programmable resistor; and the control circuit is connected with the programmable resistor to control the programmable resistor to realize resistance change at a speed of nanosecond or more.
In the implementation process, the programmable resistor is controlled by setting the control circuit, so that the high-speed switching control of the resistance value output by the programmable resistor is realized by using a digital circuit control mode, the analog requirement of the IRF is met, and a reliable implementation basis is provided for the analog recurrence of the IRF fault. Therefore, engineers can use the IRF generator to realize the simulation reproduction of the IRF fault, and the problem that the observation sample is seriously insufficient due to the difficulty in reproduction of the IRF fault at present is solved.
Further, the programmable resistor includes: n groups of resistor groups are connected in series; n is a positive integer greater than or equal to 1; each group of resistor groups comprises 9 basic resistors connected in series and 9 analog switches arranged among the basic resistors and used for controlling the short circuit of the basic resistors; the resistance value of the basic resistor of each resistor group is 1 × 10n-1And ohm, wherein n is the serial number of each resistor group.
Through the implementation process, the output resistance of different resistor groups can be freely controlled from 0 ohm to 1 multiplied by 10N-1Europe is free to control, thereby meeting the simulation requirement of the actual IRF fault.
Furthermore, each group of resistor groups further comprises a decoder, and 9 output pins of the decoder are respectively connected with control ends of the 9 analog switches to control short circuit of each basic resistor.
In the implementation process, the output end of the decoder is connected with the control end of the analog switch, so that the resistance switching at the speed of more than nanosecond can be realized, and the analog requirement of the IRF is met.
The embodiment of the application further provides a method for generating an intermittent fault resistor, which comprises the following steps: randomly generating an inner loop number NsingleThe time length T of the resistor fault activation of the current wheelactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive(ii) a At the TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAnd according to the preset sampling time interval,collecting the current resistance value; the R isfault＝Rnormal+RXSaid R isnormalIs a preset normal resistance value; at the TinctiveAnd maintaining the current resistance value as RnormalCollecting the current resistance value according to a preset sampling time interval; at the TinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle(ii) a If the current resistor fault activation times do not reach NsingleRandomly generating a new round of Tactive、RXAnd TinctiveAt said TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach NsingleUntil the current resistor fault activation times reach Nsingle。
In the implementation process, N is randomly generated by simulating the actual situation of IRF faultsingle、Tactive、RXAnd TinctiveThe method realizes the time sequence simulation of the IRF fault resistance, and continuously collects resistance data in the simulation process, thereby providing a scientific and reliable fault resistance sequence for simulating and reproducing the IRF fault in a circuit by adopting the IRF generator, and further improving the reliability of the finally obtained observation sample.
Further, the method further comprises: the number of current resistor fault activation times reaches NsingleRandomly generating a safety duration Tsafe(ii) a The T issafeGreater than Tinctive(ii) a At the safe time length TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
In practical application, the IRF is often bursty, and after a certain IRF, the IRF failure often occurs again after a certain time. In order to facilitate the control of the IRF generator, in the implementation process, the data simulation of a complete period of an IRF fault can be effectively implemented by continuously acquiring the resistance value of the safe duration, so that the reliability of the finally obtained observation sample is improved.
Further, the method further comprises: at the TsafeWhen the time reaches, whether the number of the current experience safe time length reaches the preset external cycle number N or not is judgedtotal(ii) a If not, then: randomly generating N of a new round of inner circulationsingle(ii) a Generating T of inner loopactive、RXAnd TinctiveAt said TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle(ii) a If not, repeating the above process until the current resistor fault activation times reach Nsingle(ii) a The number of current resistor fault activation times reaches NsingleThen, a new T is randomly generatedsafeAnd during the safety time period TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
In the implementation process, the simulation of the reliable resistance sequence of the IRF fault for a plurality of times is realized by setting the external cycle times, so that the IRF generator can be conveniently controlled, and the reliability of the finally obtained observation sample is improved.
The embodiment of the application also provides an injection method of intermittent resistance faults, which comprises the following steps: acquiring a fault resistance value sequence; connecting a preset intermittent resistance fault generator into a circuit to be simulated; and controlling the intermittent resistance fault generator to sequentially generate each resistor according to the fault resistance value sequence.
In the implementation process, the IRF generator is connected into the circuit to be simulated, and the resistors are sequentially generated according to the fault resistance value sequence, so that the IRF is injected, an IRF fault is generated in the circuit to be simulated according to the injected resistor of the IRF generator, the IRF fault is repeated, and a corresponding observation sample is obtained.
Further, the obtaining of the fault resistance value sequence includes: according to any one of the above methods for generating intermittent fault resistance, the resistance values are sequentially collected according to a time sequence, and the fault resistance value sequence is obtained.
Further, the intermittent resistive fault generator is any one of the aforementioned intermittent resistive fault generators.
Further, the preset intermittent resistance fault generator is an intermittent resistance fault generator which is simulated on the simulation equipment by using simulation software; the circuit to be simulated is a circuit to be simulated on simulation equipment by utilizing simulation software; the preset intermittent resistance fault generator is connected into a circuit to be simulated, and the method comprises the following steps: in the simulation process, the simulated intermittent resistance fault generator is connected into the circuit to be simulated; the structure of the simulated intermittent resistive fault generator is consistent with that of any one of the intermittent resistive fault generators.
The embodiment of the present application further provides a device for generating an intermittent fault resistor, including: a generation module and an execution module; the generation module is used for randomly generating the internal circulation times NsingleThe time length T of the resistor fault activation of the current wheelactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive(ii) a The execution module is used for executing the execution at the TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultCollecting the current resistance value according to a preset sampling time interval; the R isfault＝Rnormal+RXSaid R isnormalIs a preset normal resistance value; at the TinctiveAnd maintaining the current resistance value as RnormalCollecting the current resistance value according to a preset sampling time interval; at the TinctiveWhen the current resistor fault activation times reach the preset value, judging whether the current resistor fault activation times reach the preset valueNsingle(ii) a The generation module is further used for judging whether the current resistor fault activation times are less than NsingleRandomly generating a new round of Tactive、RXAnd Tinctive(ii) a The execution module is further configured to execute the program at TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach NsingleUntil the current resistor fault activation times reach Nsingle。
The embodiment of the application also provides electronic equipment, which comprises a processor, a memory and a communication bus; the communication bus is used for realizing connection communication between the processor and the memory; the processor is configured to execute one or more programs stored in the memory to implement any of the above methods for generating intermittent fault resistance.
There is also provided in an embodiment of the present application a computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement any of the above methods for generating intermittent fault resistance.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic flowchart of an intermittent resistive fault injection method according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a method for generating an intermittent fault resistor according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of a specific method for generating an intermittent fault resistor according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an IRF generator according to an embodiment of the present application;
FIG. 5 is a circuit diagram of a single set of resistors provided in accordance with an embodiment of the present application;
fig. 6 is a sequence diagram of fault resistance values of an IRF according to an embodiment of the present application;
FIG. 7 is a diagram of a fault resistance value sequence of the IRF shown in FIG. 6 and enlarged in phantom according to an embodiment of the present disclosure;
fig. 8 is a block diagram of an IRF generator according to an embodiment of the present application;
fig. 9 is a block diagram of a control circuit according to an embodiment of the present disclosure;
fig. 10 is a circuit diagram of a control circuit according to an embodiment of the present application;
fig. 11 is a circuit diagram of an exemplary simulation circuit of IRF soft injection according to an exemplary embodiment of the present application;
fig. 12 is an IRF soft injection simulation waveform of an exemplary embodiment provided in an embodiment of the present application;
fig. 13 is a schematic structural diagram of an intermittent fault resistance generation apparatus according to an embodiment of the present application;
fig. 14 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
The first embodiment is as follows:
in order to realize the simulation of the IRF and provide more observation samples of the IRF fault, the embodiment of the application provides an IRF injection method, an IRF generator applicable to the IRF injection method and generation of intermittent fault resistance.
Referring to fig. 1, fig. 1 is a schematic diagram of an IRF implantation method provided in an embodiment of the present application, including:
s101: and acquiring a fault resistance value sequence.
It should be noted that, in the embodiment of the present application, a fault resistance value sequence that better conforms to an IRF fault rule may be acquired and acquired by a method of constructing an IRF model.
For example, see fig. 2 for an illustration:
s201: randomly generating an inner loop number Nsingle。
S202: randomly generating the current round of resistor fault activation duration TactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive。
It should be noted that, in the embodiment of the present application, engineers and other related personnel may vibrate the circuit board by using devices such as small vibration exciters on various circuit boards, so as to count and select the range of the sudden change of resistance value, the range of the sudden change of resistance value duration (i.e., the activation duration of the resistance fault), the range of the deactivation duration of the resistance fault, the range of the interval duration (i.e., the safety duration) between two IRF faults, and how many times the sudden change of resistance value (i.e., N) occurs when one round of IRF fault occurs in the vibration process of the circuit board, so that the IRF fault occurs on the circuit boardsingle) The range of (c), and the like.
Optionally, NsingleMay range from 1 to 20 integers.
Optionally, TactiveMay range from 0.6ns to 10 ns. It should be noted that ns is a unit of nanosecond.
Optionally, TinctiveMay range from 0.3ns to 0.6 ns.
Optionally, RXMay range from 10 Ω to 100k Ω. In addition, Ω is the unit "ohm" of resistance, and k Ω is the unit "kilo ohm" of resistance.
It should be understood that the above ranges are merely preferred values of the parameters obtained by the inventors through statistical screening in the experiments, and are not intended to be limiting. In practical applications, the above ranges may vary from experiment to experiment.
In the embodiment of the application, N can be obtained through statisticssingle、Tactive、RXAnd TinctiveIn respective corresponding ranges, randomly generating Nsingle、Tactive、RXAnd Tinctive。
It should be noted that, in the embodiment of the present application, an engineer may also count the distribution rule of each parameter, so as to set the random value of each parameter according to the distribution rule corresponding to each parameter.
S203: in the generation of Nsingle、Tactive、RXAnd TinctiveThen, at TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAnd collecting the current resistance value according to a preset sampling time interval.
S204: at TactiveAfter the time length is reached, the T is enteredinctiveThe duration is kept, and the current resistance value is kept to be the preset normal resistance value RnormalAnd collecting the current resistance value according to a preset sampling time interval.
In the examples of the present application, R isfault＝Rnormal+RX。
Also, R isnormalFor the engineer to set, depending on the actual circuit conditions, e.g. to simulate intermittent resistive faults in the electrical connector, RnormalMay be set to 0.
S205: at TinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle。
If the IRF fault is reached, the process can be ended, and the fault resistance value sequence of the IRF fault is acquired at this time.
If not, go to step S202, and re-execute steps S202 to S205 until the current number of resistor failure activations reaches NsingleUntil now.
It should be noted that there is no timing relationship between step S201 and step S202. However, in one round of the inner loop process, step S201 is executed only once, and the number of execution times from step S202 to step S205 is equal to NsingleIs correlated.
It should be understood that, only one fault resistance value sequence related to an IRF fault is acquired in the above process, and an engineer may obtain a plurality of fault resistance value sequences by repeatedly executing the above manner, so as to meet the simulation requirement for the IRF fault accessing to the circuit to be simulated.
It should be understood that there will often be a certain interval between two adjacent IRF faults (relative to the time length of the interval between two adjacent sudden resistance changes in one IRF fault (i.e. T)inctive) In other words, the interval tends to be longer).
For this reason, in the embodiment of the present application, the engineer may obtain a plurality of fault resistance value sequences by repeatedly performing the above-described manner, and set the output interval duration between two adjacent fault resistance value sequences by himself/herself when programming the intermittent resistive fault generator.
In addition, in a possible implementation manner of the embodiment of the present application, an interval duration (i.e., a safety duration T) of two IRF failures may also be configured in the constructed IRF modelsafe)。
In the feasible implementation mode, the activation times can reach N at the current resistor faultsingleRandomly generating a safety duration Tsafe. In the embodiment of the present application, T may be setsafeGreater than Tinctive。
Optionally, the safety duration T may be randomly generated in a range of 1ns to 1min (minute)safe。
Note that the safety duration TsafeThe information may be generated together when step S201 or S202 is executed, and is not limited herein.
The number of current resistor fault activation times reaches NsingleWhen it comes to TsafeDuration, at which the current resistance value is kept at RnormalAnd collecting the current resistance value according to a preset sampling time interval.
In this way, an engineer may not be required to set the length of the output interval and the resulting resistance between the collected series of fault resistance values.
In addition, the present application implementsFor example, referring to FIG. 3, an external cycle number N may be presettotal。
So that the current resistor malfunction activation number reaches N as a result of the determination in step S205singleThen, it is no longer directly ended, but:
s206: randomly generating TsafeAt TsafeIn the resistor, the current resistance value is kept to be RnormalAnd collecting the current resistance value according to a preset sampling time interval.
S207: at TsafeWhen the time reaches, whether the number of times of the current experience safety duration reaches N is judgedtotal。
If so, ending the process, and outputting a related fault resistance value sequence for IRF fault for multiple times.
If not, the process may go to step S201, so as to re-execute steps S201 to S207 until the number of times of the current safety duration reaches NtotalUntil now.
It should be noted that, in the embodiment of the present application, the preset sampling time interval may be 0.1ns, but is not limited thereto. The engineer may set the sampling interval according to a randomly generated minimum precision for each duration.
It should be noted that the above manner of acquiring the fault resistance value sequence is only the manner exemplified in the embodiment of the present application. In the practical application process, the fault resistance value sequence can be obtained in other modes. For example, an engineer may obtain a value range of the corresponding parameter through statistics, and then set the fault resistance value sequence in the setting range in a manual definition manner. In the embodiment of the present application, a method for acquiring a fault resistance value sequence is not limited.
S102: and connecting a preset intermittent resistance fault generator into a circuit to be simulated.
It should be noted that there is no timing relationship between steps S101 and S102 in the embodiment of the present application.
It should also be noted that in the embodiment of the present application, the structure of the intermittent resistive fault generator can be seen from fig. 4, which includes a programmable resistor and a control circuit.
In the embodiment of the application, the control circuit is connected with the programmable resistor to control the programmable resistor to realize resistance change at a speed of nanosecond or more.
In the embodiment of the present application, in order to control the Programmable resistor to realize the resistance change at a speed of nanosecond or more, the control circuit needs to have a high switching speed and good parallelism, so in the embodiment of the present application, the control circuit may be implemented by a Field-Programmable Gate Array (FPGA), for example, chips such as QL6250-4PQ208C and EP4CE6E22C8, but is not limited thereto.
In this embodiment, in order to satisfy the free varistor capability of the programmable resistor, in this embodiment, the programmable resistor may include: the resistance group of N group that connects in series, and every group resistance group includes 9 basic resistances that connect in series and sets up between each basic resistance, is used for controlling each basic resistance short circuit's a plurality of switches. And the resistance value of the basic resistor of each resistor group is 1 × 10n-1N is the number (1 to N) of each resistor group. Thus, a resistance from 0 ohm to 10 ohm can be realizedN-1Free control of europe.
Wherein, N is a positive integer which is determined by an engineer according to actual needs and is more than or equal to 1.
For example, if it is actually required to realize free control of the resistance value between 0 ohm and 999 kilo-ohm, 6 sets of resistors may be provided, the first set includes 9 basic resistors with a resistance value of 1 ohm, the second set includes 9 basic resistors with a resistance value of 10 ohm, the third set includes 9 basic resistors with a resistance value of 100 ohm, the fourth set includes 9 basic resistors with a resistance value of 1 kilo-ohm, the fifth set includes 9 basic resistors with a resistance value of 10 kilo-ohm, and the sixth set includes 9 basic resistors with a resistance value of 100 kilo-ohm.
In order to realize the control of each basic resistor, in the embodiment of the present application, an analog switch is disposed between each basic resistor (for example, an ADG822BRM chip is used to realize the control, and one ADG822BRM chip may realize two analog switches). By arranging 9 analog switches, the quantity control of the conducted basic resistors is realized, and the control of the output resistance value is realized.
For example, referring to fig. 5, fig. 5 shows a connection structure of analog switches to which the respective basic resistors are connected.
In order to reduce the pin resources required for controlling the analog switch, a decoder may be further used to implement the control of the analog switch in the embodiment of the present application. Such as a 4-line to 10-line decoder, e.g., a 74HC42 decoder, etc. The 9 output pins of the decoder can be respectively connected with the 9 basic resistors to control the short circuit of each basic resistor. And 4 input pins of the 4-line-10-line decoder can be connected with the control circuit to receive the control of the control circuit and realize the short circuit of the corresponding basic resistor.
For example, referring to fig. 5, fig. 5 shows a connection structure of a master switch using a 74HC42 decoder as a resistor group, and an analog switch using an ADG822BRM chip to realize access of each basic resistor. With this structure, short-circuit control of any number of resistors can be realized.
It should be noted that fig. 5 shows a resistor group structure with a basic resistance of 1 ohm, and other resistor group structures are similar to the resistor group structure and are not illustrated again.
It should be noted that, in the embodiment of the present application, only one analog switch at most is allowed to be closed in one resistor group.
S103: and controlling the intermittent resistance fault generator to sequentially generate each resistor according to the fault resistance value sequence.
It should be noted that, in the embodiment of the present application, corresponding intermittent resistive fault generator hardware may be produced according to the above-mentioned intermittent resistive fault generator structure, and is connected to an actual circuit to be simulated, so that each resistor is sequentially generated according to a fault resistance value sequence, and hardware injection for an intermittent resistive fault is implemented.
In addition, in the embodiment of the application, the intermittent resistance fault generator and the circuit to be simulated can be simulated on the simulation equipment by using simulation software, the simulated intermittent resistance fault generator is connected into the circuit to be simulated in the simulation process, and then the simulated intermittent resistance fault generator is controlled to sequentially generate each resistor according to the fault resistance value sequence by using the simulation technology, so that the software injection of the intermittent resistance fault is realized.
In addition, in the embodiment of the application, the simulation software can be used for controlling the simulated intermittent resistance fault generator to sequentially generate the resistors according to the fault resistance value sequence by using a simulation technology, then the fault resistance value sequence is sent to the lower computer through communication modes such as a serial port and the like, and the lower computer controls the programmable resistor according to the simulated fault resistance value sequence after receiving the data, so that semi-simulation semi-physical injection of the intermittent resistance fault is realized.
It should be noted that the circuit to be simulated in the embodiment of the present application may be any existing circuit having a resistance element, which may be selected by an engineer according to actual observation needs, and is not limited in the embodiment of the present application.
According to the IRF generator, the fault resistance generation method and the IRF injection method, the IRF generator can effectively achieve resistance conversion above a nanosecond level, and the resistance value can effectively and randomly change, so that the simulation requirement of the IRF is met, and a reliable realization basis is provided for simulation reproduction of IRF faults. The method for generating the fault resistance provided by the embodiment of the application can ensure the randomness and the mutability of the obtained fault resistance value sequence and ensure that the injected resistance can reproduce the IRF fault. By the IRF injection method, the IRF fault recurrence is effectively realized, and therefore effective research samples are provided for researches related to the IRF fault detection, the intermittent resistance fault diagnosis and the electronic system residual life prediction.
Example two:
the embodiment further illustrates the scheme of the present application by taking a specific implementation process as an example on the basis of the first embodiment.
Firstly, an IRF model is constructed. In the IRF model:
And 3, starting simulation, entering a fault period from the moment, and experiencing the fault activation time length T of the random resistance of 0.6ns-10nsactiveDuring the time period, the fault is in an activated state, and the resistance is Rfault，Rfault＝Rnormal+RX，RnormalIs a predetermined normal resistance value, RXRandom values of 10 Ω to 100k Ω.
Secondly, based on the IRF model, relevant variables (the parameters needing to be assigned are the variables) are defined through software programming, and the steps are completed, so that the fault resistance value sequence of the intermittent resistance fault can be obtained.
In this embodiment, a sampling time interval of 0.1ns may be defined. And two arrays (vectors) T and R can be defined and are respectively used for storing the time series and the fault resistance value series corresponding to the time series.
The T vector is a discrete time series of increasing arithmetic differences, the first term is 0, the tolerance is 0.1, and the unit is ns. And then assigning values to the variables according to the steps in the first step, executing the steps, automatically generating a discrete time sequence T according to the interval of 0.1ns in the executing process, and continuously collecting the latest resistance value in the executing process according to the interval of 0.1ns to obtain a fault resistance value sequence R corresponding to T.
In an embodiment of the present application, the obtained result of the fault resistance value sequence of the intermittent resistance fault can be seen in fig. 6, wherein an enlarged view in a dashed box of fig. 6 is seen in fig. 7.
And thirdly, constructing an IRF generator model.
In this embodiment, the IRF generator is composed of a high-speed programmable resistor and a control circuit, and a block diagram of the IRF generator is shown in fig. 8, wherein A, B is a resistance output terminal of the IRF generator, and C1 to C6 are control terminals from a resistance group with a basic resistance of 1 Ω to a resistance group with a basic resistance of 100k Ω.
In the IRF generator of the present embodiment, the structure of each resistor group can be seen in fig. 5.
Referring to fig. 5, the resistor group shown in fig. 5 is a resistor group in which 9 1 Ω resistors (R1 to R9) are connected in series. Then, 9 analog switches are used for respectively controlling short circuits of resistors with corresponding numbers. In fig. 5, a1 and B1 are output terminals of the resistor group.
In the embodiment of the application, the analog switches with the numbers of S0-S8 can be given, the analog switch with the number of S0 is closed, and the other analog switches are opened, so that 9 resistors are short-circuited, and the output resistor is 0 ohm. And the S1 analog switch is closed and is otherwise opened, so that 8 resistors are short-circuited, and the output resistance is 1 ohm. Closing other opens of the analog switch S2 will short circuit 7 resistors, the output resistance is 2 ohm, and so on, when closing other opens of the analog switch S8, the output resistance is 8 ohm, when all opens of the last 9 analog switches, the output resistance is 9 ohm, the output resistance is not short-circuited.
In this embodiment, considering that an analog switch with low on-resistance and low transmission delay is often required in practical application, the analog switch in this embodiment may be implemented by using an ADG822BRM chip, and the short circuit of a specified number of resistors may be controlled by controlling the on-state of the analog switch in the ADG822BRM chip, so as to implement the output of a specified resistance value.
Because the number of pins to be controlled is large, in the embodiment of the present application, in order to save pin resources, a 4-line-10-line decoder may be used to control 9 analog switches. The output end 0 to the output end 8 of the decoder are connected with the input of the analog switch from the No. S0 to the analog switch from the No. S8, when the input of the analog switch is in a low level, the analog switch is closed, otherwise, the analog switch is opened. When a 4-bit binary number (range 0000b to 1001b) is input to the input terminal of the decoder, the output resistance of the set of resistors is identical to the number. For example, when the decoder input is binary number 0000b, output 0 will be set low and outputs 1 to 8 will be set high, corresponding to analog switch # S0 will be closed and analog switches # S1 to # S8 will be open, which causes 9 resistors to be shorted and the output resistor to be 0 ohms.
In addition, considering that low propagation delay is required for the simulation of intermittent resistive faults, in the embodiment of the present application, the decoder of the present example may employ a 74HC42 chip which is a high-speed HC series.
In this embodiment, the four input terminals of the decoder may be connected to the control circuit, and serve as the control terminals of the resistor group, so as to be controlled by the control circuit.
In this embodiment, 10 Ω, 100 Ω, 1k Ω, 10k Ω, and 100k Ω resistor groups are also constructed, and the structure of each resistor group is similar to that shown in fig. 5, and will not be described again. The resistor groups are connected in series through output ends.
In this embodiment, in consideration of the fact that a control circuit needs to have a higher switching speed and better parallelism for controlling the high-speed programmable resistor to simulate the IRF, an FPGA chip may be used as the control circuit in this embodiment.
In this embodiment, each group of resistors is controlled by a 4-10 line decoder, and six groups of resistors are used, so that 24 pins of the FPGA are required to complete the control of the whole programmable resistor, that is, the adopted FPGA chip has at least 24 general I/O pins. For this purpose, the present example is implemented using the EP4CE6E22C8 chip to meet the above requirements. The structural block diagram of the control circuit can be seen in fig. 9. Wherein, the ends C1-C6 are respectively used for controlling the resistance groups from 1 omega to 100k omega, and the total number is 24 control lines. The actual circuit diagram of the control circuit is shown in fig. 10. Wherein C1-C6 correspond to C1-C6 in FIG. 9. In fig. 10, the VCC power supply pin, GND, and clk are the zero potential pins and the clock input pin, respectively
In the embodiment, the high-speed programmable resistor can be controlled to simulate a fault resistance sequence in time sequence by programming the control circuit.
Fourthly, IRF injection.
1. And (3) realizing soft injection:
the present embodiment employs an asynchronous binary counter as a circuit to be simulated. Firstly, an IRF generator is simulated by using circuit simulation software, then the IRF generator is packaged into a secondary block, only the output end of the secondary block is led out, and then the output end of the secondary block is connected in series in a certain branch of an asynchronous binary counter circuit, so that the IRF of the branch can be injected.
In this example, the clock input terminal CLK of the asynchronous binary counter circuit is selected as the injection target, the simulation circuit is shown in fig. 11, and the simulation waveform is shown in fig. 12.
2. And (3) realizing hard injection:
the circuit diagram of the IRF generator designed in the foregoing draws a PCB circuit board, and the hardware IRF generator can be realized by programming a control circuit.
The output end of the hardware IRF generator is connected in series into a certain branch of the actual asynchronous binary counter circuit, and then IRF hard injection can be carried out on the branch. Similar to IRF soft injection, this example selects the clock input terminal CLK as the injection object, and connects the output terminal of the hardware IRF generator in series with the CLK branch to realize IRF hard injection to the CLK branch.
Compared with the existing fault injection method based on the relay, the fault injection method based on the relay combines the intermittent resistor fault model, so that the resistance values of the serially connected resistors are ensured to be randomly and suddenly changed, the fault injection method based on the relay accords with the fault characteristic of the intermittent resistors, and the usability of the input resistance values of the resistors is ensured. The IRF generator can realize resistance conversion above nanosecond level, so that the simulation requirement of the IRF is met, and a reliable realization basis is provided for the simulation reproduction of IRF faults. The existing fault injection method can not make the serially connected resistors change suddenly randomly along with time, and can not make the sudden change of the resistors conform to an intermittent resistor fault model, so that the faults can not be simulated. In addition, the soft injection and hard injection method utilizing the intermittent resistance fault can provide research samples for intermittent resistance fault detection, intermittent resistance fault diagnosis and residual life prediction research of an electronic system. The IRF model constructed by the method is simple and clear, IRF injection to the circuit can be achieved based on the IRF generator, and intermittent resistance faults in the circuit can be effectively simulated by the method. On the basis, the method and the device can provide technical support and simulation tools for intermittent resistance fault detection, intermittent resistance fault diagnosis and residual life prediction research of the circuit system. The method is simple and easy to implement, the practicability is high, and the provided IRF data sample is real and reliable.
Example three:
based on the same inventive concept, the embodiment of the present application further provides an intermittent fault resistance generation apparatus 100. Referring to fig. 13, fig. 13 shows an intermittent fault resistance generation apparatus 100 corresponding to the method shown in fig. 2 and 3. It should be understood that the specific functions of the intermittent fault resistance generation device 100 can be referred to the above description, and the detailed description is appropriately omitted here to avoid redundancy. The intermittent fault resistance generation device 100 includes at least one software function module that can be stored in a memory in the form of software or firmware or that is solidified in the operating system of the intermittent fault resistance generation device 100. Specifically, the method comprises the following steps:
referring to fig. 13, the intermittent fault resistance generation apparatus 100 includes: a generation module 101 and an execution module 102. Wherein:
the generating module 101 is configured to randomly generate an inner loop number NsingleThe time length T of the resistor fault activation of the current wheelactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive；
The execution module 102 is used for executingT isactiveIn the method, the current resistance value is kept as the fault resistance value RfaultCollecting the current resistance value according to a preset sampling time interval; the R isfault＝Rnormal+RXSaid R isnormalIs a preset normal resistance value; at the TinctiveAnd maintaining the current resistance value as RnormalCollecting the current resistance value according to a preset sampling time interval; at the TinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle；
The generating module 101 is further configured to, if the current resistor fault activation frequency does not reach the NsingleRandomly generating a new round of Tactive、RXAnd Tinctive；
The execution module 102 is further configured to execute the program at TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach NsingleUntil the current resistor fault activation times reach Nsingle。
In this embodiment of the present application, the generating module 101 is further configured to activate the current resistor for the number of times NsingleRandomly generating a safety duration Tsafe(ii) a The T issafeGreater than Tinctive(ii) a The execution module 102 is further configured to determine the safe duration TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
In this embodiment, the execution module 102 is further configured to execute the instruction at TsafeWhen the time reaches, whether the number of the current experience safe time length reaches the preset external cycle number N or not is judgedtotal；
The generating module 101 is further configured to randomly generate a new round of inner loop if the new round of inner loop is not reachedNsingleGenerating T of inner loopactive、RXAnd Tinctive；
The execution module 102 is further configured to execute the program at TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle(ii) a If not, repeating the above process until the current resistor fault activation times reach Nsingle；
The generating module 101 is further configured to activate the current resistor for the number of times NsingleThen, a new T is randomly generatedsafe；
The execution module 102 is further configured to execute the safe duration TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
It should be understood that, for the sake of brevity, the contents described in some embodiments are not repeated in this embodiment.
Example four:
the present embodiment provides an electronic device, which is shown in fig. 14 and includes a processor 1401, a memory 1402, and a communication bus 1403. Wherein:
the communication bus 1403 is used for enabling connection communication between the processor 1401 and the memory 1402.
The processor 1401 is configured to execute one or more programs stored in the memory 1402, so as to implement the intermittent fault resistance generation method in the first embodiment.
It will be appreciated that the configuration shown in fig. 14 is merely illustrative and that the electronic device may include more or fewer components than shown in fig. 14 or have a different configuration than shown in fig. 14.
The present embodiment also provides a readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash Memory, a usb (Secure Digital Card), an MMC (Multimedia Card), etc., in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the method for generating an intermittent fault resistor in the first embodiment. And will not be described in detail herein.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In this context, a plurality means two or more.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (13)
1. An intermittent resistive fault generator, comprising:
a programmable resistor;
and the control circuit is connected with the programmable resistor to control the programmable resistor to realize resistance change at a speed of nanosecond or more.
2. The intermittent resistive fault generator of claim 1, wherein the programmable resistor comprises:
n groups of resistor groups are connected in series; n is a positive integer greater than or equal to 1;
each group of resistor groups comprises 9 basic resistors connected in series and 9 analog switches arranged among the basic resistors and used for controlling the short circuit of the basic resistors;
the resistance value of the basic resistor of each resistor group is 1 × 10n-1And ohm, wherein n is the serial number of each resistor group.
3. The intermittent resistive fault generator of claim 2, wherein each group of resistor groups further comprises a decoder, and 9 output pins of the decoder are respectively connected with control terminals of 9 of the analog switches to control each basic resistor to be shorted.
4. A method of generating intermittent fault resistance, comprising:
randomly generating an inner loop number NsingleThe time length T of the resistor fault activation of the current wheelactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive；
At the TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultCollecting the current resistance value according to a preset sampling time interval; the R isfault＝Rnormal+RXSaid R isnormalIs a preset normal resistance value;
at the TinctiveAnd maintaining the current resistance value as RnormalCollecting the current resistance value according to a preset sampling time interval;
at the TinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle；
If the current resistor fault activation times do not reach NsingleRandomly generating a new round of Tactive、RXAnd TinctiveAt said TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach NsingleUntil the current resistor fault activation times reach Nsingle。
5. The method of generating intermittent fault resistance of claim 4, further comprising:
the number of current resistor fault activation times reaches NsingleRandomly generating a safety duration Tsafe(ii) a The T issafeGreater than Tinctive；
At the safe time length TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
6. The method for generating intermittent fault resistance of claim 5, further comprising:
at the TsafeWhen the time reaches, whether the number of the current experience safe time length reaches the preset external cycle number N or not is judgedtotal；
If not, then:
randomly generating N of a new round of inner circulationsingle；
Generating T of inner loopactive、RXAnd TinctiveAt said TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle(ii) a If not, repeating the above process until the current resistor fault activation times reach Nsingle；
The number of current resistor fault activation times reaches NsingleThen, a new T is randomly generatedsafeAnd during the safety time period TsafeAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval.
7. A method of injecting an intermittent resistive fault, comprising:
acquiring a fault resistance value sequence;
connecting a preset intermittent resistance fault generator into a circuit to be simulated;
and controlling the intermittent resistance fault generator to sequentially generate each resistor according to the fault resistance value sequence.
8. The intermittent resistive fault injection method of claim 7, wherein the obtaining a fault resistance value sequence comprises:
the intermittent fault resistance generation method of any one of claims 4 to 6, wherein the fault resistance value sequence is obtained by sequentially collecting resistance values in a time sequence.
9. The intermittent resistive fault injection method of claim 7, wherein the intermittent resistive fault generator is as claimed in any one of claims 1 to 3.
10. The intermittent resistive fault injection method of claim 7,
the preset intermittent resistance fault generator is an intermittent resistance fault generator which is simulated on the simulation equipment by using simulation software; the circuit to be simulated is a circuit to be simulated on simulation equipment by utilizing simulation software;
the preset intermittent resistance fault generator is connected into a circuit to be simulated, and the method comprises the following steps:
in the simulation process, the simulated intermittent resistance fault generator is connected into the circuit to be simulated;
the structure of the simulated intermittent resistive fault generator is in accordance with the structure of the intermittent resistive fault generator of any one of claims 1 to 3.
11. An intermittent fault resistance generation apparatus, comprising: a generation module and an execution module;
the generation module is used for randomly generating the internal circulation times NsingleThe time length T of the resistor fault activation of the current wheelactiveResistance value of RXAnd a resistance fault deactivation time period Tinctive；
The execution module is used for executing the execution at the TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultCollecting the current resistance value according to a preset sampling time interval; the R isfault＝Rnormal+RXSaid R isnormalIs a preset normal resistance value; at the TinctiveAnd maintaining the current resistance value as RnormalCollecting the current resistance value according to a preset sampling time interval; at the TinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach Nsingle；
The generation module is further used for judging whether the current resistor fault activation times are less than NsingleRandomly generating a new round of Tactive、RXAnd Tinctive；
The execution module is further configured to execute the program at TactiveIn the method, the current resistance value is kept as the fault resistance value RfaultAt said TinctiveAnd maintaining the current resistance value as RnormalAnd collecting the current resistance value according to a preset sampling time interval, wherein T isinctiveWhen the current resistance fault activation times reach N, judging whether the current resistance fault activation times reach NsingleUntil the current resistor fault activation times reach Nsingle。
12. An electronic device, comprising: a processor, a memory, and a communication bus;
the communication bus is used for realizing connection communication between the processor and the memory;
the processor is configured to execute one or more programs stored in the memory to implement the intermittent fault resistance generation method of any one of claims 4 to 6.
13. A computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the intermittent fault resistance generation method according to any one of claims 4 to 6.
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