CN210431389U - Oscillator circuit and integrated circuit - Google Patents
Oscillator circuit and integrated circuit Download PDFInfo
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- CN210431389U CN210431389U CN201921080888.9U CN201921080888U CN210431389U CN 210431389 U CN210431389 U CN 210431389U CN 201921080888 U CN201921080888 U CN 201921080888U CN 210431389 U CN210431389 U CN 210431389U
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Abstract
An oscillating circuit forms bias current at the input end of a mirror image circuit through a self-starting reference circuit, the mirror image bias current of the mirror image circuit generates reference current, the reference current is connected to an oscillating unit to generate oscillating signals and output the oscillating signals through shaping.
Description
Technical Field
The application belongs to the technical field of CMOS integrated circuit design, and particularly relates to an oscillating circuit and an integrated circuit.
Background
Oscillators are an integral part of many electronic systems, applications ranging from clock generation in microprocessors to carrier synthesis in cellular telephones, requiring widely varying structural and performance parameters. The design of stable, high performance oscillators using CMOS processes continues to present a significant challenge.
The CMOS oscillator designed in the current process is generally a ring oscillator, which is composed of a current reference circuit, a ring oscillation unit, and a shaping circuit. The current reference circuit adopts a current mirror structure, and generates bias independent of a power supply. The ring oscillation unit generates an oscillation signal by charging and discharging through reference current, and a starting circuit is required to be added to a current reference circuit of a traditional oscillation circuit, so that the circuit structure is more complex. The start-up circuit also causes additional power consumption, so that the overall power consumption of the oscillating circuit is high.
Disclosure of Invention
The application aims to provide an oscillating circuit and an integrated circuit, and aims to solve the problems that a traditional oscillating circuit needs a starting circuit, the circuit structure is complex, and extra power consumption is caused.
A first aspect of an embodiment of the present application provides an oscillation circuit, including:
an output terminal;
the power supply terminal is used for accessing a power supply;
a common potential terminal for connecting a common potential;
a power supply end of the mirror image circuit is connected with the power supply terminal, and an input end of the mirror image circuit is connected with a bias current;
a bias circuit connected between an input terminal of the mirror circuit and the common potential terminal, the bias circuit being self-conductive to form the bias current at the input terminal of the mirror circuit, the mirror circuit mirroring the bias current to output a reference current at an output terminal;
the input end of the oscillation unit is connected with the output end of the mirror image circuit, and the oscillation unit is set to oscillate according to the reference current and output an oscillation signal at the output end; and
and the shaping circuit is connected with the power supply terminal, the input end of the mirror image circuit, the common potential terminal, the output end of the oscillation unit and the output terminal, and is used for shaping the oscillation signal to generate a square wave oscillation signal.
In one embodiment, the bias circuit comprises a first transistor and a first load, the first transistor is a Native NMOS transistor with a threshold voltage close to zero voltage or a negative voltage, a drain of the first transistor is connected with an input end of the mirror circuit, a source of the first transistor is connected with a first end of the first load, and a second end of the first load, a gate of the first transistor and a substrate of the transistor are connected with a common potential terminal.
In one embodiment, the mirror circuit includes a second transistor and a third transistor having the same attribute, a first conduction terminal of the second transistor and a first conduction terminal of the third transistor are used as power supply terminals of the mirror circuit, a second conduction terminal of the second transistor is used as an input terminal of the mirror circuit, a second conduction terminal of the third transistor is used as an output terminal of the mirror circuit, and a gate of the second transistor and a gate of the third transistor are connected in common with the second conduction terminal of the second transistor.
In one embodiment, the second transistor and the third transistor are PMOS transistors, the source of the PMOS transistor serves as the first conduction terminal, and the drain of the PMOS transistor serves as the second conduction terminal.
In one embodiment, the first load is at least one of a resistor, a capacitor, an inductor, and a transistor.
In one embodiment, the oscillating unit is a ring oscillating circuit.
In one embodiment, the oscillation unit comprises n inverters connected in series in the same direction between the input terminal and the output terminal of the oscillation unit, and n capacitors connected between two adjacent inverters and the common potential terminal, wherein n is an odd number of 3 or more.
In one embodiment, the inverter includes two transistors cascade-connected between the common potential terminal, the input terminal of the oscillation unit, and the output terminal of the oscillation unit.
In one embodiment, the shaping circuit includes a fourth transistor and a fifth transistor, the fourth transistor is of the same property as the second transistor, a first conduction terminal of the fourth transistor is connected to the power supply terminal, a control terminal of the fourth transistor is connected in common with a control terminal of the second transistor, a second conduction terminal of the fourth transistor is connected in common with a first conduction terminal of the fifth transistor to the output terminal, a control terminal of the fifth transistor is connected to the output terminal of the oscillation unit, and a second conduction terminal of the fifth transistor is connected to the common potential terminal.
A second aspect of embodiments of the present application provides an integrated circuit including the above-described oscillation circuit.
The reference circuit in the oscillating circuit is self-started to form bias current at the input end of the mirror circuit, the mirror bias current of the mirror circuit generates reference current, and the reference current is connected to the oscillating unit to generate oscillating signals and output the oscillating signals through shaping.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a circuit diagram of an oscillating circuit according to an embodiment of the present application;
fig. 2 is an exemplary circuit schematic diagram of a reference circuit in the oscillator circuit shown in fig. 1 for providing a reference current.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, an embodiment of the present invention provides an oscillation circuit that can be integrated in an integrated circuit, including an output terminal CLK, a power supply terminal VCC, a common potential terminal VSS, a mirror circuit 100, a bias circuit 200, an oscillation unit 300, and a shaping circuit 400.
The power supply terminal VCC is for connection to a power supply, and the common potential terminal VSS is for connection to a common potential, such as ground. The power supply terminal of the mirror circuit 100 is connected to a power supply terminal VCC, the input terminal of the mirror circuit 100 is connected to a bias current Iq, and the mirror circuit 100 mirrors the bias current Iq to output a reference current I _uat the output terminalREF(ii) a The bias circuit 200 is connected between the input terminal of the mirror circuit 100 and the common potential terminal VSS, the bias circuit 200 being capable of self-conduction to form a bias current Iq at the input terminal of the mirror circuit 100; the input terminal of the oscillating unit 300 is connected to the output terminal of the mirror circuit 100, and the oscillating unit 300 is configured to be operated according to the reference current I \REFGenerating oscillation and outputting an oscillation signal at an output terminal; the shaping circuit 400 is connected to the power supply terminal VCC, the output terminal of the mirror circuit 100, the common potential terminal VSS, the output terminal of the oscillation unit 300, and the output terminal CLK, and the shaping circuit 400 is configured to shape the oscillation signal to generate a square wave oscillation signal.
Referring to fig. 2, in one embodiment, the bias circuit 200 includes a first transistor 201 and a first load 202, the threshold voltage of the first transistor 201 is close to zero or negative, a first conducting terminal of the first transistor 201 is connected to the input terminal of the mirror circuit 100, a second conducting terminal of the first transistor 201 is connected to the first terminal of the first load 202, a second terminal of the first load 202, the gate of the first transistor 201 and the substrate of the transistor are connected to a common potential terminal VSS, and the bias circuit 200 can be turned on to form a bias current Iq at the input terminal of the mirror circuit 100.
In this embodiment, the first transistor 201 is a Native NMOS transistor NB0, and the drain of the Native NMOS transistor NB0 is used as the first transistorA first turn-on terminal of the Native NMOS transistor NB0 of the first transistor 201, a source of the Native NMOS transistor NB0 having a threshold voltage VT of the Native NMOS transistor NB0NativeNMOSThe voltage is a positive voltage or a negative voltage close to zero, and the voltage can be directly conducted under the condition that the reference circuit is connected with a power supply, and the starting circuit is not required to drive. In other embodiments, the first transistor 201 may be another self-turn-on device. The first load 202 may be an active impedance or a passive impedance, which is illustrated by the passive impedance resistor RB 0. In other embodiments, the first load 202 may be at least one of a resistor, a capacitor, an inductor, a transistor, and the like.
In one embodiment, referring to fig. 2, the mirror circuit 100 includes a second transistor 101 and a third transistor 102 having the same property, a first conduction terminal of the second transistor 101 and a first conduction terminal of the third transistor 102 are used as power terminals of the mirror circuit 100, a second conduction terminal of the second transistor 101 is used as an input terminal of the mirror circuit 100, a second conduction terminal of the third transistor 102 is used as an output terminal of the mirror circuit 100, and a gate of the second transistor 101 and a gate of the third transistor 102 are connected to a second conduction terminal of the second transistor 101. For example, the second transistor 101 and the third transistor 102 constitute a bipolar basic current mirror, a MOS basic current mirror, or a cascade current mirror.
In one embodiment, the second transistor 101 and the third transistor 102 are PMOS transistors PB0 and PB1, the sources of the PMOS transistors PB0 and PB1 are first conduction terminals, and the drains of the PMOS transistors PB0 and PB1 are second conduction terminals.
The reference circuit acts on a resistor RB0 through the source end of a Native NMOS tube NB0 with the grid grounded, and the threshold voltage VT of the Native NMOS tube NB0 is utilizedNative NMOSNear zero or negative characteristics, resulting in a bias current Iq. The reference current I _uwith different magnitudes is generated by the PMOS tube PB1 mirror bias current IqREF1，I_REF1N — Iq (n — 1,2,3 …), specifically, a bias current Iq and a reference current I \uREF1Respectively as follows:
IREF1＝n*Iq
in one embodiment, the oscillating unit 300 is a ring oscillating circuit. Referring to fig. 2, the oscillation unit 300 includes n inverters 301 connected in series in the same direction between the input terminal and the output terminal of the oscillation unit 300, and n capacitors CB0 connected between two adjacent inverters 301 and the common potential terminal VSS, where n is an odd number of 3 or more, and in this embodiment n is 3.
Each inverter 301 includes two transistors cascade-connected between the common potential terminal VSS, the input terminal of the oscillation unit 300, and the output terminal of the oscillation unit 300. Specifically, one of the two transistors is a PMOS transistor PB3, the other is an NMOS transistor NB1, the source of the PMOS transistor PB3 in each inverter 301 is commonly connected as the input terminal of the oscillation unit 300 and is connected to the output terminal of the mirror circuit 100, the gates of the PMOS transistor PB3 and the NMOS transistor NB1 in each inverter 301 are commonly connected to a first node, the drains of the PMOS transistor PB3 and the NMOS transistor NB1 in each inverter 301 are commonly connected to a second node, the second node of each inverter 301 and the first node of the adjacent inverter 301 are commonly connected to a first terminal of a capacitor, and the other terminal of the capacitor and the source of the NMOS transistor NB1 in each inverter 301 are commonly connected to a common potential terminal VSS, which uses one of the first nodes as the output terminal of the oscillation unit 300. The oscillating unit 300 passes a reference current IREFThe circuit formed by the three-level inverter 301 and the capacitor is charged and discharged, so that the ring-shaped oscillation unit 300 oscillates to generate an oscillation signal.
The shaping circuit 400 includes a fourth transistor PB2 and a fifth transistor NB2, the fourth transistor PB2 and the second transistor PB0 have the same attribute, a first conduction terminal of the fourth transistor PB2 is connected to the power supply terminal VCC, a control terminal of the fourth transistor PB2 is connected in common with a control terminal of the second transistor PB0, a second conduction terminal of the fourth transistor PB2 is connected in common with a first conduction terminal of the fifth transistor NB2 to the output terminal CLK, a control terminal of the fifth transistor NB2 is connected to the output terminal of the oscillation unit 300, and a second conduction terminal of the fifth transistor NB2 is connected to the common potential terminal VSS. In this embodiment, the fourth transistor PB2 and the second transistor PB0 form a mirror circuitThe PMOS tube mirror image bias current Iq generates reference current I _withdifferent magnitudesREF2，I_REF2I ═ m × Iq (m ═ 1,2,3 …), specifically, bias current Iq and reference current I \u \REF2Respectively as follows:
IREF2＝m*Iq
the current mirrored by the PMOS device PB2 is limited, the fifth transistor NB2 is an NMOS transistor, the NMOS transistor shapes the oscillation signal to generate a square wave oscillation signal, and the power consumption and the oscillation frequency formula of the circuit are as follows:
Itotal＝(m+n+1)*Iq
wherein, VGSNIs the gate-source voltage of the NMOS tube NB 1; c is the capacitance value of the capacitor CB 0.
Under the condition that a power supply is added to the oscillating circuit, the reference circuit can be only stabilized in a normal working state without a starting circuit; the current reference circuit has a simple structure; the circuit power consumption is known to be low. The oscillation frequency formula shows that the frequency adjustment is convenient, and the oscillation frequency can be flexibly adjusted by adjusting the value of the bias current n × Iq.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An oscillating circuit, comprising:
an output terminal;
the power supply terminal is used for accessing a power supply;
a common potential terminal for connecting a common potential;
a power supply end of the mirror image circuit is connected with the power supply terminal, and an input end of the mirror image circuit is connected with a bias current;
a bias circuit connected between an input terminal of the mirror circuit and the common potential terminal, the bias circuit being self-conductive to form the bias current at the input terminal of the mirror circuit, the mirror circuit mirroring the bias current to output a reference current at an output terminal;
the input end of the oscillation unit is connected with the output end of the mirror image circuit, and the oscillation unit is set to oscillate according to the reference current and output an oscillation signal at the output end; and
and the shaping circuit is connected with the power supply terminal, the input end of the mirror image circuit, the common potential terminal, the output end of the oscillation unit and the output terminal, and is used for shaping the oscillation signal to generate a square wave oscillation signal.
2. The oscillator circuit according to claim 1, wherein the bias circuit comprises a first transistor and a first load, the first transistor is a Native NMOS transistor with a threshold voltage close to zero or a negative voltage, a drain of the first transistor is connected to the input terminal of the mirror circuit, a source of the first transistor is connected to a first terminal of the first load, and a second terminal of the first load, a gate of the first transistor and a substrate of the transistor are connected to a common potential terminal.
3. The oscillation circuit according to claim 1, wherein the mirror circuit includes a second transistor and a third transistor having the same attribute, a first conductive terminal of the second transistor and a first conductive terminal of the third transistor are power source terminals of the mirror circuit, a second conductive terminal of the second transistor is an input terminal of the mirror circuit, a second conductive terminal of the third transistor is an output terminal of the mirror circuit, and a gate of the second transistor and a gate of the third transistor are connected in common with a second conductive terminal of the second transistor.
4. The oscillator circuit according to claim 3, wherein the second transistor and the third transistor are PMOS transistors, and a source of the PMOS transistor serves as the first conduction terminal and a drain of the PMOS transistor serves as the second conduction terminal.
5. The oscillating circuit of claim 2, wherein the first load is at least one of a resistor, a capacitor, an inductor, and a transistor.
6. The oscillation circuit according to claim 1, wherein the oscillation unit is a ring oscillation circuit.
7. The oscillation circuit according to any one of claims 1 to 6, wherein the oscillation element comprises n inverters connected in series in the same direction between the input terminal and the output terminal of the oscillation element, and n capacitors connected between adjacent two inverters and a common potential terminal, n being an odd number of 3 or more.
8. The oscillation circuit according to claim 7, wherein the inverter includes two transistors cascade-connected between a common potential terminal, an input terminal of the oscillation unit, and an output terminal of the oscillation unit.
9. The oscillation circuit according to claim 3, wherein the shaping circuit includes a fourth transistor and a fifth transistor, the fourth transistor being in common with the second transistor, a first conduction terminal of the fourth transistor being connected to the power supply terminal, a control terminal of the fourth transistor being in common with a control terminal of the second transistor, a second conduction terminal of the fourth transistor being in common with a first conduction terminal of the fifth transistor being connected to the output terminal, a control terminal of the fifth transistor being connected to the output terminal of the oscillation unit, and a second conduction terminal of the fifth transistor being connected to the common potential terminal.
10. An integrated circuit comprising the oscillating circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921080888.9U CN210431389U (en) | 2019-07-10 | 2019-07-10 | Oscillator circuit and integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921080888.9U CN210431389U (en) | 2019-07-10 | 2019-07-10 | Oscillator circuit and integrated circuit |
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| CN210431389U true CN210431389U (en) | 2020-04-28 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110336558A (en) * | 2019-07-10 | 2019-10-15 | 深圳市锐能微科技有限公司 | Oscillating circuit and integrated circuit |
| CN112117993A (en) * | 2020-09-18 | 2020-12-22 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillation circuit |
| CN112422086A (en) * | 2020-12-15 | 2021-02-26 | 深圳市芯天下技术有限公司 | Oscillator circuit and flash chip |
-
2019
- 2019-07-10 CN CN201921080888.9U patent/CN210431389U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110336558A (en) * | 2019-07-10 | 2019-10-15 | 深圳市锐能微科技有限公司 | Oscillating circuit and integrated circuit |
| CN110336558B (en) * | 2019-07-10 | 2024-02-13 | 深圳市锐能微科技有限公司 | Oscillator circuit and integrated circuit |
| CN112117993A (en) * | 2020-09-18 | 2020-12-22 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillation circuit |
| CN112117993B (en) * | 2020-09-18 | 2024-03-01 | 上海艾为电子技术股份有限公司 | Shaping circuit and oscillating circuit |
| CN112422086A (en) * | 2020-12-15 | 2021-02-26 | 深圳市芯天下技术有限公司 | Oscillator circuit and flash chip |
| CN112422086B (en) * | 2020-12-15 | 2022-02-18 | 芯天下技术股份有限公司 | Oscillator circuit and flash chip |
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